// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
*
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/regmap.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt2712.h"
static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(18 , 0 xe50, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(19 , 0 xe60, 12 , 11 , 10 ),
MTK_PIN_PUPD_SPEC_SR(20 , 0 xe50, 5 , 4 , 3 ),
MTK_PIN_PUPD_SPEC_SR(21 , 0 xe60, 15 , 14 , 13 ),
MTK_PIN_PUPD_SPEC_SR(22 , 0 xe50, 8 , 7 , 6 ),
MTK_PIN_PUPD_SPEC_SR(23 , 0 xe70, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(30 , 0 xf30, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(31 , 0 xf30, 6 , 5 , 4 ),
MTK_PIN_PUPD_SPEC_SR(32 , 0 xf30, 10 , 9 , 8 ),
MTK_PIN_PUPD_SPEC_SR(33 , 0 xf30, 14 , 13 , 12 ),
MTK_PIN_PUPD_SPEC_SR(34 , 0 xf40, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(35 , 0 xf40, 6 , 5 , 4 ),
MTK_PIN_PUPD_SPEC_SR(36 , 0 xf40, 10 , 9 , 8 ),
MTK_PIN_PUPD_SPEC_SR(37 , 0 xc40, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(38 , 0 xc60, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(39 , 0 xc60, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(40 , 0 xc60, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(41 , 0 xc60, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(42 , 0 xc60, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(43 , 0 xc60, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(44 , 0 xc60, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(45 , 0 xc60, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(46 , 0 xc50, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(47 , 0 xda0, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(48 , 0 xd90, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(49 , 0 xdf0, 14 , 13 , 12 ),
MTK_PIN_PUPD_SPEC_SR(50 , 0 xdf0, 10 , 9 , 8 ),
MTK_PIN_PUPD_SPEC_SR(51 , 0 xdf0, 6 , 5 , 4 ),
MTK_PIN_PUPD_SPEC_SR(52 , 0 xdf0, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(53 , 0 xd50, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(54 , 0 xd80, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(55 , 0 xe00, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(56 , 0 xd40, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(63 , 0 xc80, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(64 , 0 xdb0, 14 , 13 , 12 ),
MTK_PIN_PUPD_SPEC_SR(65 , 0 xdb0, 6 , 5 , 4 ),
MTK_PIN_PUPD_SPEC_SR(66 , 0 xdb0, 10 , 9 , 8 ),
MTK_PIN_PUPD_SPEC_SR(67 , 0 xcd0, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(68 , 0 xdb0, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(69 , 0 xc90, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(70 , 0 xcc0, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(89 , 0 xce0, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(90 , 0 xdd0, 14 , 13 , 12 ),
MTK_PIN_PUPD_SPEC_SR(91 , 0 xdd0, 10 , 9 , 8 ),
MTK_PIN_PUPD_SPEC_SR(92 , 0 xdd0, 6 , 5 , 4 ),
MTK_PIN_PUPD_SPEC_SR(93 , 0 xdd0, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(94 , 0 xd20, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(95 , 0 xcf0, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(96 , 0 xd30, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(135 , 0 xe50, 11 , 10 , 9 ),
MTK_PIN_PUPD_SPEC_SR(136 , 0 xe50, 14 , 13 , 12 ),
MTK_PIN_PUPD_SPEC_SR(137 , 0 xe70, 5 , 4 , 3 ),
MTK_PIN_PUPD_SPEC_SR(138 , 0 xe70, 8 , 7 , 6 ),
MTK_PIN_PUPD_SPEC_SR(139 , 0 xe70, 11 , 10 , 9 ),
MTK_PIN_PUPD_SPEC_SR(140 , 0 xe70, 14 , 13 , 12 ),
MTK_PIN_PUPD_SPEC_SR(141 , 0 xe60, 2 , 1 , 0 ),
MTK_PIN_PUPD_SPEC_SR(142 , 0 xe60, 5 , 4 , 3 )
};
static const struct mtk_pin_ies_smt_set mt2712_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0 , 3 , 0 x900, 2 ),
MTK_PIN_IES_SMT_SPEC(4 , 7 , 0 x900, 0 ),
MTK_PIN_IES_SMT_SPEC(8 , 11 , 0 x900, 1 ),
MTK_PIN_IES_SMT_SPEC(12 , 12 , 0 x8d0, 6 ),
MTK_PIN_IES_SMT_SPEC(13 , 13 , 0 x8d0, 7 ),
MTK_PIN_IES_SMT_SPEC(14 , 14 , 0 x8d0, 6 ),
MTK_PIN_IES_SMT_SPEC(15 , 15 , 0 x8d0, 7 ),
MTK_PIN_IES_SMT_SPEC(18 , 23 , 0 x8d0, 1 ),
MTK_PIN_IES_SMT_SPEC(24 , 25 , 0 x8d0, 2 ),
MTK_PIN_IES_SMT_SPEC(26 , 26 , 0 x8d0, 3 ),
MTK_PIN_IES_SMT_SPEC(27 , 27 , 0 x8d0, 4 ),
MTK_PIN_IES_SMT_SPEC(28 , 29 , 0 x8d0, 3 ),
MTK_PIN_IES_SMT_SPEC(30 , 36 , 0 xf50, 13 ),
MTK_PIN_IES_SMT_SPEC(37 , 37 , 0 xc40, 13 ),
MTK_PIN_IES_SMT_SPEC(38 , 45 , 0 xc60, 13 ),
MTK_PIN_IES_SMT_SPEC(46 , 46 , 0 xc50, 13 ),
MTK_PIN_IES_SMT_SPEC(47 , 47 , 0 xda0, 13 ),
MTK_PIN_IES_SMT_SPEC(48 , 48 , 0 xd90, 13 ),
MTK_PIN_IES_SMT_SPEC(49 , 52 , 0 xd60, 13 ),
MTK_PIN_IES_SMT_SPEC(53 , 53 , 0 xd50, 13 ),
MTK_PIN_IES_SMT_SPEC(54 , 54 , 0 xd80, 13 ),
MTK_PIN_IES_SMT_SPEC(55 , 55 , 0 xe00, 13 ),
MTK_PIN_IES_SMT_SPEC(56 , 56 , 0 xd40, 13 ),
MTK_PIN_IES_SMT_SPEC(57 , 62 , 0 x900, 3 ),
MTK_PIN_IES_SMT_SPEC(63 , 63 , 0 xc80, 13 ),
MTK_PIN_IES_SMT_SPEC(64 , 66 , 0 xca0, 13 ),
MTK_PIN_IES_SMT_SPEC(67 , 67 , 0 xc80, 13 ),
MTK_PIN_IES_SMT_SPEC(68 , 68 , 0 xca0, 13 ),
MTK_PIN_IES_SMT_SPEC(69 , 69 , 0 xc90, 13 ),
MTK_PIN_IES_SMT_SPEC(70 , 70 , 0 xc80, 13 ),
MTK_PIN_IES_SMT_SPEC(71 , 74 , 0 x8d0, 8 ),
MTK_PIN_IES_SMT_SPEC(75 , 77 , 0 x8d0, 9 ),
MTK_PIN_IES_SMT_SPEC(78 , 81 , 0 x8d0, 10 ),
MTK_PIN_IES_SMT_SPEC(82 , 88 , 0 x8d0, 9 ),
MTK_PIN_IES_SMT_SPEC(89 , 89 , 0 xce0, 13 ),
MTK_PIN_IES_SMT_SPEC(90 , 93 , 0 xd00, 13 ),
MTK_PIN_IES_SMT_SPEC(94 , 94 , 0 xce0, 13 ),
MTK_PIN_IES_SMT_SPEC(95 , 96 , 0 xcf0, 13 ),
MTK_PIN_IES_SMT_SPEC(97 , 100 , 0 x8d0, 11 ),
MTK_PIN_IES_SMT_SPEC(101 , 104 , 0 x8d0, 12 ),
MTK_PIN_IES_SMT_SPEC(105 , 105 , 0 x8d0, 13 ),
MTK_PIN_IES_SMT_SPEC(106 , 106 , 0 x8d0, 14 ),
MTK_PIN_IES_SMT_SPEC(107 , 107 , 0 x8d0, 15 ),
MTK_PIN_IES_SMT_SPEC(108 , 108 , 0 x8e0, 0 ),
MTK_PIN_IES_SMT_SPEC(109 , 109 , 0 x8e0, 1 ),
MTK_PIN_IES_SMT_SPEC(110 , 110 , 0 x8e0, 2 ),
MTK_PIN_IES_SMT_SPEC(111 , 111 , 0 x8d0, 13 ),
MTK_PIN_IES_SMT_SPEC(112 , 112 , 0 x8d0, 14 ),
MTK_PIN_IES_SMT_SPEC(113 , 113 , 0 x8d0, 15 ),
MTK_PIN_IES_SMT_SPEC(114 , 114 , 0 x8e0, 0 ),
MTK_PIN_IES_SMT_SPEC(115 , 115 , 0 x8e0, 1 ),
MTK_PIN_IES_SMT_SPEC(116 , 116 , 0 x8e0, 2 ),
MTK_PIN_IES_SMT_SPEC(117 , 117 , 0 x8e0, 3 ),
MTK_PIN_IES_SMT_SPEC(118 , 118 , 0 x8e0, 4 ),
MTK_PIN_IES_SMT_SPEC(119 , 119 , 0 x8e0, 5 ),
MTK_PIN_IES_SMT_SPEC(120 , 120 , 0 x8e0, 3 ),
MTK_PIN_IES_SMT_SPEC(121 , 121 , 0 x8e0, 4 ),
MTK_PIN_IES_SMT_SPEC(122 , 122 , 0 x8e0, 5 ),
MTK_PIN_IES_SMT_SPEC(123 , 126 , 0 x8e0, 6 ),
MTK_PIN_IES_SMT_SPEC(127 , 130 , 0 x8e0, 7 ),
MTK_PIN_IES_SMT_SPEC(131 , 134 , 0 x8e0, 8 ),
MTK_PIN_IES_SMT_SPEC(135 , 142 , 0 x8d0, 1 ),
MTK_PIN_IES_SMT_SPEC(143 , 147 , 0 x8e0, 9 ),
MTK_PIN_IES_SMT_SPEC(148 , 152 , 0 x8e0, 10 ),
MTK_PIN_IES_SMT_SPEC(153 , 156 , 0 x8e0, 11 ),
MTK_PIN_IES_SMT_SPEC(157 , 160 , 0 x8e0, 12 ),
MTK_PIN_IES_SMT_SPEC(161 , 164 , 0 x8e0, 13 ),
MTK_PIN_IES_SMT_SPEC(165 , 168 , 0 x8e0, 14 ),
MTK_PIN_IES_SMT_SPEC(169 , 170 , 0 x8e0, 15 ),
MTK_PIN_IES_SMT_SPEC(171 , 172 , 0 x8f0, 0 ),
MTK_PIN_IES_SMT_SPEC(173 , 173 , 0 x8f0, 1 ),
MTK_PIN_IES_SMT_SPEC(174 , 175 , 0 x8f0, 2 ),
MTK_PIN_IES_SMT_SPEC(176 , 176 , 0 x8f0, 1 ),
MTK_PIN_IES_SMT_SPEC(177 , 177 , 0 x8f0, 3 ),
MTK_PIN_IES_SMT_SPEC(178 , 178 , 0 x8f0, 4 ),
MTK_PIN_IES_SMT_SPEC(179 , 179 , 0 x8f0, 3 ),
MTK_PIN_IES_SMT_SPEC(180 , 180 , 0 x8f0, 4 ),
MTK_PIN_IES_SMT_SPEC(181 , 181 , 0 x8f0, 5 ),
MTK_PIN_IES_SMT_SPEC(182 , 182 , 0 x8f0, 6 ),
MTK_PIN_IES_SMT_SPEC(183 , 183 , 0 x8f0, 5 ),
MTK_PIN_IES_SMT_SPEC(184 , 184 , 0 x8f0, 6 ),
MTK_PIN_IES_SMT_SPEC(185 , 186 , 0 x8f0, 7 ),
MTK_PIN_IES_SMT_SPEC(187 , 187 , 0 x8f0, 8 ),
MTK_PIN_IES_SMT_SPEC(188 , 188 , 0 x8f0, 9 ),
MTK_PIN_IES_SMT_SPEC(189 , 189 , 0 x8f0, 8 ),
MTK_PIN_IES_SMT_SPEC(190 , 190 , 0 x8f0, 9 ),
MTK_PIN_IES_SMT_SPEC(191 , 191 , 0 x8f0, 10 ),
MTK_PIN_IES_SMT_SPEC(192 , 192 , 0 x8f0, 11 ),
MTK_PIN_IES_SMT_SPEC(193 , 194 , 0 x8f0, 10 ),
MTK_PIN_IES_SMT_SPEC(195 , 195 , 0 x8f0, 11 ),
MTK_PIN_IES_SMT_SPEC(196 , 199 , 0 x8f0, 12 ),
MTK_PIN_IES_SMT_SPEC(200 , 203 , 0 x8f0, 13 ),
MTK_PIN_IES_SMT_SPEC(204 , 206 , 0 x8f0, 14 ),
MTK_PIN_IES_SMT_SPEC(207 , 209 , 0 x8f0, 15 )
};
static const struct mtk_pin_ies_smt_set mt2712_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0 , 3 , 0 x8c0, 2 ),
MTK_PIN_IES_SMT_SPEC(4 , 7 , 0 x8c0, 0 ),
MTK_PIN_IES_SMT_SPEC(8 , 9 , 0 x8c0, 1 ),
MTK_PIN_IES_SMT_SPEC(10 , 11 , 0 x8c0, 4 ),
MTK_PIN_IES_SMT_SPEC(12 , 12 , 0 x890, 6 ),
MTK_PIN_IES_SMT_SPEC(13 , 13 , 0 x890, 7 ),
MTK_PIN_IES_SMT_SPEC(14 , 14 , 0 x890, 6 ),
MTK_PIN_IES_SMT_SPEC(15 , 15 , 0 x890, 7 ),
MTK_PIN_IES_SMT_SPEC(18 , 23 , 0 x890, 1 ),
MTK_PIN_IES_SMT_SPEC(24 , 25 , 0 x890, 2 ),
MTK_PIN_IES_SMT_SPEC(26 , 26 , 0 x890, 3 ),
MTK_PIN_IES_SMT_SPEC(27 , 27 , 0 x890, 4 ),
MTK_PIN_IES_SMT_SPEC(28 , 29 , 0 x890, 3 ),
MTK_PIN_IES_SMT_SPEC(30 , 36 , 0 xf50, 14 ),
MTK_PIN_IES_SMT_SPEC(37 , 37 , 0 xc40, 14 ),
MTK_PIN_IES_SMT_SPEC(38 , 45 , 0 xc60, 14 ),
MTK_PIN_IES_SMT_SPEC(46 , 46 , 0 xc50, 14 ),
MTK_PIN_IES_SMT_SPEC(47 , 47 , 0 xda0, 14 ),
MTK_PIN_IES_SMT_SPEC(48 , 48 , 0 xd90, 14 ),
MTK_PIN_IES_SMT_SPEC(49 , 52 , 0 xd60, 14 ),
MTK_PIN_IES_SMT_SPEC(53 , 53 , 0 xd50, 14 ),
MTK_PIN_IES_SMT_SPEC(54 , 54 , 0 xd80, 14 ),
MTK_PIN_IES_SMT_SPEC(55 , 55 , 0 xe00, 14 ),
MTK_PIN_IES_SMT_SPEC(56 , 56 , 0 xd40, 14 ),
MTK_PIN_IES_SMT_SPEC(57 , 62 , 0 x8c0, 3 ),
MTK_PIN_IES_SMT_SPEC(63 , 63 , 0 xc80, 14 ),
MTK_PIN_IES_SMT_SPEC(64 , 66 , 0 xca0, 14 ),
MTK_PIN_IES_SMT_SPEC(67 , 68 , 0 xc80, 14 ),
MTK_PIN_IES_SMT_SPEC(69 , 69 , 0 xc90, 14 ),
MTK_PIN_IES_SMT_SPEC(70 , 70 , 0 xc80, 14 ),
MTK_PIN_IES_SMT_SPEC(71 , 74 , 0 x890, 8 ),
MTK_PIN_IES_SMT_SPEC(75 , 77 , 0 x890, 9 ),
MTK_PIN_IES_SMT_SPEC(78 , 81 , 0 x890, 10 ),
MTK_PIN_IES_SMT_SPEC(82 , 88 , 0 x890, 9 ),
MTK_PIN_IES_SMT_SPEC(89 , 89 , 0 xce0, 14 ),
MTK_PIN_IES_SMT_SPEC(90 , 93 , 0 xd00, 14 ),
MTK_PIN_IES_SMT_SPEC(94 , 94 , 0 xce0, 14 ),
MTK_PIN_IES_SMT_SPEC(95 , 96 , 0 xcf0, 14 ),
MTK_PIN_IES_SMT_SPEC(97 , 100 , 0 x890, 11 ),
MTK_PIN_IES_SMT_SPEC(101 , 104 , 0 x890, 12 ),
MTK_PIN_IES_SMT_SPEC(105 , 105 , 0 x890, 13 ),
MTK_PIN_IES_SMT_SPEC(106 , 106 , 0 x890, 14 ),
MTK_PIN_IES_SMT_SPEC(107 , 107 , 0 x890, 15 ),
MTK_PIN_IES_SMT_SPEC(108 , 108 , 0 x8a0, 0 ),
MTK_PIN_IES_SMT_SPEC(109 , 109 , 0 x8a0, 1 ),
MTK_PIN_IES_SMT_SPEC(110 , 110 , 0 x8a0, 2 ),
MTK_PIN_IES_SMT_SPEC(111 , 111 , 0 x890, 13 ),
MTK_PIN_IES_SMT_SPEC(112 , 112 , 0 x890, 14 ),
MTK_PIN_IES_SMT_SPEC(113 , 113 , 0 x890, 15 ),
MTK_PIN_IES_SMT_SPEC(114 , 114 , 0 x8a0, 0 ),
MTK_PIN_IES_SMT_SPEC(115 , 115 , 0 x8a0, 1 ),
MTK_PIN_IES_SMT_SPEC(116 , 116 , 0 x8a0, 2 ),
MTK_PIN_IES_SMT_SPEC(117 , 117 , 0 x8a0, 3 ),
MTK_PIN_IES_SMT_SPEC(118 , 118 , 0 x8a0, 4 ),
MTK_PIN_IES_SMT_SPEC(119 , 119 , 0 x8a0, 5 ),
MTK_PIN_IES_SMT_SPEC(120 , 120 , 0 x8a0, 3 ),
MTK_PIN_IES_SMT_SPEC(121 , 121 , 0 x8a0, 4 ),
MTK_PIN_IES_SMT_SPEC(122 , 122 , 0 x8a0, 5 ),
MTK_PIN_IES_SMT_SPEC(123 , 126 , 0 x8a0, 6 ),
MTK_PIN_IES_SMT_SPEC(127 , 130 , 0 x8a0, 7 ),
MTK_PIN_IES_SMT_SPEC(131 , 135 , 0 x8a0, 8 ),
MTK_PIN_IES_SMT_SPEC(136 , 142 , 0 x890, 1 ),
MTK_PIN_IES_SMT_SPEC(143 , 147 , 0 x8a0, 9 ),
MTK_PIN_IES_SMT_SPEC(148 , 152 , 0 x8a0, 10 ),
MTK_PIN_IES_SMT_SPEC(153 , 156 , 0 x8a0, 11 ),
MTK_PIN_IES_SMT_SPEC(157 , 160 , 0 x8a0, 12 ),
MTK_PIN_IES_SMT_SPEC(161 , 164 , 0 x8a0, 13 ),
MTK_PIN_IES_SMT_SPEC(165 , 168 , 0 x8a0, 14 ),
MTK_PIN_IES_SMT_SPEC(169 , 170 , 0 x8a0, 15 ),
MTK_PIN_IES_SMT_SPEC(171 , 172 , 0 x8b0, 0 ),
MTK_PIN_IES_SMT_SPEC(173 , 173 , 0 x8b0, 1 ),
MTK_PIN_IES_SMT_SPEC(174 , 175 , 0 x8b0, 2 ),
MTK_PIN_IES_SMT_SPEC(176 , 176 , 0 x8b0, 1 ),
MTK_PIN_IES_SMT_SPEC(177 , 177 , 0 x8b0, 3 ),
MTK_PIN_IES_SMT_SPEC(178 , 178 , 0 x8b0, 4 ),
MTK_PIN_IES_SMT_SPEC(179 , 179 , 0 x8b0, 3 ),
MTK_PIN_IES_SMT_SPEC(180 , 180 , 0 x8b0, 4 ),
MTK_PIN_IES_SMT_SPEC(181 , 181 , 0 x8b0, 5 ),
MTK_PIN_IES_SMT_SPEC(182 , 182 , 0 x8b0, 6 ),
MTK_PIN_IES_SMT_SPEC(183 , 183 , 0 x8b0, 5 ),
MTK_PIN_IES_SMT_SPEC(184 , 184 , 0 x8b0, 6 ),
MTK_PIN_IES_SMT_SPEC(185 , 186 , 0 x8b0, 7 ),
MTK_PIN_IES_SMT_SPEC(187 , 187 , 0 x8b0, 8 ),
MTK_PIN_IES_SMT_SPEC(188 , 188 , 0 x8b0, 9 ),
MTK_PIN_IES_SMT_SPEC(189 , 189 , 0 x8b0, 8 ),
MTK_PIN_IES_SMT_SPEC(190 , 190 , 0 x8b0, 9 ),
MTK_PIN_IES_SMT_SPEC(191 , 191 , 0 x8b0, 10 ),
MTK_PIN_IES_SMT_SPEC(192 , 192 , 0 x8b0, 11 ),
MTK_PIN_IES_SMT_SPEC(193 , 194 , 0 x8b0, 10 ),
MTK_PIN_IES_SMT_SPEC(195 , 195 , 0 x8b0, 11 ),
MTK_PIN_IES_SMT_SPEC(196 , 199 , 0 x8b0, 12 ),
MTK_PIN_IES_SMT_SPEC(200 , 203 , 0 x8b0, 13 ),
MTK_PIN_IES_SMT_SPEC(204 , 206 , 0 x8b0, 14 ),
MTK_PIN_IES_SMT_SPEC(207 , 209 , 0 x8b0, 15 )
};
static const struct mtk_drv_group_desc mt2712_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4 , 16 , 1 , 2 , 4 ),
/* 0E2E4SR 2/4/6/8 */
MTK_DRV_GRP(2 , 8 , 1 , 2 , 2 ),
/* E8E4E2 2/4/6/8/10/12/14/16 */
MTK_DRV_GRP(2 , 16 , 0 , 2 , 2 )
};
static const struct mtk_pin_drv_grp mt2712_pin_drv[] = {
MTK_PIN_DRV_GRP(0 , 0 xc10, 4 , 0 ),
MTK_PIN_DRV_GRP(1 , 0 xc10, 4 , 0 ),
MTK_PIN_DRV_GRP(2 , 0 xc10, 4 , 0 ),
MTK_PIN_DRV_GRP(3 , 0 xc10, 4 , 0 ),
MTK_PIN_DRV_GRP(4 , 0 xc00, 12 , 0 ),
MTK_PIN_DRV_GRP(5 , 0 xc00, 12 , 0 ),
MTK_PIN_DRV_GRP(6 , 0 xc00, 12 , 0 ),
MTK_PIN_DRV_GRP(7 , 0 xc00, 12 , 0 ),
MTK_PIN_DRV_GRP(8 , 0 xc10, 0 , 0 ),
MTK_PIN_DRV_GRP(9 , 0 xc10, 0 , 0 ),
MTK_PIN_DRV_GRP(10 , 0 xc10, 0 , 0 ),
MTK_PIN_DRV_GRP(11 , 0 xc10, 0 , 0 ),
MTK_PIN_DRV_GRP(12 , 0 xb60, 0 , 0 ),
MTK_PIN_DRV_GRP(13 , 0 xb60, 4 , 0 ),
MTK_PIN_DRV_GRP(14 , 0 xb60, 0 , 0 ),
MTK_PIN_DRV_GRP(15 , 0 xb60, 4 , 0 ),
MTK_PIN_DRV_GRP(18 , 0 xb40, 0 , 1 ),
MTK_PIN_DRV_GRP(19 , 0 xb40, 0 , 1 ),
MTK_PIN_DRV_GRP(20 , 0 xb40, 0 , 1 ),
MTK_PIN_DRV_GRP(21 , 0 xb40, 0 , 1 ),
MTK_PIN_DRV_GRP(22 , 0 xb40, 0 , 1 ),
MTK_PIN_DRV_GRP(23 , 0 xb40, 0 , 1 ),
MTK_PIN_DRV_GRP(24 , 0 xb40, 4 , 0 ),
MTK_PIN_DRV_GRP(25 , 0 xb40, 8 , 0 ),
MTK_PIN_DRV_GRP(26 , 0 xb40, 12 , 0 ),
MTK_PIN_DRV_GRP(27 , 0 xb50, 0 , 0 ),
MTK_PIN_DRV_GRP(28 , 0 xb40, 12 , 0 ),
MTK_PIN_DRV_GRP(29 , 0 xb40, 12 , 0 ),
MTK_PIN_DRV_GRP(30 , 0 xf50, 8 , 2 ),
MTK_PIN_DRV_GRP(31 , 0 xf50, 8 , 2 ),
MTK_PIN_DRV_GRP(32 , 0 xf50, 8 , 2 ),
MTK_PIN_DRV_GRP(33 , 0 xf50, 8 , 2 ),
MTK_PIN_DRV_GRP(34 , 0 xf50, 8 , 2 ),
MTK_PIN_DRV_GRP(35 , 0 xf50, 8 , 2 ),
MTK_PIN_DRV_GRP(36 , 0 xf50, 8 , 2 ),
MTK_PIN_DRV_GRP(37 , 0 xc40, 8 , 2 ),
MTK_PIN_DRV_GRP(38 , 0 xc60, 8 , 2 ),
MTK_PIN_DRV_GRP(39 , 0 xc60, 8 , 2 ),
MTK_PIN_DRV_GRP(40 , 0 xc60, 8 , 2 ),
MTK_PIN_DRV_GRP(41 , 0 xc60, 8 , 2 ),
MTK_PIN_DRV_GRP(42 , 0 xc60, 8 , 2 ),
MTK_PIN_DRV_GRP(43 , 0 xc60, 8 , 2 ),
MTK_PIN_DRV_GRP(44 , 0 xc60, 8 , 2 ),
MTK_PIN_DRV_GRP(45 , 0 xc60, 8 , 2 ),
MTK_PIN_DRV_GRP(46 , 0 xc50, 8 , 2 ),
MTK_PIN_DRV_GRP(47 , 0 xda0, 8 , 2 ),
MTK_PIN_DRV_GRP(48 , 0 xd90, 8 , 2 ),
MTK_PIN_DRV_GRP(49 , 0 xd60, 8 , 2 ),
MTK_PIN_DRV_GRP(50 , 0 xd60, 8 , 2 ),
MTK_PIN_DRV_GRP(51 , 0 xd60, 8 , 2 ),
MTK_PIN_DRV_GRP(52 , 0 xd60, 8 , 2 ),
MTK_PIN_DRV_GRP(53 , 0 xd50, 8 , 2 ),
MTK_PIN_DRV_GRP(54 , 0 xd80, 8 , 2 ),
MTK_PIN_DRV_GRP(55 , 0 xe00, 8 , 2 ),
MTK_PIN_DRV_GRP(56 , 0 xd40, 8 , 2 ),
MTK_PIN_DRV_GRP(63 , 0 xc80, 8 , 2 ),
MTK_PIN_DRV_GRP(64 , 0 xca0, 8 , 2 ),
MTK_PIN_DRV_GRP(65 , 0 xca0, 8 , 2 ),
MTK_PIN_DRV_GRP(66 , 0 xca0, 8 , 2 ),
MTK_PIN_DRV_GRP(67 , 0 xcd0, 8 , 2 ),
MTK_PIN_DRV_GRP(68 , 0 xca0, 8 , 2 ),
MTK_PIN_DRV_GRP(69 , 0 xc90, 8 , 2 ),
MTK_PIN_DRV_GRP(70 , 0 xcc0, 8 , 2 ),
MTK_PIN_DRV_GRP(71 , 0 xb60, 8 , 1 ),
MTK_PIN_DRV_GRP(72 , 0 xb60, 8 , 1 ),
MTK_PIN_DRV_GRP(73 , 0 xb60, 8 , 1 ),
MTK_PIN_DRV_GRP(74 , 0 xb60, 8 , 1 ),
MTK_PIN_DRV_GRP(75 , 0 xb60, 12 , 1 ),
MTK_PIN_DRV_GRP(76 , 0 xb60, 12 , 1 ),
MTK_PIN_DRV_GRP(77 , 0 xb60, 12 , 1 ),
MTK_PIN_DRV_GRP(78 , 0 xb70, 0 , 1 ),
MTK_PIN_DRV_GRP(79 , 0 xb70, 0 , 1 ),
MTK_PIN_DRV_GRP(80 , 0 xb70, 0 , 1 ),
MTK_PIN_DRV_GRP(81 , 0 xb70, 0 , 1 ),
MTK_PIN_DRV_GRP(82 , 0 xb60, 12 , 1 ),
MTK_PIN_DRV_GRP(83 , 0 xb60, 12 , 1 ),
MTK_PIN_DRV_GRP(84 , 0 xb60, 12 , 1 ),
MTK_PIN_DRV_GRP(85 , 0 xb60, 12 , 1 ),
MTK_PIN_DRV_GRP(86 , 0 xb60, 12 , 1 ),
MTK_PIN_DRV_GRP(87 , 0 xb60, 12 , 1 ),
MTK_PIN_DRV_GRP(88 , 0 xb60, 12 , 1 ),
MTK_PIN_DRV_GRP(89 , 0 xce0, 8 , 2 ),
MTK_PIN_DRV_GRP(90 , 0 xd00, 8 , 2 ),
MTK_PIN_DRV_GRP(91 , 0 xd00, 8 , 2 ),
MTK_PIN_DRV_GRP(92 , 0 xd00, 8 , 2 ),
MTK_PIN_DRV_GRP(93 , 0 xd00, 8 , 2 ),
MTK_PIN_DRV_GRP(94 , 0 xd20, 8 , 2 ),
MTK_PIN_DRV_GRP(95 , 0 xcf0, 8 , 2 ),
MTK_PIN_DRV_GRP(96 , 0 xd30, 8 , 2 ),
MTK_PIN_DRV_GRP(97 , 0 xb70, 4 , 0 ),
MTK_PIN_DRV_GRP(98 , 0 xb70, 4 , 0 ),
MTK_PIN_DRV_GRP(99 , 0 xb70, 4 , 0 ),
MTK_PIN_DRV_GRP(100 , 0 xb70, 4 , 0 ),
MTK_PIN_DRV_GRP(101 , 0 xb70, 8 , 0 ),
MTK_PIN_DRV_GRP(102 , 0 xb70, 8 , 0 ),
MTK_PIN_DRV_GRP(103 , 0 xb70, 8 , 0 ),
MTK_PIN_DRV_GRP(104 , 0 xb70, 8 , 0 ),
MTK_PIN_DRV_GRP(135 , 0 xb40, 0 , 1 ),
MTK_PIN_DRV_GRP(136 , 0 xb40, 0 , 1 ),
MTK_PIN_DRV_GRP(137 , 0 xb40, 0 , 1 ),
MTK_PIN_DRV_GRP(138 , 0 xb40, 0 , 1 ),
MTK_PIN_DRV_GRP(139 , 0 xb40, 0 , 1 ),
MTK_PIN_DRV_GRP(140 , 0 xb40, 0 , 1 ),
MTK_PIN_DRV_GRP(141 , 0 xb40, 0 , 1 ),
MTK_PIN_DRV_GRP(142 , 0 xb40, 0 , 1 ),
MTK_PIN_DRV_GRP(143 , 0 xba0, 12 , 0 ),
MTK_PIN_DRV_GRP(144 , 0 xba0, 12 , 0 ),
MTK_PIN_DRV_GRP(145 , 0 xba0, 12 , 0 ),
MTK_PIN_DRV_GRP(146 , 0 xba0, 12 , 0 ),
MTK_PIN_DRV_GRP(147 , 0 xba0, 12 , 0 ),
MTK_PIN_DRV_GRP(148 , 0 xbb0, 0 , 0 ),
MTK_PIN_DRV_GRP(149 , 0 xbb0, 0 , 0 ),
MTK_PIN_DRV_GRP(150 , 0 xbb0, 0 , 0 ),
MTK_PIN_DRV_GRP(151 , 0 xbb0, 0 , 0 ),
MTK_PIN_DRV_GRP(152 , 0 xbb0, 0 , 0 ),
MTK_PIN_DRV_GRP(153 , 0 xbb0, 4 , 0 ),
MTK_PIN_DRV_GRP(154 , 0 xbb0, 4 , 0 ),
MTK_PIN_DRV_GRP(155 , 0 xbb0, 4 , 0 ),
MTK_PIN_DRV_GRP(156 , 0 xbb0, 4 , 0 ),
MTK_PIN_DRV_GRP(157 , 0 xbb0, 8 , 0 ),
MTK_PIN_DRV_GRP(158 , 0 xbb0, 8 , 0 ),
MTK_PIN_DRV_GRP(159 , 0 xbb0, 8 , 0 ),
MTK_PIN_DRV_GRP(160 , 0 xbb0, 8 , 0 ),
MTK_PIN_DRV_GRP(161 , 0 xbb0, 12 , 0 ),
MTK_PIN_DRV_GRP(162 , 0 xbb0, 12 , 0 ),
MTK_PIN_DRV_GRP(163 , 0 xbb0, 12 , 0 ),
MTK_PIN_DRV_GRP(164 , 0 xbb0, 12 , 0 ),
MTK_PIN_DRV_GRP(165 , 0 xbc0, 0 , 0 ),
MTK_PIN_DRV_GRP(166 , 0 xbc0, 0 , 0 ),
MTK_PIN_DRV_GRP(167 , 0 xbc0, 0 , 0 ),
MTK_PIN_DRV_GRP(168 , 0 xbc0, 0 , 0 ),
MTK_PIN_DRV_GRP(169 , 0 xbc0, 4 , 0 ),
MTK_PIN_DRV_GRP(170 , 0 xbc0, 4 , 0 ),
MTK_PIN_DRV_GRP(171 , 0 xbc0, 8 , 0 ),
MTK_PIN_DRV_GRP(172 , 0 xbc0, 8 , 0 ),
MTK_PIN_DRV_GRP(173 , 0 xbc0, 12 , 0 ),
MTK_PIN_DRV_GRP(174 , 0 xbd0, 0 , 0 ),
MTK_PIN_DRV_GRP(175 , 0 xbd0, 0 , 0 ),
MTK_PIN_DRV_GRP(176 , 0 xbc0, 12 , 0 ),
MTK_PIN_DRV_GRP(177 , 0 xbd0, 4 , 0 ),
MTK_PIN_DRV_GRP(178 , 0 xbd0, 8 , 0 ),
MTK_PIN_DRV_GRP(179 , 0 xbd0, 4 , 0 ),
MTK_PIN_DRV_GRP(180 , 0 xbd0, 8 , 0 ),
MTK_PIN_DRV_GRP(181 , 0 xbd0, 12 , 0 ),
MTK_PIN_DRV_GRP(182 , 0 xbe0, 0 , 0 ),
MTK_PIN_DRV_GRP(183 , 0 xbd0, 12 , 0 ),
MTK_PIN_DRV_GRP(184 , 0 xbe0, 0 , 0 ),
MTK_PIN_DRV_GRP(185 , 0 xbe0, 4 , 0 ),
MTK_PIN_DRV_GRP(186 , 0 xbe0, 8 , 0 ),
MTK_PIN_DRV_GRP(187 , 0 xbe0, 12 , 0 ),
MTK_PIN_DRV_GRP(188 , 0 xbf0, 0 , 0 ),
MTK_PIN_DRV_GRP(189 , 0 xbe0, 12 , 0 ),
MTK_PIN_DRV_GRP(190 , 0 xbf0, 0 , 0 ),
MTK_PIN_DRV_GRP(191 , 0 xbf0, 4 , 0 ),
MTK_PIN_DRV_GRP(192 , 0 xbf0, 8 , 0 ),
MTK_PIN_DRV_GRP(193 , 0 xbf0, 4 , 0 ),
MTK_PIN_DRV_GRP(194 , 0 xbf0, 4 , 0 ),
MTK_PIN_DRV_GRP(195 , 0 xbf0, 8 , 0 ),
MTK_PIN_DRV_GRP(196 , 0 xbf0, 12 , 0 ),
MTK_PIN_DRV_GRP(197 , 0 xbf0, 12 , 0 ),
MTK_PIN_DRV_GRP(198 , 0 xbf0, 12 , 0 ),
MTK_PIN_DRV_GRP(199 , 0 xbf0, 12 , 0 ),
MTK_PIN_DRV_GRP(200 , 0 xc00, 0 , 0 ),
MTK_PIN_DRV_GRP(201 , 0 xc00, 0 , 0 ),
MTK_PIN_DRV_GRP(202 , 0 xc00, 0 , 0 ),
MTK_PIN_DRV_GRP(203 , 0 xc00, 0 , 0 ),
MTK_PIN_DRV_GRP(204 , 0 xc00, 4 , 0 ),
MTK_PIN_DRV_GRP(205 , 0 xc00, 4 , 0 ),
MTK_PIN_DRV_GRP(206 , 0 xc00, 4 , 0 ),
MTK_PIN_DRV_GRP(207 , 0 xc00, 8 , 0 ),
MTK_PIN_DRV_GRP(208 , 0 xc00, 8 , 0 ),
MTK_PIN_DRV_GRP(209 , 0 xc00, 8 , 0 ),
};
static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = {
.pins = mtk_pins_mt2712,
.npins = ARRAY_SIZE(mtk_pins_mt2712),
.grp_desc = mt2712_drv_grp,
.n_grp_cls = ARRAY_SIZE(mt2712_drv_grp),
.pin_drv_grp = mt2712_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt2712_pin_drv),
.spec_ies = mt2712_ies_set,
.n_spec_ies = ARRAY_SIZE(mt2712_ies_set),
.spec_pupd = mt2712_spec_pupd,
.n_spec_pupd = ARRAY_SIZE(mt2712_spec_pupd),
.spec_smt = mt2712_smt_set,
.n_spec_smt = ARRAY_SIZE(mt2712_smt_set),
.spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
.spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
.dir_offset = 0 x0000,
.pullen_offset = 0 x0100,
.pullsel_offset = 0 x0200,
.dout_offset = 0 x0300,
.din_offset = 0 x0400,
.pinmux_offset = 0 x0500,
.type1_start = 210 ,
.type1_end = 210 ,
.port_shf = 4 ,
.port_mask = 0 xf,
.port_align = 4 ,
.mode_mask = 0 xf,
.mode_per_reg = 5 ,
.mode_shf = 4 ,
.eint_hw = {
.port_mask = 0 xf,
.ports = 8 ,
.ap_num = 229 ,
.db_cnt = 40 ,
.db_time = debounce_time_mt2701,
},
};
static const struct of_device_id mt2712_pctrl_match[] = {
{ .compatible = "mediatek,mt2712-pinctrl" , .data = &mt2712_pinctrl_data },
{ }
};
MODULE_DEVICE_TABLE(of, mt2712_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mtk_pctrl_common_probe,
.driver = {
.name = "mediatek-mt2712-pinctrl" ,
.of_match_table = mt2712_pctrl_match,
.pm = pm_sleep_ptr(&mtk_eint_pm_ops),
},
};
static int __init mtk_pinctrl_init(void )
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);
Messung V0.5 in Prozent C=100 H=100 G=100