// SPDX-License-Identifier: GPL-2.0 /* * Intel Sunrisepoint PCH pinctrl/GPIO driver * * Copyright (C) 2015, Intel Corporation * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> * Mika Westerberg <mika.westerberg@linux.intel.com> #include <linux/mod_devicetable.h>#include <linux/module.h>#include <linux/platform_device.h>#include <linux/pm.h>#include <linux/pinctrl/pinctrl.h>#include "pinctrl-intel.h" #define SPT_H_PAD_OWN 0 x020#define SPT_H_PADCFGLOCK 0 x090#define SPT_H_HOSTSW_OWN 0 x0d0#define SPT_H_GPI_IS 0 x100#define SPT_H_GPI_IE 0 x120#define SPT_LP_PAD_OWN 0 x020#define SPT_LP_PADCFGLOCK 0 x0a0#define SPT_LP_HOSTSW_OWN 0 x0d0#define SPT_LP_GPI_IS 0 x100#define SPT_LP_GPI_IE 0 x120#define SPT_H_GPP(r, s, e, g) \1 ), \#define SPT_H_COMMUNITY(b, s, e, g) \#define SPT_LP_COMMUNITY(b, s, e) \24 , 4 , SPT_LP)/* Sunrisepoint-LP */ static const struct pinctrl_pin_desc sptlp_pins[] = {/* GPP_A */ 0 , "RCINB" ),1 , "LAD_0" ),2 , "LAD_1" ),3 , "LAD_2" ),4 , "LAD_3" ),5 , "LFRAMEB" ),6 , "SERIQ" ),7 , "PIRQAB" ),8 , "CLKRUNB" ),9 , "CLKOUT_LPC_0" ),10 , "CLKOUT_LPC_1" ),11 , "PMEB" ),12 , "BM_BUSYB" ),13 , "SUSWARNB_SUS_PWRDNACK" ),14 , "SUS_STATB" ),15 , "SUSACKB" ),16 , "SD_1P8_SEL" ),17 , "SD_PWR_EN_B" ),18 , "ISH_GP_0" ),19 , "ISH_GP_1" ),20 , "ISH_GP_2" ),21 , "ISH_GP_3" ),22 , "ISH_GP_4" ),23 , "ISH_GP_5" ),/* GPP_B */ 24 , "CORE_VID_0" ),25 , "CORE_VID_1" ),26 , "VRALERTB" ),27 , "CPU_GP_2" ),28 , "CPU_GP_3" ),29 , "SRCCLKREQB_0" ),30 , "SRCCLKREQB_1" ),31 , "SRCCLKREQB_2" ),32 , "SRCCLKREQB_3" ),33 , "SRCCLKREQB_4" ),34 , "SRCCLKREQB_5" ),35 , "EXT_PWR_GATEB" ),36 , "SLP_S0B" ),37 , "PLTRSTB" ),38 , "SPKR" ),39 , "GSPI0_CSB" ),40 , "GSPI0_CLK" ),41 , "GSPI0_MISO" ),42 , "GSPI0_MOSI" ),43 , "GSPI1_CSB" ),44 , "GSPI1_CLK" ),45 , "GSPI1_MISO" ),46 , "GSPI1_MOSI" ),47 , "SML1ALERTB" ),/* GPP_C */ 48 , "SMBCLK" ),49 , "SMBDATA" ),50 , "SMBALERTB" ),51 , "SML0CLK" ),52 , "SML0DATA" ),53 , "SML0ALERTB" ),54 , "SML1CLK" ),55 , "SML1DATA" ),56 , "UART0_RXD" ),57 , "UART0_TXD" ),58 , "UART0_RTSB" ),59 , "UART0_CTSB" ),60 , "UART1_RXD" ),61 , "UART1_TXD" ),62 , "UART1_RTSB" ),63 , "UART1_CTSB" ),64 , "I2C0_SDA" ),65 , "I2C0_SCL" ),66 , "I2C1_SDA" ),67 , "I2C1_SCL" ),68 , "UART2_RXD" ),69 , "UART2_TXD" ),70 , "UART2_RTSB" ),71 , "UART2_CTSB" ),/* GPP_D */ 72 , "SPI1_CSB" ),73 , "SPI1_CLK" ),74 , "SPI1_MISO_IO_1" ),75 , "SPI1_MOSI_IO_0" ),76 , "FLASHTRIG" ),77 , "ISH_I2C0_SDA" ),78 , "ISH_I2C0_SCL" ),79 , "ISH_I2C1_SDA" ),80 , "ISH_I2C1_SCL" ),81 , "ISH_SPI_CSB" ),82 , "ISH_SPI_CLK" ),83 , "ISH_SPI_MISO" ),84 , "ISH_SPI_MOSI" ),85 , "ISH_UART0_RXD" ),86 , "ISH_UART0_TXD" ),87 , "ISH_UART0_RTSB" ),88 , "ISH_UART0_CTSB" ),89 , "DMIC_CLK_1" ),90 , "DMIC_DATA_1" ),91 , "DMIC_CLK_0" ),92 , "DMIC_DATA_0" ),93 , "SPI1_IO_2" ),94 , "SPI1_IO_3" ),95 , "SSP_MCLK" ),/* GPP_E */ 96 , "SATAXPCIE_0" ),97 , "SATAXPCIE_1" ),98 , "SATAXPCIE_2" ),99 , "CPU_GP_0" ),100 , "SATA_DEVSLP_0" ),101 , "SATA_DEVSLP_1" ),102 , "SATA_DEVSLP_2" ),103 , "CPU_GP_1" ),104 , "SATA_LEDB" ),105 , "USB2_OCB_0" ),106 , "USB2_OCB_1" ),107 , "USB2_OCB_2" ),108 , "USB2_OCB_3" ),109 , "DDSP_HPD_0" ),110 , "DDSP_HPD_1" ),111 , "DDSP_HPD_2" ),112 , "DDSP_HPD_3" ),113 , "EDP_HPD" ),114 , "DDPB_CTRLCLK" ),115 , "DDPB_CTRLDATA" ),116 , "DDPC_CTRLCLK" ),117 , "DDPC_CTRLDATA" ),118 , "DDPD_CTRLCLK" ),119 , "DDPD_CTRLDATA" ),/* GPP_F */ 120 , "SSP2_SCLK" ),121 , "SSP2_SFRM" ),122 , "SSP2_TXD" ),123 , "SSP2_RXD" ),124 , "I2C2_SDA" ),125 , "I2C2_SCL" ),126 , "I2C3_SDA" ),127 , "I2C3_SCL" ),128 , "I2C4_SDA" ),129 , "I2C4_SCL" ),130 , "I2C5_SDA" ),131 , "I2C5_SCL" ),132 , "EMMC_CMD" ),133 , "EMMC_DATA_0" ),134 , "EMMC_DATA_1" ),135 , "EMMC_DATA_2" ),136 , "EMMC_DATA_3" ),137 , "EMMC_DATA_4" ),138 , "EMMC_DATA_5" ),139 , "EMMC_DATA_6" ),140 , "EMMC_DATA_7" ),141 , "EMMC_RCLK" ),142 , "EMMC_CLK" ),143 , "GPP_F_23" ),/* GPP_G */ 144 , "SD_CMD" ),145 , "SD_DATA_0" ),146 , "SD_DATA_1" ),147 , "SD_DATA_2" ),148 , "SD_DATA_3" ),149 , "SD_CDB" ),150 , "SD_CLK" ),151 , "SD_WP" ),static const unsigned sptlp_spi0_pins[] = { 39 , 40 , 41 , 42 };static const unsigned sptlp_spi1_pins[] = { 43 , 44 , 45 , 46 };static const unsigned sptlp_uart0_pins[] = { 56 , 57 , 58 , 59 };static const unsigned sptlp_uart1_pins[] = { 60 , 61 , 62 , 63 };static const unsigned sptlp_uart2_pins[] = { 68 , 69 , 71 , 71 };static const unsigned sptlp_i2c0_pins[] = { 64 , 65 };static const unsigned sptlp_i2c1_pins[] = { 66 , 67 };static const unsigned sptlp_i2c2_pins[] = { 124 , 125 };static const unsigned sptlp_i2c3_pins[] = { 126 , 127 };static const unsigned sptlp_i2c4_pins[] = { 128 , 129 };static const unsigned sptlp_i2c4b_pins[] = { 85 , 86 };static const unsigned sptlp_i2c5_pins[] = { 130 , 131 };static const unsigned sptlp_ssp2_pins[] = { 120 , 121 , 122 , 123 };static const unsigned sptlp_emmc_pins[] = {132 , 133 , 134 , 135 , 136 , 137 , 138 , 139 , 140 , 141 , 142 ,static const unsigned sptlp_sd_pins[] = {144 , 145 , 146 , 147 , 148 , 149 , 150 , 151 ,static const struct intel_pingroup sptlp_groups[] = {"spi0_grp" , sptlp_spi0_pins, 1 ),"spi1_grp" , sptlp_spi1_pins, 1 ),"uart0_grp" , sptlp_uart0_pins, 1 ),"uart1_grp" , sptlp_uart1_pins, 1 ),"uart2_grp" , sptlp_uart2_pins, 1 ),"i2c0_grp" , sptlp_i2c0_pins, 1 ),"i2c1_grp" , sptlp_i2c1_pins, 1 ),"i2c2_grp" , sptlp_i2c2_pins, 1 ),"i2c3_grp" , sptlp_i2c3_pins, 1 ),"i2c4_grp" , sptlp_i2c4_pins, 1 ),"i2c4b_grp" , sptlp_i2c4b_pins, 3 ),"i2c5_grp" , sptlp_i2c5_pins, 1 ),"ssp2_grp" , sptlp_ssp2_pins, 1 ),"emmc_grp" , sptlp_emmc_pins, 1 ),"sd_grp" , sptlp_sd_pins, 1 ),static const char * const sptlp_spi0_groups[] = { "spi0_grp" };static const char * const sptlp_spi1_groups[] = { "spi0_grp" };static const char * const sptlp_uart0_groups[] = { "uart0_grp" };static const char * const sptlp_uart1_groups[] = { "uart1_grp" };static const char * const sptlp_uart2_groups[] = { "uart2_grp" };static const char * const sptlp_i2c0_groups[] = { "i2c0_grp" };static const char * const sptlp_i2c1_groups[] = { "i2c1_grp" };static const char * const sptlp_i2c2_groups[] = { "i2c2_grp" };static const char * const sptlp_i2c3_groups[] = { "i2c3_grp" };static const char * const sptlp_i2c4_groups[] = { "i2c4_grp" , "i2c4b_grp" };static const char * const sptlp_i2c5_groups[] = { "i2c5_grp" };static const char * const sptlp_ssp2_groups[] = { "ssp2_grp" };static const char * const sptlp_emmc_groups[] = { "emmc_grp" };static const char * const sptlp_sd_groups[] = { "sd_grp" };static const struct intel_function sptlp_functions[] = {"spi0" , sptlp_spi0_groups),"spi1" , sptlp_spi1_groups),"uart0" , sptlp_uart0_groups),"uart1" , sptlp_uart1_groups),"uart2" , sptlp_uart2_groups),"i2c0" , sptlp_i2c0_groups),"i2c1" , sptlp_i2c1_groups),"i2c2" , sptlp_i2c2_groups),"i2c3" , sptlp_i2c3_groups),"i2c4" , sptlp_i2c4_groups),"i2c5" , sptlp_i2c5_groups),"ssp2" , sptlp_ssp2_groups),"emmc" , sptlp_emmc_groups),"sd" , sptlp_sd_groups),static const struct intel_community sptlp_communities[] = {0 , 0 , 47 ),1 , 48 , 119 ),2 , 120 , 151 ),static const struct intel_pinctrl_soc_data sptlp_soc_data = {/* Sunrisepoint-H */ static const struct pinctrl_pin_desc spth_pins[] = {/* GPP_A */ 0 , "RCINB" ),1 , "LAD_0" ),2 , "LAD_1" ),3 , "LAD_2" ),4 , "LAD_3" ),5 , "LFRAMEB" ),6 , "SERIQ" ),7 , "PIRQAB" ),8 , "CLKRUNB" ),9 , "CLKOUT_LPC_0" ),10 , "CLKOUT_LPC_1" ),11 , "PMEB" ),12 , "BM_BUSYB" ),13 , "SUSWARNB_SUS_PWRDNACK" ),14 , "SUS_STATB" ),15 , "SUSACKB" ),16 , "CLKOUT_48" ),17 , "ISH_GP_7" ),18 , "ISH_GP_0" ),19 , "ISH_GP_1" ),20 , "ISH_GP_2" ),21 , "ISH_GP_3" ),22 , "ISH_GP_4" ),23 , "ISH_GP_5" ),/* GPP_B */ 24 , "CORE_VID_0" ),25 , "CORE_VID_1" ),26 , "VRALERTB" ),27 , "CPU_GP_2" ),28 , "CPU_GP_3" ),29 , "SRCCLKREQB_0" ),30 , "SRCCLKREQB_1" ),31 , "SRCCLKREQB_2" ),32 , "SRCCLKREQB_3" ),33 , "SRCCLKREQB_4" ),34 , "SRCCLKREQB_5" ),35 , "EXT_PWR_GATEB" ),36 , "SLP_S0B" ),37 , "PLTRSTB" ),38 , "SPKR" ),39 , "GSPI0_CSB" ),40 , "GSPI0_CLK" ),41 , "GSPI0_MISO" ),42 , "GSPI0_MOSI" ),43 , "GSPI1_CSB" ),44 , "GSPI1_CLK" ),45 , "GSPI1_MISO" ),46 , "GSPI1_MOSI" ),47 , "SML1ALERTB" ),/* GPP_C */ 48 , "SMBCLK" ),49 , "SMBDATA" ),50 , "SMBALERTB" ),51 , "SML0CLK" ),52 , "SML0DATA" ),53 , "SML0ALERTB" ),54 , "SML1CLK" ),55 , "SML1DATA" ),56 , "UART0_RXD" ),57 , "UART0_TXD" ),58 , "UART0_RTSB" ),59 , "UART0_CTSB" ),60 , "UART1_RXD" ),61 , "UART1_TXD" ),62 , "UART1_RTSB" ),63 , "UART1_CTSB" ),64 , "I2C0_SDA" ),65 , "I2C0_SCL" ),66 , "I2C1_SDA" ),67 , "I2C1_SCL" ),68 , "UART2_RXD" ),69 , "UART2_TXD" ),70 , "UART2_RTSB" ),71 , "UART2_CTSB" ),/* GPP_D */ 72 , "SPI1_CSB" ),73 , "SPI1_CLK" ),74 , "SPI1_MISO_IO_1" ),75 , "SPI1_MOSI_IO_0" ),76 , "ISH_I2C2_SDA" ),77 , "SSP0_SFRM" ),78 , "SSP0_TXD" ),79 , "SSP0_RXD" ),80 , "SSP0_SCLK" ),81 , "ISH_SPI_CSB" ),82 , "ISH_SPI_CLK" ),83 , "ISH_SPI_MISO" ),84 , "ISH_SPI_MOSI" ),85 , "ISH_UART0_RXD" ),86 , "ISH_UART0_TXD" ),87 , "ISH_UART0_RTSB" ),88 , "ISH_UART0_CTSB" ),89 , "DMIC_CLK_1" ),90 , "DMIC_DATA_1" ),91 , "DMIC_CLK_0" ),92 , "DMIC_DATA_0" ),93 , "SPI1_IO_2" ),94 , "SPI1_IO_3" ),95 , "ISH_I2C2_SCL" ),/* GPP_E */ 96 , "SATAXPCIE_0" ),97 , "SATAXPCIE_1" ),98 , "SATAXPCIE_2" ),99 , "CPU_GP_0" ),100 , "SATA_DEVSLP_0" ),101 , "SATA_DEVSLP_1" ),102 , "SATA_DEVSLP_2" ),103 , "CPU_GP_1" ),104 , "SATA_LEDB" ),105 , "USB2_OCB_0" ),106 , "USB2_OCB_1" ),107 , "USB2_OCB_2" ),108 , "USB2_OCB_3" ),/* GPP_F */ 109 , "SATAXPCIE_3" ),110 , "SATAXPCIE_4" ),111 , "SATAXPCIE_5" ),112 , "SATAXPCIE_6" ),113 , "SATAXPCIE_7" ),114 , "SATA_DEVSLP_3" ),115 , "SATA_DEVSLP_4" ),116 , "SATA_DEVSLP_5" ),117 , "SATA_DEVSLP_6" ),118 , "SATA_DEVSLP_7" ),119 , "SATA_SCLOCK" ),120 , "SATA_SLOAD" ),121 , "SATA_SDATAOUT1" ),122 , "SATA_SDATAOUT0" ),123 , "GPP_F_14" ),124 , "USB_OCB_4" ),125 , "USB_OCB_5" ),126 , "USB_OCB_6" ),127 , "USB_OCB_7" ),128 , "L_VDDEN" ),129 , "L_BKLTEN" ),130 , "L_BKLTCTL" ),131 , "GPP_F_22" ),132 , "GPP_F_23" ),/* GPP_G */ 133 , "FAN_TACH_0" ),134 , "FAN_TACH_1" ),135 , "FAN_TACH_2" ),136 , "FAN_TACH_3" ),137 , "FAN_TACH_4" ),138 , "FAN_TACH_5" ),139 , "FAN_TACH_6" ),140 , "FAN_TACH_7" ),141 , "FAN_PWM_0" ),142 , "FAN_PWM_1" ),143 , "FAN_PWM_2" ),144 , "FAN_PWM_3" ),145 , "GSXDOUT" ),146 , "GSXSLOAD" ),147 , "GSXDIN" ),148 , "GSXRESETB" ),149 , "GSXCLK" ),150 , "ADR_COMPLETE" ),151 , "NMIB" ),152 , "SMIB" ),153 , "GPP_G_20" ),154 , "GPP_G_21" ),155 , "GPP_G_22" ),156 , "GPP_G_23" ),/* GPP_H */ 157 , "SRCCLKREQB_6" ),158 , "SRCCLKREQB_7" ),159 , "SRCCLKREQB_8" ),160 , "SRCCLKREQB_9" ),161 , "SRCCLKREQB_10" ),162 , "SRCCLKREQB_11" ),163 , "SRCCLKREQB_12" ),164 , "SRCCLKREQB_13" ),165 , "SRCCLKREQB_14" ),166 , "SRCCLKREQB_15" ),167 , "SML2CLK" ),168 , "SML2DATA" ),169 , "SML2ALERTB" ),170 , "SML3CLK" ),171 , "SML3DATA" ),172 , "SML3ALERTB" ),173 , "SML4CLK" ),174 , "SML4DATA" ),175 , "SML4ALERTB" ),176 , "ISH_I2C0_SDA" ),177 , "ISH_I2C0_SCL" ),178 , "ISH_I2C1_SDA" ),179 , "ISH_I2C1_SCL" ),180 , "GPP_H_23" ),/* GPP_I */ 181 , "DDSP_HDP_0" ),182 , "DDSP_HDP_1" ),183 , "DDSP_HDP_2" ),184 , "DDSP_HDP_3" ),185 , "EDP_HPD" ),186 , "DDPB_CTRLCLK" ),187 , "DDPB_CTRLDATA" ),188 , "DDPC_CTRLCLK" ),189 , "DDPC_CTRLDATA" ),190 , "DDPD_CTRLCLK" ),191 , "DDPD_CTRLDATA" ),static const unsigned spth_spi0_pins[] = { 39 , 40 , 41 , 42 };static const unsigned spth_spi1_pins[] = { 43 , 44 , 45 , 46 };static const unsigned spth_uart0_pins[] = { 56 , 57 , 58 , 59 };static const unsigned spth_uart1_pins[] = { 60 , 61 , 62 , 63 };static const unsigned spth_uart2_pins[] = { 68 , 69 , 71 , 71 };static const unsigned spth_i2c0_pins[] = { 64 , 65 };static const unsigned spth_i2c1_pins[] = { 66 , 67 };static const unsigned spth_i2c2_pins[] = { 76 , 95 };static const struct intel_pingroup spth_groups[] = {"spi0_grp" , spth_spi0_pins, 1 ),"spi1_grp" , spth_spi1_pins, 1 ),"uart0_grp" , spth_uart0_pins, 1 ),"uart1_grp" , spth_uart1_pins, 1 ),"uart2_grp" , spth_uart2_pins, 1 ),"i2c0_grp" , spth_i2c0_pins, 1 ),"i2c1_grp" , spth_i2c1_pins, 1 ),"i2c2_grp" , spth_i2c2_pins, 2 ),static const char * const spth_spi0_groups[] = { "spi0_grp" };static const char * const spth_spi1_groups[] = { "spi0_grp" };static const char * const spth_uart0_groups[] = { "uart0_grp" };static const char * const spth_uart1_groups[] = { "uart1_grp" };static const char * const spth_uart2_groups[] = { "uart2_grp" };static const char * const spth_i2c0_groups[] = { "i2c0_grp" };static const char * const spth_i2c1_groups[] = { "i2c1_grp" };static const char * const spth_i2c2_groups[] = { "i2c2_grp" };static const struct intel_function spth_functions[] = {"spi0" , spth_spi0_groups),"spi1" , spth_spi1_groups),"uart0" , spth_uart0_groups),"uart1" , spth_uart1_groups),"uart2" , spth_uart2_groups),"i2c0" , spth_i2c0_groups),"i2c1" , spth_i2c1_groups),"i2c2" , spth_i2c2_groups),static const struct intel_padgroup spth_community0_gpps[] = {0 , 0 , 23 , 0 ), /* GPP_A */ 1 , 24 , 47 , 24 ), /* GPP_B */ static const struct intel_padgroup spth_community1_gpps[] = {0 , 48 , 71 , 48 ), /* GPP_C */ 1 , 72 , 95 , 72 ), /* GPP_D */ 2 , 96 , 108 , 96 ), /* GPP_E */ 3 , 109 , 132 , 120 ), /* GPP_F */ 4 , 133 , 156 , 144 ), /* GPP_G */ 5 , 157 , 180 , 168 ), /* GPP_H */ static const struct intel_padgroup spth_community3_gpps[] = {0 , 181 , 191 , 192 ), /* GPP_I */ static const struct intel_community spth_communities[] = {0 , 0 , 47 , spth_community0_gpps),1 , 48 , 180 , spth_community1_gpps),2 , 181 , 191 , spth_community3_gpps),static const struct intel_pinctrl_soc_data spth_soc_data = {static const struct acpi_device_id spt_pinctrl_acpi_match[] = {"INT344B" , (kernel_ulong_t)&sptlp_soc_data },"INT3451" , (kernel_ulong_t)&spth_soc_data },"INT345D" , (kernel_ulong_t)&spth_soc_data },static struct platform_driver spt_pinctrl_driver = {"sunrisepoint-pinctrl" ,static int __init spt_pinctrl_init(void )return platform_driver_register(&spt_pinctrl_driver);static void __exit spt_pinctrl_exit(void )"Mathias Nyman <mathias.nyman@linux.intel.com>" );"Mika Westerberg <mika.westerberg@linux.intel.com>" );"Intel Sunrisepoint PCH pinctrl/GPIO driver" );"GPL v2" );"PINCTRL_INTEL" );
Messung V0.5 in Prozent C=94 H=96 G=94
¤ Dauer der Verarbeitung: 0.13 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
