// SPDX-License-Identifier: GPL-2.0 /* * Intel Jasper Lake PCH pinctrl/GPIO driver * * Copyright (C) 2020, Intel Corporation * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> #include <linux/mod_devicetable.h>#include <linux/module.h>#include <linux/platform_device.h>#include <linux/pm.h>#include <linux/pinctrl/pinctrl.h>#include "pinctrl-intel.h" #define JSL_PAD_OWN 0 x020#define JSL_PADCFGLOCK 0 x080#define JSL_HOSTSW_OWN 0 x0c0#define JSL_GPI_IS 0 x100#define JSL_GPI_IE 0 x120#define JSL_GPP(r, s, e, g) \1 ), \#define JSL_COMMUNITY(b, s, e, g) \/* Jasper Lake */ static const struct pinctrl_pin_desc jsl_pins[] = {/* GPP_F */ 0 , "CNV_BRI_DT_UART0_RTSB" ),1 , "CNV_BRI_RSP_UART0_RXD" ),2 , "EMMC_HIP_MON" ),3 , "CNV_RGI_RSP_UART0_CTSB" ),4 , "CNV_RF_RESET_B" ),5 , "MODEM_CLKREQ" ),6 , "CNV_PA_BLANKING" ),7 , "EMMC_CMD" ),8 , "EMMC_DATA0" ),9 , "EMMC_DATA1" ),10 , "EMMC_DATA2" ),11 , "EMMC_DATA3" ),12 , "EMMC_DATA4" ),13 , "EMMC_DATA5" ),14 , "EMMC_DATA6" ),15 , "EMMC_DATA7" ),16 , "EMMC_RCLK" ),17 , "EMMC_CLK" ),18 , "EMMC_RESETB" ),19 , "A4WP_PRESENT" ),/* SPI */ 20 , "SPI0_IO_2" ),21 , "SPI0_IO_3" ),22 , "SPI0_MOSI_IO_0" ),23 , "SPI0_MISO_IO_1" ),24 , "SPI0_TPM_CSB" ),25 , "SPI0_FLASH_0_CSB" ),26 , "SPI0_FLASH_1_CSB" ),27 , "SPI0_CLK" ),28 , "SPI0_CLK_LOOPBK" ),/* GPP_B */ 29 , "CORE_VID_0" ),30 , "CORE_VID_1" ),31 , "VRALERTB" ),32 , "CPU_GP_2" ),33 , "CPU_GP_3" ),34 , "SRCCLKREQB_0" ),35 , "SRCCLKREQB_1" ),36 , "SRCCLKREQB_2" ),37 , "SRCCLKREQB_3" ),38 , "SRCCLKREQB_4" ),39 , "SRCCLKREQB_5" ),40 , "PMCALERTB" ),41 , "SLP_S0B" ),42 , "PLTRSTB" ),43 , "SPKR" ),44 , "GSPI0_CS0B" ),45 , "GSPI0_CLK" ),46 , "GSPI0_MISO" ),47 , "GSPI0_MOSI" ),48 , "GSPI1_CS0B" ),49 , "GSPI1_CLK" ),50 , "GSPI1_MISO" ),51 , "GSPI1_MOSI" ),52 , "DDSP_HPD_A" ),53 , "GSPI0_CLK_LOOPBK" ),54 , "GSPI1_CLK_LOOPBK" ),/* GPP_A */ 55 , "ESPI_IO_0" ),56 , "ESPI_IO_1" ),57 , "ESPI_IO_2" ),58 , "ESPI_IO_3" ),59 , "ESPI_CSB" ),60 , "ESPI_CLK" ),61 , "ESPI_RESETB" ),62 , "SMBCLK" ),63 , "SMBDATA" ),64 , "SMBALERTB" ),65 , "CPU_GP_0" ),66 , "CPU_GP_1" ),67 , "USB2_OCB_1" ),68 , "USB2_OCB_2" ),69 , "USB2_OCB_3" ),70 , "DDSP_HPD_A_TIME_SYNC_0" ),71 , "DDSP_HPD_B" ),72 , "DDSP_HPD_C" ),73 , "USB2_OCB_0" ),74 , "PCHHOTB" ),75 , "ESPI_CLK_LOOPBK" ),/* GPP_S */ 76 , "SNDW1_CLK" ),77 , "SNDW1_DATA" ),78 , "SNDW2_CLK" ),79 , "SNDW2_DATA" ),80 , "SNDW1_CLK" ),81 , "SNDW1_DATA" ),82 , "SNDW4_CLK_DMIC_CLK_0" ),83 , "SNDW4_DATA_DMIC_DATA_0" ),/* GPP_R */ 84 , "HDA_BCLK" ),85 , "HDA_SYNC" ),86 , "HDA_SDO" ),87 , "HDA_SDI_0" ),88 , "HDA_RSTB" ),89 , "HDA_SDI_1" ),90 , "I2S1_SFRM" ),91 , "I2S1_TXD" ),/* GPP_H */ 92 , "GPPC_H_0" ),93 , "SD_PWR_EN_B" ),94 , "MODEM_CLKREQ" ),95 , "SX_EXIT_HOLDOFFB" ),96 , "I2C2_SDA" ),97 , "I2C2_SCL" ),98 , "I2C3_SDA" ),99 , "I2C3_SCL" ),100 , "I2C4_SDA" ),101 , "I2C4_SCL" ),102 , "CPU_VCCIO_PWR_GATEB" ),103 , "I2S2_SCLK" ),104 , "I2S2_SFRM" ),105 , "I2S2_TXD" ),106 , "I2S2_RXD" ),107 , "I2S1_SCLK" ),108 , "GPPC_H_16" ),109 , "GPPC_H_17" ),110 , "GPPC_H_18" ),111 , "GPPC_H_19" ),112 , "GPPC_H_20" ),113 , "GPPC_H_21" ),114 , "GPPC_H_22" ),115 , "GPPC_H_23" ),/* GPP_D */ 116 , "SPI1_CSB" ),117 , "SPI1_CLK" ),118 , "SPI1_MISO_IO_1" ),119 , "SPI1_MOSI_IO_0" ),120 , "ISH_I2C0_SDA" ),121 , "ISH_I2C0_SCL" ),122 , "ISH_I2C1_SDA" ),123 , "ISH_I2C1_SCL" ),124 , "ISH_SPI_CSB" ),125 , "ISH_SPI_CLK" ),126 , "ISH_SPI_MISO" ),127 , "ISH_SPI_MOSI" ),128 , "ISH_UART0_RXD" ),129 , "ISH_UART0_TXD" ),130 , "ISH_UART0_RTSB" ),131 , "ISH_UART0_CTSB" ),132 , "SPI1_IO_2" ),133 , "SPI1_IO_3" ),134 , "I2S_MCLK" ),135 , "CNV_MFUART2_RXD" ),136 , "CNV_MFUART2_TXD" ),137 , "CNV_PA_BLANKING" ),138 , "I2C5_SDA" ),139 , "I2C5_SCL" ),140 , "GSPI2_CLK_LOOPBK" ),141 , "SPI1_CLK_LOOPBK" ),/* vGPIO */ 142 , "CNV_BTEN" ),143 , "CNV_WCEN" ),144 , "CNV_BT_HOST_WAKEB" ),145 , "CNV_BT_IF_SELECT" ),146 , "vCNV_BT_UART_TXD" ),147 , "vCNV_BT_UART_RXD" ),148 , "vCNV_BT_UART_CTS_B" ),149 , "vCNV_BT_UART_RTS_B" ),150 , "vCNV_MFUART1_TXD" ),151 , "vCNV_MFUART1_RXD" ),152 , "vCNV_MFUART1_CTS_B" ),153 , "vCNV_MFUART1_RTS_B" ),154 , "vUART0_TXD" ),155 , "vUART0_RXD" ),156 , "vUART0_CTS_B" ),157 , "vUART0_RTS_B" ),158 , "vISH_UART0_TXD" ),159 , "vISH_UART0_RXD" ),160 , "vISH_UART0_CTS_B" ),161 , "vISH_UART0_RTS_B" ),162 , "vCNV_BT_I2S_BCLK" ),163 , "vCNV_BT_I2S_WS_SYNC" ),164 , "vCNV_BT_I2S_SDO" ),165 , "vCNV_BT_I2S_SDI" ),166 , "vI2S2_SCLK" ),167 , "vI2S2_SFRM" ),168 , "vI2S2_TXD" ),169 , "vI2S2_RXD" ),170 , "vSD3_CD_B" ),/* GPP_C */ 171 , "GPPC_C_0" ),172 , "GPPC_C_1" ),173 , "GPPC_C_2" ),174 , "GPPC_C_3" ),175 , "GPPC_C_4" ),176 , "GPPC_C_5" ),177 , "SUSWARNB_SUSPWRDNACK" ),178 , "SUSACKB" ),179 , "UART0_RXD" ),180 , "UART0_TXD" ),181 , "UART0_RTSB" ),182 , "UART0_CTSB" ),183 , "UART1_RXD" ),184 , "UART1_TXD" ),185 , "UART1_RTSB" ),186 , "UART1_CTSB" ),187 , "I2C0_SDA" ),188 , "I2C0_SCL" ),189 , "I2C1_SDA" ),190 , "I2C1_SCL" ),191 , "UART2_RXD" ),192 , "UART2_TXD" ),193 , "UART2_RTSB" ),194 , "UART2_CTSB" ),/* HVCMOS */ 195 , "L_BKLTEN" ),196 , "L_BKLTCTL" ),197 , "L_VDDEN" ),198 , "SYS_PWROK" ),199 , "SYS_RESETB" ),200 , "MLK_RSTB" ),/* GPP_E */ 201 , "ISH_GP_0" ),202 , "ISH_GP_1" ),203 , "IMGCLKOUT_1" ),204 , "ISH_GP_2" ),205 , "IMGCLKOUT_2" ),206 , "SATA_LEDB" ),207 , "IMGCLKOUT_3" ),208 , "ISH_GP_3" ),209 , "ISH_GP_4" ),210 , "ISH_GP_5" ),211 , "ISH_GP_6" ),212 , "ISH_GP_7" ),213 , "IMGCLKOUT_4" ),214 , "DDPA_CTRLCLK" ),215 , "DDPA_CTRLDATA" ),216 , "DDPB_CTRLCLK" ),217 , "DDPB_CTRLDATA" ),218 , "DDPC_CTRLCLK" ),219 , "DDPC_CTRLDATA" ),220 , "IMGCLKOUT_5" ),221 , "CNV_BRI_DT" ),222 , "CNV_BRI_RSP" ),223 , "CNV_RGI_DT" ),224 , "CNV_RGI_RSP" ),/* GPP_G */ 225 , "SD3_CMD" ),226 , "SD3_D0" ),227 , "SD3_D1" ),228 , "SD3_D2" ),229 , "SD3_D3" ),230 , "SD3_CDB" ),231 , "SD3_CLK" ),232 , "SD3_WP" ),static const struct intel_padgroup jsl_community0_gpps[] = {0 , 0 , 19 , 320 ), /* GPP_F */ 1 , 20 , 28 , INTEL_GPIO_BASE_NOMAP), /* SPI */ 2 , 29 , 54 , 32 ), /* GPP_B */ 3 , 55 , 75 , 64 ), /* GPP_A */ 4 , 76 , 83 , 96 ), /* GPP_S */ 5 , 84 , 91 , 128 ), /* GPP_R */ static const struct intel_padgroup jsl_community1_gpps[] = {0 , 92 , 115 , 160 ), /* GPP_H */ 1 , 116 , 141 , 192 ), /* GPP_D */ 2 , 142 , 170 , 224 ), /* vGPIO */ 3 , 171 , 194 , 256 ), /* GPP_C */ static const struct intel_padgroup jsl_community4_gpps[] = {0 , 195 , 200 , INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 1 , 201 , 224 , 288 ), /* GPP_E */ static const struct intel_padgroup jsl_community5_gpps[] = {0 , 225 , 232 , INTEL_GPIO_BASE_ZERO), /* GPP_G */ static const struct intel_community jsl_communities[] = {0 , 0 , 91 , jsl_community0_gpps),1 , 92 , 194 , jsl_community1_gpps),2 , 195 , 224 , jsl_community4_gpps),3 , 225 , 232 , jsl_community5_gpps),static const struct intel_pinctrl_soc_data jsl_soc_data = {static const struct acpi_device_id jsl_pinctrl_acpi_match[] = {"INT34C8" , (kernel_ulong_t)&jsl_soc_data },static struct platform_driver jsl_pinctrl_driver = {"jasperlake-pinctrl" ,"Andy Shevchenko <andriy.shevchenko@linux.intel.com>" );"Intel Jasper Lake PCH pinctrl/GPIO driver" );"GPL v2" );"PINCTRL_INTEL" );
Messung V0.5 in Prozent C=96 H=94 G=94
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