// SPDX-License-Identifier: GPL-2.0 /* * Intel Ice Lake PCH pinctrl/GPIO driver * * Copyright (C) 2018, 2022 Intel Corporation * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> * Mika Westerberg <mika.westerberg@linux.intel.com> #include <linux/acpi.h>#include <linux/module.h>#include <linux/platform_device.h>#include <linux/pm.h>#include <linux/pinctrl/pinctrl.h>#include "pinctrl-intel.h" #define ICL_LP_PAD_OWN 0 x020#define ICL_LP_PADCFGLOCK 0 x080#define ICL_LP_HOSTSW_OWN 0 x0b0#define ICL_LP_GPI_IS 0 x100#define ICL_LP_GPI_IE 0 x110#define ICL_N_PAD_OWN 0 x020#define ICL_N_PADCFGLOCK 0 x080#define ICL_N_HOSTSW_OWN 0 x0b0#define ICL_N_GPI_IS 0 x100#define ICL_N_GPI_IE 0 x120#define ICL_GPP(r, s, e, g) \1 ), \#define ICL_LP_COMMUNITY(b, s, e, g) \#define ICL_N_COMMUNITY(b, s, e, g) \/* Ice Lake-LP */ static const struct pinctrl_pin_desc icllp_pins[] = {/* GPP_G */ 0 , "SD3_CMD" ),1 , "SD3_D0" ),2 , "SD3_D1" ),3 , "SD3_D2" ),4 , "SD3_D3" ),5 , "SD3_CDB" ),6 , "SD3_CLK" ),7 , "SD3_WP" ),/* GPP_B */ 8 , "CORE_VID_0" ),9 , "CORE_VID_1" ),10 , "VRALERTB" ),11 , "CPU_GP_2" ),12 , "CPU_GP_3" ),13 , "ISH_I2C0_SDA" ),14 , "ISH_I2C0_SCL" ),15 , "ISH_I2C1_SDA" ),16 , "ISH_I2C1_SCL" ),17 , "I2C5_SDA" ),18 , "I2C5_SCL" ),19 , "PMCALERTB" ),20 , "SLP_S0B" ),21 , "PLTRSTB" ),22 , "SPKR" ),23 , "GSPI0_CS0B" ),24 , "GSPI0_CLK" ),25 , "GSPI0_MISO" ),26 , "GSPI0_MOSI" ),27 , "GSPI1_CS0B" ),28 , "GSPI1_CLK" ),29 , "GSPI1_MISO" ),30 , "GSPI1_MOSI" ),31 , "SML1ALERTB" ),32 , "GSPI0_CLK_LOOPBK" ),33 , "GSPI1_CLK_LOOPBK" ),/* GPP_A */ 34 , "ESPI_IO_0" ),35 , "ESPI_IO_1" ),36 , "ESPI_IO_2" ),37 , "ESPI_IO_3" ),38 , "ESPI_CSB" ),39 , "ESPI_CLK" ),40 , "ESPI_RESETB" ),41 , "I2S2_SCLK" ),42 , "I2S2_SFRM" ),43 , "I2S2_TXD" ),44 , "I2S2_RXD" ),45 , "SATA_DEVSLP_2" ),46 , "SATAXPCIE_1" ),47 , "SATAXPCIE_2" ),48 , "USB2_OCB_1" ),49 , "USB2_OCB_2" ),50 , "USB2_OCB_3" ),51 , "DDSP_HPD_C" ),52 , "DDSP_HPD_B" ),53 , "DDSP_HPD_1" ),54 , "DDSP_HPD_2" ),55 , "I2S5_TXD" ),56 , "I2S5_RXD" ),57 , "I2S1_SCLK" ),58 , "ESPI_CLK_LOOPBK" ),/* GPP_H */ 59 , "SD_1P8_SEL" ),60 , "SD_PWR_EN_B" ),61 , "GPPC_H_2" ),62 , "SX_EXIT_HOLDOFFB" ),63 , "I2C2_SDA" ),64 , "I2C2_SCL" ),65 , "I2C3_SDA" ),66 , "I2C3_SCL" ),67 , "I2C4_SDA" ),68 , "I2C4_SCL" ),69 , "SRCCLKREQB_4" ),70 , "SRCCLKREQB_5" ),71 , "M2_SKT2_CFG_0" ),72 , "M2_SKT2_CFG_1" ),73 , "M2_SKT2_CFG_2" ),74 , "M2_SKT2_CFG_3" ),75 , "DDPB_CTRLCLK" ),76 , "DDPB_CTRLDATA" ),77 , "CPU_VCCIO_PWR_GATEB" ),78 , "TIME_SYNC_0" ),79 , "IMGCLKOUT_1" ),80 , "IMGCLKOUT_2" ),81 , "IMGCLKOUT_3" ),82 , "IMGCLKOUT_4" ),/* GPP_D */ 83 , "ISH_GP_0" ),84 , "ISH_GP_1" ),85 , "ISH_GP_2" ),86 , "ISH_GP_3" ),87 , "IMGCLKOUT_0" ),88 , "SRCCLKREQB_0" ),89 , "SRCCLKREQB_1" ),90 , "SRCCLKREQB_2" ),91 , "SRCCLKREQB_3" ),92 , "ISH_SPI_CSB" ),93 , "ISH_SPI_CLK" ),94 , "ISH_SPI_MISO" ),95 , "ISH_SPI_MOSI" ),96 , "ISH_UART0_RXD" ),97 , "ISH_UART0_TXD" ),98 , "ISH_UART0_RTSB" ),99 , "ISH_UART0_CTSB" ),100 , "ISH_GP_4" ),101 , "ISH_GP_5" ),102 , "I2S_MCLK" ),103 , "GSPI2_CLK_LOOPBK" ),/* GPP_F */ 104 , "CNV_BRI_DT" ),105 , "CNV_BRI_RSP" ),106 , "CNV_RGI_DT" ),107 , "CNV_RGI_RSP" ),108 , "CNV_RF_RESET_B" ),109 , "EMMC_HIP_MON" ),110 , "CNV_PA_BLANKING" ),111 , "EMMC_CMD" ),112 , "EMMC_DATA0" ),113 , "EMMC_DATA1" ),114 , "EMMC_DATA2" ),115 , "EMMC_DATA3" ),116 , "EMMC_DATA4" ),117 , "EMMC_DATA5" ),118 , "EMMC_DATA6" ),119 , "EMMC_DATA7" ),120 , "EMMC_RCLK" ),121 , "EMMC_CLK" ),122 , "EMMC_RESETB" ),123 , "A4WP_PRESENT" ),/* vGPIO */ 124 , "CNV_BTEN" ),125 , "CNV_WCEN" ),126 , "CNV_BT_HOST_WAKEB" ),127 , "CNV_BT_IF_SELECT" ),128 , "vCNV_BT_UART_TXD" ),129 , "vCNV_BT_UART_RXD" ),130 , "vCNV_BT_UART_CTS_B" ),131 , "vCNV_BT_UART_RTS_B" ),132 , "vCNV_MFUART1_TXD" ),133 , "vCNV_MFUART1_RXD" ),134 , "vCNV_MFUART1_CTS_B" ),135 , "vCNV_MFUART1_RTS_B" ),136 , "vUART0_TXD" ),137 , "vUART0_RXD" ),138 , "vUART0_CTS_B" ),139 , "vUART0_RTS_B" ),140 , "vISH_UART0_TXD" ),141 , "vISH_UART0_RXD" ),142 , "vISH_UART0_CTS_B" ),143 , "vISH_UART0_RTS_B" ),144 , "vCNV_BT_I2S_BCLK" ),145 , "vCNV_BT_I2S_WS_SYNC" ),146 , "vCNV_BT_I2S_SDO" ),147 , "vCNV_BT_I2S_SDI" ),148 , "vI2S2_SCLK" ),149 , "vI2S2_SFRM" ),150 , "vI2S2_TXD" ),151 , "vI2S2_RXD" ),152 , "vSD3_CD_B" ),/* GPP_C */ 153 , "SMBCLK" ),154 , "SMBDATA" ),155 , "SMBALERTB" ),156 , "SML0CLK" ),157 , "SML0DATA" ),158 , "SML0ALERTB" ),159 , "SML1CLK" ),160 , "SML1DATA" ),161 , "UART0_RXD" ),162 , "UART0_TXD" ),163 , "UART0_RTSB" ),164 , "UART0_CTSB" ),165 , "UART1_RXD" ),166 , "UART1_TXD" ),167 , "UART1_RTSB" ),168 , "UART1_CTSB" ),169 , "I2C0_SDA" ),170 , "I2C0_SCL" ),171 , "I2C1_SDA" ),172 , "I2C1_SCL" ),173 , "UART2_RXD" ),174 , "UART2_TXD" ),175 , "UART2_RTSB" ),176 , "UART2_CTSB" ),/* HVCMOS */ 177 , "L_BKLTEN" ),178 , "L_BKLTCTL" ),179 , "L_VDDEN" ),180 , "SYS_PWROK" ),181 , "SYS_RESETB" ),182 , "MLK_RSTB" ),/* GPP_E */ 183 , "SATAXPCIE_0" ),184 , "SPI1_IO_2" ),185 , "SPI1_IO_3" ),186 , "CPU_GP_0" ),187 , "SATA_DEVSLP_0" ),188 , "SATA_DEVSLP_1" ),189 , "GPPC_E_6" ),190 , "CPU_GP_1" ),191 , "SATA_LEDB" ),192 , "USB2_OCB_0" ),193 , "SPI1_CSB" ),194 , "SPI1_CLK" ),195 , "SPI1_MISO_IO_1" ),196 , "SPI1_MOSI_IO_0" ),197 , "DDSP_HPD_A" ),198 , "ISH_GP_6" ),199 , "ISH_GP_7" ),200 , "DISP_MISC_4" ),201 , "DDP1_CTRLCLK" ),202 , "DDP1_CTRLDATA" ),203 , "DDP2_CTRLCLK" ),204 , "DDP2_CTRLDATA" ),205 , "DDPA_CTRLCLK" ),206 , "DDPA_CTRLDATA" ),/* JTAG */ 207 , "JTAG_TDO" ),208 , "JTAGX" ),209 , "PRDYB" ),210 , "PREQB" ),211 , "CPU_TRSTB" ),212 , "JTAG_TDI" ),213 , "JTAG_TMS" ),214 , "JTAG_TCK" ),215 , "ITP_PMODE" ),/* GPP_R */ 216 , "HDA_BCLK" ),217 , "HDA_SYNC" ),218 , "HDA_SDO" ),219 , "HDA_SDI_0" ),220 , "HDA_RSTB" ),221 , "HDA_SDI_1" ),222 , "I2S1_TXD" ),223 , "I2S1_RXD" ),/* GPP_S */ 224 , "SNDW1_CLK" ),225 , "SNDW1_DATA" ),226 , "SNDW2_CLK" ),227 , "SNDW2_DATA" ),228 , "SNDW3_CLK" ),229 , "SNDW3_DATA" ),230 , "SNDW4_CLK" ),231 , "SNDW4_DATA" ),/* SPI */ 232 , "SPI0_IO_2" ),233 , "SPI0_IO_3" ),234 , "SPI0_MOSI_IO_0" ),235 , "SPI0_MISO_IO_1" ),236 , "SPI0_TPM_CSB" ),237 , "SPI0_FLASH_0_CSB" ),238 , "SPI0_FLASH_1_CSB" ),239 , "SPI0_CLK" ),240 , "SPI0_CLK_LOOPBK" ),static const struct intel_padgroup icllp_community0_gpps[] = {0 , 0 , 7 , 0 ), /* GPP_G */ 1 , 8 , 33 , 32 ), /* GPP_B */ 2 , 34 , 58 , 64 ), /* GPP_A */ static const struct intel_padgroup icllp_community1_gpps[] = {0 , 59 , 82 , 96 ), /* GPP_H */ 1 , 83 , 103 , 128 ), /* GPP_D */ 2 , 104 , 123 , 160 ), /* GPP_F */ 3 , 124 , 152 , 192 ), /* vGPIO */ static const struct intel_padgroup icllp_community4_gpps[] = {0 , 153 , 176 , 224 ), /* GPP_C */ 1 , 177 , 182 , INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 2 , 183 , 206 , 256 ), /* GPP_E */ 3 , 207 , 215 , INTEL_GPIO_BASE_NOMAP), /* JTAG */ static const struct intel_padgroup icllp_community5_gpps[] = {0 , 216 , 223 , 288 ), /* GPP_R */ 1 , 224 , 231 , 320 ), /* GPP_S */ 2 , 232 , 240 , INTEL_GPIO_BASE_NOMAP), /* SPI */ static const struct intel_community icllp_communities[] = {0 , 0 , 58 , icllp_community0_gpps),1 , 59 , 152 , icllp_community1_gpps),2 , 153 , 215 , icllp_community4_gpps),3 , 216 , 240 , icllp_community5_gpps),static const unsigned int icllp_spi0_pins[] = { 22 , 23 , 24 , 25 , 26 };static const unsigned int icllp_spi0_modes[] = { 3 , 1 , 1 , 1 , 1 };static const unsigned int icllp_spi1_pins[] = { 27 , 28 , 29 , 30 , 31 };static const unsigned int icllp_spi1_modes[] = { 1 , 1 , 1 , 1 , 3 };static const unsigned int icllp_spi2_pins[] = { 92 , 93 , 94 , 95 , 98 };static const unsigned int icllp_spi2_modes[] = { 3 , 3 , 3 , 3 , 2 };static const unsigned int icllp_i2c0_pins[] = { 169 , 170 };static const unsigned int icllp_i2c1_pins[] = { 171 , 172 };static const unsigned int icllp_i2c2_pins[] = { 63 , 64 };static const unsigned int icllp_i2c3_pins[] = { 65 , 66 };static const unsigned int icllp_i2c4_pins[] = { 67 , 68 };static const unsigned int icllp_uart0_pins[] = { 161 , 162 , 163 , 164 };static const unsigned int icllp_uart1_pins[] = { 165 , 166 , 167 , 168 };static const unsigned int icllp_uart2_pins[] = { 173 , 174 , 175 , 176 };static const struct intel_pingroup icllp_groups[] = {"spi0_grp" , icllp_spi0_pins, icllp_spi0_modes),"spi1_grp" , icllp_spi1_pins, icllp_spi1_modes),"spi2_grp" , icllp_spi2_pins, icllp_spi2_modes),"i2c0_grp" , icllp_i2c0_pins, 1 ),"i2c1_grp" , icllp_i2c1_pins, 1 ),"i2c2_grp" , icllp_i2c2_pins, 1 ),"i2c3_grp" , icllp_i2c3_pins, 1 ),"i2c4_grp" , icllp_i2c4_pins, 1 ),"uart0_grp" , icllp_uart0_pins, 1 ),"uart1_grp" , icllp_uart1_pins, 1 ),"uart2_grp" , icllp_uart2_pins, 1 ),static const char * const icllp_spi0_groups[] = { "spi0_grp" };static const char * const icllp_spi1_groups[] = { "spi1_grp" };static const char * const icllp_spi2_groups[] = { "spi2_grp" };static const char * const icllp_i2c0_groups[] = { "i2c0_grp" };static const char * const icllp_i2c1_groups[] = { "i2c1_grp" };static const char * const icllp_i2c2_groups[] = { "i2c2_grp" };static const char * const icllp_i2c3_groups[] = { "i2c3_grp" };static const char * const icllp_i2c4_groups[] = { "i2c4_grp" };static const char * const icllp_uart0_groups[] = { "uart0_grp" };static const char * const icllp_uart1_groups[] = { "uart1_grp" };static const char * const icllp_uart2_groups[] = { "uart2_grp" };static const struct intel_function icllp_functions[] = {"spi0" , icllp_spi0_groups),"spi1" , icllp_spi1_groups),"spi2" , icllp_spi2_groups),"i2c0" , icllp_i2c0_groups),"i2c1" , icllp_i2c1_groups),"i2c2" , icllp_i2c2_groups),"i2c3" , icllp_i2c3_groups),"i2c4" , icllp_i2c4_groups),"uart0" , icllp_uart0_groups),"uart1" , icllp_uart1_groups),"uart2" , icllp_uart2_groups),static const struct intel_pinctrl_soc_data icllp_soc_data = {/* Ice Lake-N */ static const struct pinctrl_pin_desc icln_pins[] = {/* SPI */ 0 , "SPI0_IO_2" ),1 , "SPI0_IO_3" ),2 , "SPI0_MOSI_IO_0" ),3 , "SPI0_MISO_IO_1" ),4 , "SPI0_TPM_CSB" ),5 , "SPI0_FLASH_0_CSB" ),6 , "SPI0_FLASH_1_CSB" ),7 , "SPI0_CLK" ),8 , "SPI0_CLK_LOOPBK" ),/* GPP_B */ 9 , "CORE_VID_0" ),10 , "CORE_VID_1" ),11 , "VRALERTB" ),12 , "CPU_GP_2" ),13 , "CPU_GP_3" ),14 , "SRCCLKREQB_0" ),15 , "SRCCLKREQB_1" ),16 , "SRCCLKREQB_2" ),17 , "SRCCLKREQB_3" ),18 , "SRCCLKREQB_4" ),19 , "SRCCLKREQB_5" ),20 , "EXT_PWR_GATEB" ),21 , "SLP_S0B" ),22 , "PLTRSTB" ),23 , "SPKR_GSPI0_CS1B" ),24 , "GSPI0_CS0B" ),25 , "GSPI0_CLK" ),26 , "GSPI0_MISO_TBT_LSX3_A" ),27 , "GSPI0_MOSI_TBT_LSX3_B" ),28 , "GSPI1_CS0B" ),29 , "GSPI1_CLK_NFC_CLK" ),30 , "GSPI1_MISO_NFC_CLKREQ" ),31 , "GSPI1_MOSI" ),32 , "GSPI1_CS1B" ),33 , "GSPI0_CLK_LOOPBK" ),34 , "GSPI1_CLK_LOOPBK" ),/* GPP_A */ 35 , "ESPI_IO_0" ),36 , "ESPI_IO_1" ),37 , "ESPI_IO_2" ),38 , "ESPI_IO_3" ),39 , "ESPI_CSB" ),40 , "ESPI_CLK" ),41 , "ESPI_RESETB" ),42 , "SMBCLK" ),43 , "SMBDATA" ),44 , "SMBALERTB" ),45 , "CPU_GP_0" ),46 , "CPU_GP_1" ),47 , "USB2_OCB_1" ),48 , "USB2_OCB_2" ),49 , "USB2_OCB_3" ),50 , "DDSP_HPD_A_TIME_SYNC_0" ),51 , "DDSP_HPD_B_TIME_SYNC_1" ),52 , "DDSP_HPD_C" ),53 , "USB2_OCB_0" ),54 , "PCHHOTB" ),55 , "ESPI_CLK_LOOPBK" ),/* GPP_S */ 56 , "SNDW1_CLK" ),57 , "SNDW1_DATA" ),58 , "SNDW2_CLK" ),59 , "SNDW2_DATA" ),60 , "SNDW3_CLK_DMIC_CLK_1" ),61 , "SNDW3_DATA_DMIC_DATA_1" ),62 , "SNDW4_CLK_DMIC_CLK_0" ),63 , "SNDW4_DATA_DMIC_DATA_0" ),/* GPP_R */ 64 , "HDA_BCLK" ),65 , "HDA_SYNC" ),66 , "HDA_SDO" ),67 , "HDA_SDI_0" ),68 , "HDA_RSTB" ),69 , "HDA_SDI_1_I2S1_RXD" ),70 , "I2S1_SFRM" ),71 , "I2S1_TXD" ),/* GPP_H */ 72 , "GPPC_H_0" ),73 , "CNV_RF_RESET_B" ),74 , "MODEM_CLKREQ" ),75 , "SX_EXIT_HOLDOFFB" ),76 , "I2C2_SDA" ),77 , "I2C2_SCL" ),78 , "I2C3_SDA" ),79 , "I2C3_SCL" ),80 , "I2C4_SDA" ),81 , "I2C4_SCL" ),82 , "CPU_VCCIO_PWR_GATEB" ),83 , "I2S2_SCLK" ),84 , "CNV_RF_RESET_B" ),85 , "MODEM_CLKREQ" ),86 , "I2S2_RXD" ),87 , "I2S1_SCLK" ),88 , "GPPC_H_16" ),89 , "GPPC_H_17" ),90 , "GPPC_H_18" ),91 , "GPPC_H_19" ),92 , "GPPC_H_20" ),93 , "GPPC_H_21" ),94 , "GPPC_H_22" ),95 , "GPPC_H_23" ),/* GPP_D */ 96 , "SPI1_CSB_BK_0_SBK_0" ),97 , "SPI1_CLK_BK_1_SBK_1" ),98 , "SPI1_MISO_IO_1_BK_2_SBK_2" ),99 , "SPI1_MOSI_IO_0_BK_3_SBK_3" ),100 , "ISH_I2C0_SDA" ),101 , "ISH_I2C0_SCL" ),102 , "ISH_I2C1_SDA" ),103 , "ISH_I2C1_SCL" ),104 , "ISH_SPI_CSB_GSPI2_CS0B_TBT_LSX4_A" ),105 , "ISH_SPI_CLK_GSPI2_CLK_TBT_LSX4_B" ),106 , "ISH_SPI_MISO_GSPI2_MISO_TBT_LSX5_A" ),107 , "ISH_SPI_MOSI_GSPI2_MOSI_TBT_LSX5_B" ),108 , "ISH_UART0_RXD_I2C4B_SDA" ),109 , "ISH_UART0_TXD_I2C4B_SCL" ),110 , "ISH_UART0_RTSB_GSPI2_CS1B" ),111 , "ISH_UART0_CTSB_CNV_WCEN" ),112 , "SPI1_IO_2" ),113 , "SPI1_IO_3" ),114 , "I2S_MCLK" ),115 , "CNV_MFUART2_RXD" ),116 , "CNV_MFUART2_TXD" ),117 , "CNV_PA_BLANKING" ),118 , "I2C5_SDA_ISH_I2C2_SDA" ),119 , "I2C5_SCL_ISH_I2C2_SCL" ),120 , "GSPI2_CLK_LOOPBK" ),121 , "SPI1_CLK_LOOPBK" ),/* vGPIO */ 122 , "CNV_BTEN" ),123 , "CNV_WCEN" ),124 , "CNV_BT_HOST_WAKEB" ),125 , "CNV_BT_IF_SELECT" ),126 , "vCNV_BT_UART_TXD" ),127 , "vCNV_BT_UART_RXD" ),128 , "vCNV_BT_UART_CTS_B" ),129 , "vCNV_BT_UART_RTS_B" ),130 , "vCNV_MFUART1_TXD" ),131 , "vCNV_MFUART1_RXD" ),132 , "vCNV_MFUART1_CTS_B" ),133 , "vCNV_MFUART1_RTS_B" ),134 , "vUART0_TXD" ),135 , "vUART0_RXD" ),136 , "vUART0_CTS_B" ),137 , "vUART0_RTS_B" ),138 , "vISH_UART0_TXD" ),139 , "vISH_UART0_RXD" ),140 , "vISH_UART0_CTS_B" ),141 , "vISH_UART0_RTS_B" ),142 , "vCNV_BT_I2S_BCLK" ),143 , "vCNV_BT_I2S_WS_SYNC" ),144 , "vCNV_BT_I2S_SDO" ),145 , "vCNV_BT_I2S_SDI" ),146 , "vI2S2_SCLK" ),147 , "vI2S2_SFRM" ),148 , "vI2S2_TXD" ),149 , "vI2S2_RXD" ),150 , "vSD3_CD_B" ),/* GPP_C */ 151 , "GPPC_C_0" ),152 , "GPPC_C_1" ),153 , "GPPC_C_2" ),154 , "GPPC_C_3" ),155 , "GPPC_C_4" ),156 , "GPPC_C_5" ),157 , "SUSWARNB_SUSPWRDNACK" ),158 , "SUSACKB" ),159 , "UART0_RXD" ),160 , "UART0_TXD" ),161 , "UART0_RTSB" ),162 , "UART0_CTSB" ),163 , "UART1_RXD_ISH_UART1_RXD" ),164 , "UART1_TXD_ISH_UART1_TXD" ),165 , "UART1_RTSB_ISH_UART1_RTSB" ),166 , "UART1_CTSB_ISH_UART1_CTSB" ),167 , "I2C0_SDA" ),168 , "I2C0_SCL" ),169 , "I2C1_SDA" ),170 , "I2C1_SCL" ),171 , "UART2_RXD_CNV_MFUART0_RXD" ),172 , "UART2_TXD_CNV_MFUART0_TXD" ),173 , "UART2_RTSB_CNV_MFUART0_RTS_B" ),174 , "UART2_CTSB_CNV_MFUART0_CTS_B" ),/* HVCMOS */ 175 , "L_BKLTEN" ),176 , "L_BKLTCTL" ),177 , "L_VDDEN" ),178 , "SYS_PWROK" ),179 , "SYS_RESETB" ),180 , "MLK_RSTB" ),/* GPP_E */ 181 , "ISH_GP_0_IMGCLKOUT_0" ),182 , "ISH_GP_1" ),183 , "IMGCLKOUT_1" ),184 , "ISH_GP_2_SATA_DEVSLP_0" ),185 , "IMGCLKOUT_2" ),186 , "SATA_LEDB_SPI1_CS1B" ),187 , "IMGCLKOUT_3" ),188 , "ISH_GP_3_SATA_DEVSLP_1" ),189 , "FIVR_DIGPB_0" ),190 , "SML0CLK" ),191 , "SML0DATA" ),192 , "BSSB_LS3_RX" ),193 , "BSSB_LS3_TX" ),194 , "BSSB_LS0_RX" ),195 , "BSSB_LS0_TX" ),196 , "BSSB_LS1_RX" ),197 , "BSSB_LS1_TX" ),198 , "BSSB_LS2_RX" ),199 , "BSSB_LS2_TX" ),200 , "FIVR_DIGPB_1" ),201 , "CNV_BRI_DT" ),202 , "CNV_BRI_RSP" ),203 , "CNV_RGI_DT" ),204 , "CNV_RGI_RSP" ),/* GPP_G */ 205 , "SD3_CMD" ),206 , "SD3_D0" ),207 , "SD3_D1" ),208 , "SD3_D2" ),209 , "SD3_D3" ),210 , "SD3_CDB" ),211 , "SD3_CLK" ),212 , "SD3_WP" ),static const struct intel_padgroup icln_community0_gpps[] = {0 , 0 , 8 , INTEL_GPIO_BASE_NOMAP), /* SPI */ 1 , 9 , 34 , 32 ), /* GPP_B */ 2 , 35 , 55 , 64 ), /* GPP_A */ 3 , 56 , 63 , 96 ), /* GPP_S */ 4 , 64 , 71 , 128 ), /* GPP_R */ static const struct intel_padgroup icln_community1_gpps[] = {0 , 72 , 95 , 160 ), /* GPP_H */ 1 , 96 , 121 , 192 ), /* GPP_D */ 2 , 122 , 150 , 224 ), /* vGPIO */ 3 , 151 , 174 , 256 ), /* GPP_C */ static const struct intel_padgroup icln_community4_gpps[] = {0 , 175 , 180 , INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 1 , 181 , 204 , 288 ), /* GPP_E */ static const struct intel_padgroup icln_community5_gpps[] = {0 , 205 , 212 , INTEL_GPIO_BASE_ZERO), /* GPP_G */ static const struct intel_community icln_communities[] = {0 , 0 , 71 , icln_community0_gpps),1 , 72 , 174 , icln_community1_gpps),2 , 175 , 204 , icln_community4_gpps),3 , 205 , 212 , icln_community5_gpps),static const struct intel_pinctrl_soc_data icln_soc_data = {static const struct acpi_device_id icl_pinctrl_acpi_match[] = {"INT3455" , (kernel_ulong_t)&icllp_soc_data },"INT34C3" , (kernel_ulong_t)&icln_soc_data },static struct platform_driver icl_pinctrl_driver = {"icelake-pinctrl" ,"Andy Shevchenko <andriy.shevchenko@linux.intel.com>" );"Mika Westerberg <mika.westerberg@linux.intel.com>" );"Intel Ice Lake PCH pinctrl/GPIO driver" );"GPL v2" );"PINCTRL_INTEL" );
Messung V0.5 in Prozent C=95 H=96 G=95
¤ Dauer der Verarbeitung: 0.13 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
