// SPDX-License-Identifier: GPL-2.0 /* * Intel Gemini Lake SoC pinctrl/GPIO driver * * Copyright (C) 2017 Intel Corporation * Author: Mika Westerberg <mika.westerberg@linux.intel.com> #include <linux/mod_devicetable.h>#include <linux/module.h>#include <linux/platform_device.h>#include <linux/pm.h>#include <linux/pinctrl/pinctrl.h>#include "pinctrl-intel.h" #define GLK_PAD_OWN 0 x020#define GLK_PADCFGLOCK 0 x080#define GLK_HOSTSW_OWN 0 x0b0#define GLK_GPI_IS 0 x100#define GLK_GPI_IE 0 x110#define GLK_COMMUNITY(b, s, e) \32 , 4 , GLK)/* GLK */ static const struct pinctrl_pin_desc glk_northwest_pins[] = {0 , "TCK" ),1 , "TRST_B" ),2 , "TMS" ),3 , "TDI" ),4 , "TDO" ),5 , "JTAGX" ),6 , "CX_PREQ_B" ),7 , "CX_PRDY_B" ),8 , "GPIO_8" ),9 , "GPIO_9" ),10 , "GPIO_10" ),11 , "GPIO_11" ),12 , "GPIO_12" ),13 , "GPIO_13" ),14 , "GPIO_14" ),15 , "GPIO_15" ),16 , "GPIO_16" ),17 , "GPIO_17" ),18 , "GPIO_18" ),19 , "GPIO_19" ),20 , "GPIO_20" ),21 , "GPIO_21" ),22 , "GPIO_22" ),23 , "GPIO_23" ),24 , "GPIO_24" ),25 , "GPIO_25" ),26 , "ISH_GPIO_0" ),27 , "ISH_GPIO_1" ),28 , "ISH_GPIO_2" ),29 , "ISH_GPIO_3" ),30 , "ISH_GPIO_4" ),31 , "ISH_GPIO_5" ),32 , "ISH_GPIO_6" ),33 , "ISH_GPIO_7" ),34 , "ISH_GPIO_8" ),35 , "ISH_GPIO_9" ),36 , "GPIO_36" ),37 , "GPIO_37" ),38 , "GPIO_38" ),39 , "GPIO_39" ),40 , "GPIO_40" ),41 , "GPIO_41" ),42 , "GP_INTD_DSI_TE1" ),43 , "GP_INTD_DSI_TE2" ),44 , "USB_OC0_B" ),45 , "USB_OC1_B" ),46 , "DSI_I2C_SDA" ),47 , "DSI_I2C_SCL" ),48 , "PMC_I2C_SDA" ),49 , "PMC_I2C_SCL" ),50 , "LPSS_I2C0_SDA" ),51 , "LPSS_I2C0_SCL" ),52 , "LPSS_I2C1_SDA" ),53 , "LPSS_I2C1_SCL" ),54 , "LPSS_I2C2_SDA" ),55 , "LPSS_I2C2_SCL" ),56 , "LPSS_I2C3_SDA" ),57 , "LPSS_I2C3_SCL" ),58 , "LPSS_I2C4_SDA" ),59 , "LPSS_I2C4_SCL" ),60 , "LPSS_UART0_RXD" ),61 , "LPSS_UART0_TXD" ),62 , "LPSS_UART0_RTS_B" ),63 , "LPSS_UART0_CTS_B" ),64 , "LPSS_UART2_RXD" ),65 , "LPSS_UART2_TXD" ),66 , "LPSS_UART2_RTS_B" ),67 , "LPSS_UART2_CTS_B" ),68 , "PMC_SPI_FS0" ),69 , "PMC_SPI_FS1" ),70 , "PMC_SPI_FS2" ),71 , "PMC_SPI_RXD" ),72 , "PMC_SPI_TXD" ),73 , "PMC_SPI_CLK" ),74 , "THERMTRIP_B" ),75 , "PROCHOT_B" ),76 , "EMMC_RST_B" ),77 , "GPIO_212" ),78 , "GPIO_213" ),79 , "GPIO_214" ),static const unsigned int glk_northwest_uart1_pins[] = { 26 , 27 , 28 , 29 };static const unsigned int glk_northwest_pwm0_pins[] = { 42 };static const unsigned int glk_northwest_pwm1_pins[] = { 43 };static const unsigned int glk_northwest_pwm2_pins[] = { 44 };static const unsigned int glk_northwest_pwm3_pins[] = { 45 };static const unsigned int glk_northwest_i2c0_pins[] = { 50 , 51 };static const unsigned int glk_northwest_i2c1_pins[] = { 52 , 53 };static const unsigned int glk_northwest_i2c2_pins[] = { 54 , 55 };static const unsigned int glk_northwest_i2c3_pins[] = { 56 , 57 };static const unsigned int glk_northwest_i2c4_pins[] = { 58 , 59 };static const unsigned int glk_northwest_uart0_pins[] = { 60 , 61 , 62 , 63 };static const unsigned int glk_northwest_uart2_pins[] = { 64 , 65 , 66 , 67 };static const struct intel_pingroup glk_northwest_groups[] = {"uart1_grp" , glk_northwest_uart1_pins, 2 ),"pwm0_grp" , glk_northwest_pwm0_pins, 2 ),"pwm1_grp" , glk_northwest_pwm1_pins, 2 ),"pwm2_grp" , glk_northwest_pwm2_pins, 2 ),"pwm3_grp" , glk_northwest_pwm3_pins, 2 ),"i2c0_grp" , glk_northwest_i2c0_pins, 1 ),"i2c1_grp" , glk_northwest_i2c1_pins, 1 ),"i2c2_grp" , glk_northwest_i2c2_pins, 1 ),"i2c3_grp" , glk_northwest_i2c3_pins, 1 ),"i2c4_grp" , glk_northwest_i2c4_pins, 1 ),"uart0_grp" , glk_northwest_uart0_pins, 1 ),"uart2_grp" , glk_northwest_uart2_pins, 1 ),static const char * const glk_northwest_uart1_groups[] = { "uart1_grp" };static const char * const glk_northwest_pwm0_groups[] = { "pwm0_grp" };static const char * const glk_northwest_pwm1_groups[] = { "pwm1_grp" };static const char * const glk_northwest_pwm2_groups[] = { "pwm2_grp" };static const char * const glk_northwest_pwm3_groups[] = { "pwm3_grp" };static const char * const glk_northwest_i2c0_groups[] = { "i2c0_grp" };static const char * const glk_northwest_i2c1_groups[] = { "i2c1_grp" };static const char * const glk_northwest_i2c2_groups[] = { "i2c2_grp" };static const char * const glk_northwest_i2c3_groups[] = { "i2c3_grp" };static const char * const glk_northwest_i2c4_groups[] = { "i2c4_grp" };static const char * const glk_northwest_uart0_groups[] = { "uart0_grp" };static const char * const glk_northwest_uart2_groups[] = { "uart2_grp" };static const struct intel_function glk_northwest_functions[] = {"uart1" , glk_northwest_uart1_groups),"pmw0" , glk_northwest_pwm0_groups),"pmw1" , glk_northwest_pwm1_groups),"pmw2" , glk_northwest_pwm2_groups),"pmw3" , glk_northwest_pwm3_groups),"i2c0" , glk_northwest_i2c0_groups),"i2c1" , glk_northwest_i2c1_groups),"i2c2" , glk_northwest_i2c2_groups),"i2c3" , glk_northwest_i2c3_groups),"i2c4" , glk_northwest_i2c4_groups),"uart0" , glk_northwest_uart0_groups),"uart2" , glk_northwest_uart2_groups),static const struct intel_community glk_northwest_communities[] = {0 , 0 , 79 ),static const struct intel_pinctrl_soc_data glk_northwest_soc_data = {"1" ,static const struct pinctrl_pin_desc glk_north_pins[] = {0 , "SVID0_ALERT_B" ),1 , "SVID0_DATA" ),2 , "SVID0_CLK" ),3 , "LPSS_SPI_0_CLK" ),4 , "LPSS_SPI_0_FS0" ),5 , "LPSS_SPI_0_FS1" ),6 , "LPSS_SPI_0_RXD" ),7 , "LPSS_SPI_0_TXD" ),8 , "LPSS_SPI_2_CLK" ),9 , "LPSS_SPI_2_FS0" ),10 , "LPSS_SPI_2_FS1" ),11 , "LPSS_SPI_2_FS2" ),12 , "LPSS_SPI_2_RXD" ),13 , "LPSS_SPI_2_TXD" ),14 , "FST_SPI_CS0_B" ),15 , "FST_SPI_CS1_B" ),16 , "FST_SPI_MOSI_IO0" ),17 , "FST_SPI_MISO_IO1" ),18 , "FST_SPI_IO2" ),19 , "FST_SPI_IO3" ),20 , "FST_SPI_CLK" ),21 , "FST_SPI_CLK_FB" ),22 , "PMU_PLTRST_B" ),23 , "PMU_PWRBTN_B" ),24 , "PMU_SLP_S0_B" ),25 , "PMU_SLP_S3_B" ),26 , "PMU_SLP_S4_B" ),27 , "SUSPWRDNACK" ),28 , "EMMC_DNX_PWR_EN_B" ),29 , "GPIO_105" ),30 , "PMU_BATLOW_B" ),31 , "PMU_RESETBUTTON_B" ),32 , "PMU_SUSCLK" ),33 , "SUS_STAT_B" ),34 , "LPSS_I2C5_SDA" ),35 , "LPSS_I2C5_SCL" ),36 , "LPSS_I2C6_SDA" ),37 , "LPSS_I2C6_SCL" ),38 , "LPSS_I2C7_SDA" ),39 , "LPSS_I2C7_SCL" ),40 , "PCIE_WAKE0_B" ),41 , "PCIE_WAKE1_B" ),42 , "PCIE_WAKE2_B" ),43 , "PCIE_WAKE3_B" ),44 , "PCIE_CLKREQ0_B" ),45 , "PCIE_CLKREQ1_B" ),46 , "PCIE_CLKREQ2_B" ),47 , "PCIE_CLKREQ3_B" ),48 , "HV_DDI0_DDC_SDA" ),49 , "HV_DDI0_DDC_SCL" ),50 , "HV_DDI1_DDC_SDA" ),51 , "HV_DDI1_DDC_SCL" ),52 , "PANEL0_VDDEN" ),53 , "PANEL0_BKLTEN" ),54 , "PANEL0_BKLTCTL" ),55 , "HV_DDI0_HPD" ),56 , "HV_DDI1_HPD" ),57 , "HV_EDP_HPD" ),58 , "GPIO_134" ),59 , "GPIO_135" ),60 , "GPIO_136" ),61 , "GPIO_137" ),62 , "GPIO_138" ),63 , "GPIO_139" ),64 , "GPIO_140" ),65 , "GPIO_141" ),66 , "GPIO_142" ),67 , "GPIO_143" ),68 , "GPIO_144" ),69 , "GPIO_145" ),70 , "GPIO_146" ),71 , "LPC_ILB_SERIRQ" ),72 , "LPC_CLKOUT0" ),73 , "LPC_CLKOUT1" ),74 , "LPC_AD0" ),75 , "LPC_AD1" ),76 , "LPC_AD2" ),77 , "LPC_AD3" ),78 , "LPC_CLKRUNB" ),79 , "LPC_FRAMEB" ),static const unsigned int glk_north_spi0_pins[] = { 3 , 4 , 5 , 6 , 7 };static const unsigned int glk_north_spi1_pins[] = { 8 , 9 , 10 , 11 , 12 , 13 };static const unsigned int glk_north_i2c5_pins[] = { 34 , 35 };static const unsigned int glk_north_i2c6_pins[] = { 36 , 37 };static const unsigned int glk_north_i2c7_pins[] = { 38 , 39 };static const unsigned int glk_north_uart0_pins[] = { 62 , 63 , 64 , 65 };static const unsigned int glk_north_spi0b_pins[] = { 66 , 67 , 68 , 69 , 70 };static const struct intel_pingroup glk_north_groups[] = {"spi0_grp" , glk_north_spi0_pins, 1 ),"spi1_grp" , glk_north_spi1_pins, 1 ),"i2c5_grp" , glk_north_i2c5_pins, 1 ),"i2c6_grp" , glk_north_i2c6_pins, 1 ),"i2c7_grp" , glk_north_i2c7_pins, 1 ),"uart0_grp" , glk_north_uart0_pins, 2 ),"spi0b_grp" , glk_north_spi0b_pins, 2 ),static const char * const glk_north_spi0_groups[] = { "spi0_grp" , "spi0b_grp" };static const char * const glk_north_spi1_groups[] = { "spi1_grp" };static const char * const glk_north_i2c5_groups[] = { "i2c5_grp" };static const char * const glk_north_i2c6_groups[] = { "i2c6_grp" };static const char * const glk_north_i2c7_groups[] = { "i2c7_grp" };static const char * const glk_north_uart0_groups[] = { "uart0_grp" };static const struct intel_function glk_north_functions[] = {"spi0" , glk_north_spi0_groups),"spi1" , glk_north_spi1_groups),"i2c5" , glk_north_i2c5_groups),"i2c6" , glk_north_i2c6_groups),"i2c7" , glk_north_i2c7_groups),"uart0" , glk_north_uart0_groups),static const struct intel_community glk_north_communities[] = {0 , 0 , 79 ),static const struct intel_pinctrl_soc_data glk_north_soc_data = {"2" ,static const struct pinctrl_pin_desc glk_audio_pins[] = {0 , "AVS_I2S0_MCLK" ),1 , "AVS_I2S0_BCLK" ),2 , "AVS_I2S0_WS_SYNC" ),3 , "AVS_I2S0_SDI" ),4 , "AVS_I2S0_SDO" ),5 , "AVS_I2S1_MCLK" ),6 , "AVS_I2S1_BCLK" ),7 , "AVS_I2S1_WS_SYNC" ),8 , "AVS_I2S1_SDI" ),9 , "AVS_I2S1_SDO" ),10 , "AVS_HDA_BCLK" ),11 , "AVS_HDA_WS_SYNC" ),12 , "AVS_HDA_SDI" ),13 , "AVS_HDA_SDO" ),14 , "AVS_HDA_RSTB" ),15 , "AVS_M_CLK_A1" ),16 , "AVS_M_CLK_B1" ),17 , "AVS_M_DATA_1" ),18 , "AVS_M_CLK_AB2" ),19 , "AVS_M_DATA_2" ),static const struct intel_community glk_audio_communities[] = {0 , 0 , 19 ),static const struct intel_pinctrl_soc_data glk_audio_soc_data = {"3" ,static const struct pinctrl_pin_desc glk_scc_pins[] = {0 , "SMB_ALERTB" ),1 , "SMB_CLK" ),2 , "SMB_DATA" ),3 , "SDCARD_LVL_WP" ),4 , "SDCARD_CLK" ),5 , "SDCARD_CLK_FB" ),6 , "SDCARD_D0" ),7 , "SDCARD_D1" ),8 , "SDCARD_D2" ),9 , "SDCARD_D3" ),10 , "SDCARD_CMD" ),11 , "SDCARD_CD_B" ),12 , "SDCARD_PWR_DOWN_B" ),13 , "GPIO_210" ),14 , "OSC_CLK_OUT_0" ),15 , "OSC_CLK_OUT_1" ),16 , "CNV_BRI_DT" ),17 , "CNV_BRI_RSP" ),18 , "CNV_RGI_DT" ),19 , "CNV_RGI_RSP" ),20 , "CNV_RF_RESET_B" ),21 , "XTAL_CLKREQ" ),22 , "SDIO_CLK_FB" ),23 , "EMMC0_CLK" ),24 , "EMMC0_CLK_FB" ),25 , "EMMC0_D0" ),26 , "EMMC0_D1" ),27 , "EMMC0_D2" ),28 , "EMMC0_D3" ),29 , "EMMC0_D4" ),30 , "EMMC0_D5" ),31 , "EMMC0_D6" ),32 , "EMMC0_D7" ),33 , "EMMC0_CMD" ),34 , "EMMC0_STROBE" ),static const unsigned int glk_scc_i2c7_pins[] = { 1 , 2 };static const unsigned int glk_scc_sdcard_pins[] = {3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 ,static const unsigned int glk_scc_sdio_pins[] = { 16 , 17 , 18 , 19 , 20 , 21 , 22 };static const unsigned int glk_scc_uart1_pins[] = { 16 , 17 , 18 , 19 };static const unsigned int glk_scc_emmc_pins[] = {23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 ,static const struct intel_pingroup glk_scc_groups[] = {"i2c7_grp" , glk_scc_i2c7_pins, 2 ),"sdcard_grp" , glk_scc_sdcard_pins, 1 ),"sdio_grp" , glk_scc_sdio_pins, 2 ),"uart1_grp" , glk_scc_uart1_pins, 3 ),"emmc_grp" , glk_scc_emmc_pins, 1 ),static const char * const glk_scc_i2c7_groups[] = { "i2c7_grp" };static const char * const glk_scc_sdcard_groups[] = { "sdcard_grp" };static const char * const glk_scc_sdio_groups[] = { "sdio_grp" };static const char * const glk_scc_uart1_groups[] = { "uart1_grp" };static const char * const glk_scc_emmc_groups[] = { "emmc_grp" };static const struct intel_function glk_scc_functions[] = {"i2c7" , glk_scc_i2c7_groups),"sdcard" , glk_scc_sdcard_groups),"sdio" , glk_scc_sdio_groups),"uart1" , glk_scc_uart1_groups),"emmc" , glk_scc_emmc_groups),static const struct intel_community glk_scc_communities[] = {0 , 0 , 34 ),static const struct intel_pinctrl_soc_data glk_scc_soc_data = {"4" ,static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = {static const struct acpi_device_id glk_pinctrl_acpi_match[] = {"INT3453" , (kernel_ulong_t)glk_pinctrl_soc_data },static struct platform_driver glk_pinctrl_driver = {"geminilake-pinctrl" ,static int __init glk_pinctrl_init(void )return platform_driver_register(&glk_pinctrl_driver);static void __exit glk_pinctrl_exit(void )"Mika Westerberg <mika.westerberg@linux.intel.com>" );"Intel Gemini Lake SoC pinctrl/GPIO driver" );"GPL v2" );"PINCTRL_INTEL" );
Messung V0.5 in Prozent C=96 H=94 G=94
¤ Dauer der Verarbeitung: 0.13 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
