// SPDX-License-Identifier: GPL-2.0 /* * Intel Elkhart Lake PCH pinctrl/GPIO driver * * Copyright (C) 2019, Intel Corporation * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> #include <linux/mod_devicetable.h>#include <linux/module.h>#include <linux/platform_device.h>#include <linux/pm.h>#include <linux/pinctrl/pinctrl.h>#include "pinctrl-intel.h" #define EHL_PAD_OWN 0 x020#define EHL_PADCFGLOCK 0 x080#define EHL_HOSTSW_OWN 0 x0b0#define EHL_GPI_IS 0 x100#define EHL_GPI_IE 0 x120#define EHL_GPP(r, s, e) \1 ), \#define EHL_COMMUNITY(b, s, e, g) \/* Elkhart Lake */ static const struct pinctrl_pin_desc ehl_community0_pins[] = {/* GPP_B */ 0 , "CORE_VID_0" ),1 , "CORE_VID_1" ),2 , "VRALERTB" ),3 , "CPU_GP_2" ),4 , "CPU_GP_3" ),5 , "OSE_I2C0_SCLK" ),6 , "OSE_I2C0_SDAT" ),7 , "OSE_I2C1_SCLK" ),8 , "OSE_I2C1_SDAT" ),9 , "I2C5_SDA" ),10 , "I2C5_SCL" ),11 , "PMCALERTB" ),12 , "SLP_S0B" ),13 , "PLTRSTB" ),14 , "SPKR" ),15 , "GSPI0_CS0B" ),16 , "GSPI0_CLK" ),17 , "GSPI0_MISO" ),18 , "GSPI0_MOSI" ),19 , "GSPI1_CS0B" ),20 , "GSPI1_CLK" ),21 , "GSPI1_MISO" ),22 , "GSPI1_MOSI" ),23 , "GPPC_B_23" ),24 , "GSPI0_CLK_LOOPBK" ),25 , "GSPI1_CLK_LOOPBK" ),/* GPP_T */ 26 , "OSE_QEPA_2" ),27 , "OSE_QEPB_2" ),28 , "OSE_QEPI_2" ),29 , "GPPC_T_3" ),30 , "RGMII0_INT" ),31 , "RGMII0_RESETB" ),32 , "RGMII0_AUXTS" ),33 , "RGMII0_PPS" ),34 , "USB2_OCB_2" ),35 , "OSE_HSUART2_EN" ),36 , "OSE_HSUART2_RE" ),37 , "USB2_OCB_3" ),38 , "OSE_UART2_RXD" ),39 , "OSE_UART2_TXD" ),40 , "OSE_UART2_RTSB" ),41 , "OSE_UART2_CTSB" ),/* GPP_G */ 42 , "SD3_CMD" ),43 , "SD3_D0" ),44 , "SD3_D1" ),45 , "SD3_D2" ),46 , "SD3_D3" ),47 , "SD3_CDB" ),48 , "SD3_CLK" ),49 , "I2S2_SCLK" ),50 , "I2S2_SFRM" ),51 , "I2S2_TXD" ),52 , "I2S2_RXD" ),53 , "I2S3_SCLK" ),54 , "I2S3_SFRM" ),55 , "I2S3_TXD" ),56 , "I2S3_RXD" ),57 , "ESPI_IO_0" ),58 , "ESPI_IO_1" ),59 , "ESPI_IO_2" ),60 , "ESPI_IO_3" ),61 , "I2S1_SCLK" ),62 , "ESPI_CSB" ),63 , "ESPI_CLK" ),64 , "ESPI_RESETB" ),65 , "SD3_WP" ),66 , "ESPI_CLK_LOOPBK" ),static const struct intel_padgroup ehl_community0_gpps[] = {0 , 0 , 25 ), /* GPP_B */ 1 , 26 , 41 ), /* GPP_T */ 2 , 42 , 66 ), /* GPP_G */ static const struct intel_community ehl_community0[] = {0 , 0 , 66 , ehl_community0_gpps),static const struct intel_pinctrl_soc_data ehl_community0_soc_data = {"0" ,static const struct pinctrl_pin_desc ehl_community1_pins[] = {/* GPP_V */ 0 , "EMMC_CMD" ),1 , "EMMC_DATA0" ),2 , "EMMC_DATA1" ),3 , "EMMC_DATA2" ),4 , "EMMC_DATA3" ),5 , "EMMC_DATA4" ),6 , "EMMC_DATA5" ),7 , "EMMC_DATA6" ),8 , "EMMC_DATA7" ),9 , "EMMC_RCLK" ),10 , "EMMC_CLK" ),11 , "EMMC_RESETB" ),12 , "OSE_TGPIO0" ),13 , "OSE_TGPIO1" ),14 , "OSE_TGPIO2" ),15 , "OSE_TGPIO3" ),/* GPP_H */ 16 , "RGMII1_INT" ),17 , "RGMII1_RESETB" ),18 , "RGMII1_AUXTS" ),19 , "RGMII1_PPS" ),20 , "I2C2_SDA" ),21 , "I2C2_SCL" ),22 , "I2C3_SDA" ),23 , "I2C3_SCL" ),24 , "I2C4_SDA" ),25 , "I2C4_SCL" ),26 , "SRCCLKREQB_4" ),27 , "SRCCLKREQB_5" ),28 , "OSE_UART1_RXD" ),29 , "OSE_UART1_TXD" ),30 , "GPPC_H_14" ),31 , "OSE_UART1_CTSB" ),32 , "PCIE_LNK_DOWN" ),33 , "SD_PWR_EN_B" ),34 , "CPU_C10_GATEB" ),35 , "GPPC_H_19" ),36 , "OSE_PWM7" ),37 , "OSE_HSUART1_DE" ),38 , "OSE_HSUART1_RE" ),39 , "OSE_HSUART1_EN" ),/* GPP_D */ 40 , "OSE_QEPA_0" ),41 , "OSE_QEPB_0" ),42 , "OSE_QEPI_0" ),43 , "OSE_PWM6" ),44 , "OSE_PWM2" ),45 , "SRCCLKREQB_0" ),46 , "SRCCLKREQB_1" ),47 , "SRCCLKREQB_2" ),48 , "SRCCLKREQB_3" ),49 , "OSE_SPI0_CSB" ),50 , "OSE_SPI0_SCLK" ),51 , "OSE_SPI0_MISO" ),52 , "OSE_SPI0_MOSI" ),53 , "OSE_QEPA_1" ),54 , "OSE_QEPB_1" ),55 , "OSE_PWM3" ),56 , "OSE_QEPI_1" ),57 , "OSE_PWM4" ),58 , "OSE_PWM5" ),59 , "I2S_MCLK1_OUT" ),60 , "GSPI2_CLK_LOOPBK" ),/* GPP_U */ 61 , "RGMII2_INT" ),62 , "RGMII2_RESETB" ),63 , "RGMII2_PPS" ),64 , "RGMII2_AUXTS" ),65 , "ISI_SPIM_CS" ),66 , "ISI_SPIM_SCLK" ),67 , "ISI_SPIM_MISO" ),68 , "OSE_QEPA_3" ),69 , "ISI_SPIS_CS" ),70 , "ISI_SPIS_SCLK" ),71 , "ISI_SPIS_MISO" ),72 , "OSE_QEPB_3" ),73 , "ISI_CHX_OKNOK_0" ),74 , "ISI_CHX_OKNOK_1" ),75 , "ISI_CHX_RLY_SWTCH" ),76 , "ISI_CHX_PMIC_EN" ),77 , "ISI_OKNOK_0" ),78 , "ISI_OKNOK_1" ),79 , "ISI_ALERT" ),80 , "OSE_QEPI_3" ),81 , "GSPI3_CLK_LOOPBK" ),82 , "GSPI4_CLK_LOOPBK" ),83 , "GSPI5_CLK_LOOPBK" ),84 , "GSPI6_CLK_LOOPBK" ),/* vGPIO */ 85 , "CNV_BTEN" ),86 , "CNV_BT_HOST_WAKEB" ),87 , "CNV_BT_IF_SELECT" ),88 , "vCNV_BT_UART_TXD" ),89 , "vCNV_BT_UART_RXD" ),90 , "vCNV_BT_UART_CTS_B" ),91 , "vCNV_BT_UART_RTS_B" ),92 , "vCNV_MFUART1_TXD" ),93 , "vCNV_MFUART1_RXD" ),94 , "vCNV_MFUART1_CTS_B" ),95 , "vCNV_MFUART1_RTS_B" ),96 , "vUART0_TXD" ),97 , "vUART0_RXD" ),98 , "vUART0_CTS_B" ),99 , "vUART0_RTS_B" ),100 , "vOSE_UART0_TXD" ),101 , "vOSE_UART0_RXD" ),102 , "vOSE_UART0_CTS_B" ),103 , "vOSE_UART0_RTS_B" ),104 , "vCNV_BT_I2S_BCLK" ),105 , "vCNV_BT_I2S_WS_SYNC" ),106 , "vCNV_BT_I2S_SDO" ),107 , "vCNV_BT_I2S_SDI" ),108 , "vI2S2_SCLK" ),109 , "vI2S2_SFRM" ),110 , "vI2S2_TXD" ),111 , "vI2S2_RXD" ),112 , "vSD3_CD_B" ),static const struct intel_padgroup ehl_community1_gpps[] = {0 , 0 , 15 ), /* GPP_V */ 1 , 16 , 39 ), /* GPP_H */ 2 , 40 , 60 ), /* GPP_D */ 3 , 61 , 84 ), /* GPP_U */ 4 , 85 , 112 ), /* vGPIO */ static const struct intel_community ehl_community1[] = {0 , 0 , 112 , ehl_community1_gpps),static const struct intel_pinctrl_soc_data ehl_community1_soc_data = {"1" ,static const struct pinctrl_pin_desc ehl_community2_pins[] = {/* DSW */ 0 , "BATLOWB" ),1 , "ACPRESENT" ),2 , "LAN_WAKEB" ),3 , "PWRBTNB" ),4 , "SLP_S3B" ),5 , "SLP_S4B" ),6 , "SLP_AB" ),7 , "GPD_7" ),8 , "SUSCLK" ),9 , "SLP_WLANB" ),10 , "SLP_S5B" ),11 , "LANPHYPC" ),12 , "INPUT3VSEL" ),13 , "SLP_LANB" ),14 , "SLP_SUSB" ),15 , "WAKEB" ),16 , "DRAM_RESETB" ),static const struct intel_padgroup ehl_community2_gpps[] = {0 , 0 , 16 ), /* DSW */ static const struct intel_community ehl_community2[] = {0 , 0 , 16 , ehl_community2_gpps),static const struct intel_pinctrl_soc_data ehl_community2_soc_data = {"2" ,static const struct pinctrl_pin_desc ehl_community3_pins[] = {/* CPU */ 0 , "HDACPU_SDI" ),1 , "HDACPU_SDO" ),2 , "HDACPU_BCLK" ),3 , "PM_SYNC" ),4 , "PECI" ),5 , "CPUPWRGD" ),6 , "THRMTRIPB" ),7 , "PLTRST_CPUB" ),8 , "PM_DOWN" ),9 , "TRIGGER_IN" ),10 , "TRIGGER_OUT" ),11 , "UFS_RESETB" ),12 , "CLKOUT_CPURTC" ),13 , "VCCST_OVERRIDE" ),14 , "C10_WAKE" ),15 , "PROCHOTB" ),16 , "CATERRB" ),/* GPP_S */ 17 , "UFS_REF_CLK_0" ),18 , "UFS_REF_CLK_1" ),/* GPP_A */ 19 , "RGMII0_TXDATA_3" ),20 , "RGMII0_TXDATA_2" ),21 , "RGMII0_TXDATA_1" ),22 , "RGMII0_TXDATA_0" ),23 , "RGMII0_TXCLK" ),24 , "RGMII0_TXCTL" ),25 , "RGMII0_RXCLK" ),26 , "RGMII0_RXDATA_3" ),27 , "RGMII0_RXDATA_2" ),28 , "RGMII0_RXDATA_1" ),29 , "RGMII0_RXDATA_0" ),30 , "RGMII1_TXDATA_3" ),31 , "RGMII1_TXDATA_2" ),32 , "RGMII1_TXDATA_1" ),33 , "RGMII1_TXDATA_0" ),34 , "RGMII1_TXCLK" ),35 , "RGMII1_TXCTL" ),36 , "RGMII1_RXCLK" ),37 , "RGMII1_RXCTL" ),38 , "RGMII1_RXDATA_3" ),39 , "RGMII1_RXDATA_2" ),40 , "RGMII1_RXDATA_1" ),41 , "RGMII1_RXDATA_0" ),42 , "RGMII0_RXCTL" ),/* vGPIO_3 */ 43 , "ESPI_USB_OCB_0" ),44 , "ESPI_USB_OCB_1" ),45 , "ESPI_USB_OCB_2" ),46 , "ESPI_USB_OCB_3" ),static const struct intel_padgroup ehl_community3_gpps[] = {0 , 0 , 16 ), /* CPU */ 1 , 17 , 18 ), /* GPP_S */ 2 , 19 , 42 ), /* GPP_A */ 3 , 43 , 46 ), /* vGPIO_3 */ static const struct intel_community ehl_community3[] = {0 , 0 , 46 , ehl_community3_gpps),static const struct intel_pinctrl_soc_data ehl_community3_soc_data = {"3" ,static const struct pinctrl_pin_desc ehl_community4_pins[] = {/* GPP_C */ 0 , "SMBCLK" ),1 , "SMBDATA" ),2 , "OSE_PWM0" ),3 , "RGMII0_MDC" ),4 , "RGMII0_MDIO" ),5 , "OSE_PWM1" ),6 , "RGMII1_MDC" ),7 , "RGMII1_MDIO" ),8 , "OSE_TGPIO4" ),9 , "OSE_HSUART0_EN" ),10 , "OSE_TGPIO5" ),11 , "OSE_HSUART0_RE" ),12 , "OSE_UART0_RXD" ),13 , "OSE_UART0_TXD" ),14 , "OSE_UART0_RTSB" ),15 , "OSE_UART0_CTSB" ),16 , "RGMII2_MDIO" ),17 , "RGMII2_MDC" ),18 , "OSE_I2C4_SDAT" ),19 , "OSE_I2C4_SCLK" ),20 , "OSE_UART4_RXD" ),21 , "OSE_UART4_TXD" ),22 , "OSE_UART4_RTSB" ),23 , "OSE_UART4_CTSB" ),/* GPP_F */ 24 , "CNV_BRI_DT" ),25 , "CNV_BRI_RSP" ),26 , "CNV_RGI_DT" ),27 , "CNV_RGI_RSP" ),28 , "CNV_RF_RESET_B" ),29 , "EMMC_HIP_MON" ),30 , "CNV_PA_BLANKING" ),31 , "OSE_I2S1_SCLK" ),32 , "I2S_MCLK2_INOUT" ),33 , "BOOTMPC" ),34 , "OSE_I2S1_SFRM" ),35 , "GPPC_F_11" ),36 , "GSXDOUT" ),37 , "GSXSLOAD" ),38 , "GSXDIN" ),39 , "GSXSRESETB" ),40 , "GSXCLK" ),41 , "GPPC_F_17" ),42 , "OSE_I2S1_TXD" ),43 , "OSE_I2S1_RXD" ),44 , "EXT_PWR_GATEB" ),45 , "EXT_PWR_GATE2B" ),46 , "VNN_CTRL" ),47 , "V1P05_CTRL" ),48 , "GPPF_CLK_LOOPBACK" ),/* HVCMOS */ 49 , "L_BKLTEN" ),50 , "L_BKLTCTL" ),51 , "L_VDDEN" ),52 , "SYS_PWROK" ),53 , "SYS_RESETB" ),54 , "MLK_RSTB" ),/* GPP_E */ 55 , "SATA_LEDB" ),56 , "GPPC_E_1" ),57 , "GPPC_E_2" ),58 , "DDSP_HPD_B" ),59 , "SATA_DEVSLP_0" ),60 , "DDPB_CTRLDATA" ),61 , "GPPC_E_6" ),62 , "DDPB_CTRLCLK" ),63 , "GPPC_E_8" ),64 , "USB2_OCB_0" ),65 , "GPPC_E_10" ),66 , "GPPC_E_11" ),67 , "GPPC_E_12" ),68 , "GPPC_E_13" ),69 , "DDSP_HPD_A" ),70 , "OSE_I2S0_RXD" ),71 , "OSE_I2S0_TXD" ),72 , "DDSP_HPD_C" ),73 , "DDPA_CTRLDATA" ),74 , "DDPA_CTRLCLK" ),75 , "OSE_I2S0_SCLK" ),76 , "OSE_I2S0_SFRM" ),77 , "DDPC_CTRLDATA" ),78 , "DDPC_CTRLCLK" ),79 , "SPI1_CLK_LOOPBK" ),static const struct intel_padgroup ehl_community4_gpps[] = {0 , 0 , 23 ), /* GPP_C */ 1 , 24 , 48 ), /* GPP_F */ 2 , 49 , 54 ), /* HVCMOS */ 3 , 55 , 79 ), /* GPP_E */ static const struct intel_community ehl_community4[] = {0 , 0 , 79 , ehl_community4_gpps),static const struct intel_pinctrl_soc_data ehl_community4_soc_data = {"4" ,static const struct pinctrl_pin_desc ehl_community5_pins[] = {/* GPP_R */ 0 , "HDA_BCLK" ),1 , "HDA_SYNC" ),2 , "HDA_SDO" ),3 , "HDA_SDI_0" ),4 , "HDA_RSTB" ),5 , "HDA_SDI_1" ),6 , "GPP_R_6" ),7 , "GPP_R_7" ),static const struct intel_padgroup ehl_community5_gpps[] = {0 , 0 , 7 ), /* GPP_R */ static const struct intel_community ehl_community5[] = {0 , 0 , 7 , ehl_community5_gpps),static const struct intel_pinctrl_soc_data ehl_community5_soc_data = {"5" ,static const struct intel_pinctrl_soc_data *ehl_soc_data_array[] = {static const struct acpi_device_id ehl_pinctrl_acpi_match[] = {"INTC1020" , (kernel_ulong_t)ehl_soc_data_array },static struct platform_driver ehl_pinctrl_driver = {"elkhartlake-pinctrl" ,"Andy Shevchenko <andriy.shevchenko@linux.intel.com>" );"Intel Elkhart Lake PCH pinctrl/GPIO driver" );"GPL v2" );"PINCTRL_INTEL" );
Messung V0.5 in Prozent C=96 H=93 G=94
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(vorverarbeitet am 2026-06-07)
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