// SPDX-License-Identifier: GPL-2.0 /* * Intel Denverton SoC pinctrl/GPIO driver * * Copyright (C) 2017, Intel Corporation * Author: Mika Westerberg <mika.westerberg@linux.intel.com> #include <linux/mod_devicetable.h>#include <linux/module.h>#include <linux/platform_device.h>#include <linux/pm.h>#include <linux/pinctrl/pinctrl.h>#include "pinctrl-intel.h" #define DNV_PAD_OWN 0 x020#define DNV_PADCFGLOCK 0 x090#define DNV_HOSTSW_OWN 0 x0C0#define DNV_GPI_IS 0 x100#define DNV_GPI_IE 0 x120#define DNV_GPP(n, s, e) \1 ), \#define DNV_COMMUNITY(b, s, e, g) \/* Denverton */ static const struct pinctrl_pin_desc dnv_pins[] = {/* North ALL */ 0 , "GBE0_SDP0" ),1 , "GBE1_SDP0" ),2 , "GBE0_SDP1" ),3 , "GBE1_SDP1" ),4 , "GBE0_SDP2" ),5 , "GBE1_SDP2" ),6 , "GBE0_SDP3" ),7 , "GBE1_SDP3" ),8 , "GBE2_LED0" ),9 , "GBE2_LED1" ),10 , "GBE0_I2C_CLK" ),11 , "GBE0_I2C_DATA" ),12 , "GBE1_I2C_CLK" ),13 , "GBE1_I2C_DATA" ),14 , "NCSI_RXD0" ),15 , "NCSI_CLK_IN" ),16 , "NCSI_RXD1" ),17 , "NCSI_CRS_DV" ),18 , "IDSLDO_VID_TICKLE" ),19 , "NCSI_TX_EN" ),20 , "NCSI_TXD0" ),21 , "NCSI_TXD1" ),22 , "NCSI_ARB_OUT" ),23 , "GBE0_LED0" ),24 , "GBE0_LED1" ),25 , "GBE1_LED0" ),26 , "GBE1_LED1" ),27 , "SPARE_0" ),28 , "PCIE_CLKREQ0_N" ),29 , "PCIE_CLKREQ1_N" ),30 , "PCIE_CLKREQ2_N" ),31 , "PCIE_CLKREQ3_N" ),32 , "PCIE_CLKREQ4_N" ),33 , "GBE_MDC" ),34 , "GBE_MDIO" ),35 , "SVID_ALERT_N" ),36 , "SVID_DATA" ),37 , "SVID_CLK" ),38 , "THERMTRIP_N" ),39 , "PROCHOT_N" ),40 , "MEMHOT_N" ),/* South DFX */ 41 , "DFX_PORT_CLK0" ),42 , "DFX_PORT_CLK1" ),43 , "DFX_PORT0" ),44 , "DFX_PORT1" ),45 , "DFX_PORT2" ),46 , "DFX_PORT3" ),47 , "DFX_PORT4" ),48 , "DFX_PORT5" ),49 , "DFX_PORT6" ),50 , "DFX_PORT7" ),51 , "DFX_PORT8" ),52 , "DFX_PORT9" ),53 , "DFX_PORT10" ),54 , "DFX_PORT11" ),55 , "DFX_PORT12" ),56 , "DFX_PORT13" ),57 , "DFX_PORT14" ),58 , "DFX_PORT15" ),/* South GPP0 */ 59 , "SPI_TPM_CS_N" ),60 , "UART2_CTS" ),61 , "PCIE_CLKREQ5_N" ),62 , "PCIE_CLKREQ6_N" ),63 , "PCIE_CLKREQ7_N" ),64 , "UART0_RXD" ),65 , "UART0_TXD" ),66 , "CPU_RESET_N" ),67 , "NMI" ),68 , "ERROR2_N" ),69 , "ERROR1_N" ),70 , "ERROR0_N" ),71 , "IERR_N" ),72 , "MCERR_N" ),73 , "SMB0_LEG_CLK" ),74 , "SMB0_LEG_DATA" ),75 , "SMB0_LEG_ALRT_N" ),76 , "SMB1_HOST_DATA" ),77 , "SMB1_HOST_CLK" ),78 , "SMB2_PECI_DATA" ),79 , "SMB2_PECI_CLK" ),80 , "SMB4_CSME0_DATA" ),81 , "SMB4_CSME0_CLK" ),82 , "SMB4_CSME0_ALRT_N" ),83 , "USB_OC0_N" ),84 , "FLEX_CLK_SE0" ),85 , "FLEX_CLK_SE1" ),86 , "SPARE_4" ),87 , "SMB3_IE0_CLK" ),88 , "SMB3_IE0_DATA" ),89 , "SMB3_IE0_ALRT_N" ),90 , "SATA0_LED_N" ),91 , "SATA1_LED_N" ),92 , "SATA_PDETECT0" ),93 , "SATA_PDETECT1" ),94 , "UART1_RTS" ),95 , "UART1_CTS" ),96 , "UART1_RXD" ),97 , "UART1_TXD" ),98 , "SPARE_8" ),99 , "SPARE_9" ),100 , "TCK" ),101 , "TRST_N" ),102 , "TMS" ),103 , "TDI" ),104 , "TDO" ),105 , "CX_PRDY_N" ),106 , "CX_PREQ_N" ),107 , "TAP1_TCK" ),108 , "TAP1_TRST_N" ),109 , "TAP1_TMS" ),110 , "TAP1_TDI" ),111 , "TAP1_TDO" ),/* South GPP1 */ 112 , "SUSPWRDNACK" ),113 , "PMU_SUSCLK" ),114 , "ADR_TRIGGER" ),115 , "PMU_SLP_S45_N" ),116 , "PMU_SLP_S3_N" ),117 , "PMU_WAKE_N" ),118 , "PMU_PWRBTN_N" ),119 , "PMU_RESETBUTTON_N" ),120 , "PMU_PLTRST_N" ),121 , "SUS_STAT_N" ),122 , "SLP_S0IX_N" ),123 , "SPI_CS0_N" ),124 , "SPI_CS1_N" ),125 , "SPI_MOSI_IO0" ),126 , "SPI_MISO_IO1" ),127 , "SPI_IO2" ),128 , "SPI_IO3" ),129 , "SPI_CLK" ),130 , "SPI_CLK_LOOPBK" ),131 , "ESPI_IO0" ),132 , "ESPI_IO1" ),133 , "ESPI_IO2" ),134 , "ESPI_IO3" ),135 , "ESPI_CS0_N" ),136 , "ESPI_CLK" ),137 , "ESPI_RST_N" ),138 , "ESPI_ALRT0_N" ),139 , "ESPI_CS1_N" ),140 , "ESPI_ALRT1_N" ),141 , "ESPI_CLK_LOOPBK" ),142 , "EMMC_CMD" ),143 , "EMMC_STROBE" ),144 , "EMMC_CLK" ),145 , "EMMC_D0" ),146 , "EMMC_D1" ),147 , "EMMC_D2" ),148 , "EMMC_D3" ),149 , "EMMC_D4" ),150 , "EMMC_D5" ),151 , "EMMC_D6" ),152 , "EMMC_D7" ),153 , "SPARE_3" ),static const unsigned int dnv_uart0_pins[] = { 60 , 61 , 64 , 65 };static const unsigned int dnv_uart0_modes[] = { 2 , 3 , 1 , 1 };static const unsigned int dnv_uart1_pins[] = { 94 , 95 , 96 , 97 };static const unsigned int dnv_uart2_pins[] = { 60 , 61 , 62 , 63 };static const unsigned int dnv_uart2_modes[] = { 1 , 2 , 2 , 2 };static const unsigned int dnv_emmc_pins[] = {142 , 143 , 144 , 145 , 146 , 147 , 148 , 149 , 150 , 151 , 152 ,static const struct intel_pingroup dnv_groups[] = {"uart0_grp" , dnv_uart0_pins, dnv_uart0_modes),"uart1_grp" , dnv_uart1_pins, 1 ),"uart2_grp" , dnv_uart2_pins, dnv_uart2_modes),"emmc_grp" , dnv_emmc_pins, 1 ),static const char * const dnv_uart0_groups[] = { "uart0_grp" };static const char * const dnv_uart1_groups[] = { "uart1_grp" };static const char * const dnv_uart2_groups[] = { "uart2_grp" };static const char * const dnv_emmc_groups[] = { "emmc_grp" };static const struct intel_function dnv_functions[] = {"uart0" , dnv_uart0_groups),"uart1" , dnv_uart1_groups),"uart2" , dnv_uart2_groups),"emmc" , dnv_emmc_groups),static const struct intel_padgroup dnv_north_gpps[] = {0 , 0 , 31 ), /* North ALL_0 */ 1 , 32 , 40 ), /* North ALL_1 */ static const struct intel_padgroup dnv_south_gpps[] = {0 , 41 , 58 ), /* South DFX */ 1 , 59 , 90 ), /* South GPP0_0 */ 2 , 91 , 111 ), /* South GPP0_1 */ 3 , 112 , 143 ), /* South GPP1_0 */ 4 , 144 , 153 ), /* South GPP1_1 */ static const struct intel_community dnv_communities[] = {0 , 0 , 40 , dnv_north_gpps),1 , 41 , 153 , dnv_south_gpps),static const struct intel_pinctrl_soc_data dnv_soc_data = {static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {"INTC3000" , (kernel_ulong_t)&dnv_soc_data },static const struct platform_device_id dnv_pinctrl_platform_ids[] = {"denverton-pinctrl" , (kernel_ulong_t)&dnv_soc_data },static struct platform_driver dnv_pinctrl_driver = {"denverton-pinctrl" ,static int __init dnv_pinctrl_init(void )return platform_driver_register(&dnv_pinctrl_driver);static void __exit dnv_pinctrl_exit(void )"Mika Westerberg <mika.westerberg@linux.intel.com>" );"Intel Denverton SoC pinctrl/GPIO driver" );"GPL v2" );"PINCTRL_INTEL" );
Messung V0.5 in Prozent C=96 H=90 G=93
¤ Dauer der Verarbeitung: 0.12 Sekunden
(vorverarbeitet am 2026-06-08)
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