// SPDX-License-Identifier: GPL-2.0 /* * Intel Cannon Lake PCH pinctrl/GPIO driver * * Copyright (C) 2017, Intel Corporation * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> * Mika Westerberg <mika.westerberg@linux.intel.com> #include <linux/mod_devicetable.h>#include <linux/module.h>#include <linux/platform_device.h>#include <linux/pm.h>#include <linux/pinctrl/pinctrl.h>#include "pinctrl-intel.h" #define CNL_LP_PAD_OWN 0 x020#define CNL_LP_PADCFGLOCK 0 x080#define CNL_LP_HOSTSW_OWN 0 x0b0#define CNL_LP_GPI_IS 0 x100#define CNL_LP_GPI_IE 0 x120#define CNL_H_PAD_OWN 0 x020#define CNL_H_PADCFGLOCK 0 x080#define CNL_H_HOSTSW_OWN 0 x0c0#define CNL_H_GPI_IS 0 x100#define CNL_H_GPI_IE 0 x120#define CNL_GPP(r, s, e, g) \1 ), \#define CNL_LP_COMMUNITY(b, s, e, g) \#define CNL_H_COMMUNITY(b, s, e, g) \/* Cannon Lake-H */ static const struct pinctrl_pin_desc cnlh_pins[] = {/* GPP_A */ 0 , "RCINB" ),1 , "LAD_0" ),2 , "LAD_1" ),3 , "LAD_2" ),4 , "LAD_3" ),5 , "LFRAMEB" ),6 , "SERIRQ" ),7 , "PIRQAB" ),8 , "CLKRUNB" ),9 , "CLKOUT_LPC_0" ),10 , "CLKOUT_LPC_1" ),11 , "PMEB" ),12 , "BM_BUSYB" ),13 , "SUSWARNB_SUSPWRDNACK" ),14 , "SUS_STATB" ),15 , "SUSACKB" ),16 , "CLKOUT_48" ),17 , "SD_VDD1_PWR_EN_B" ),18 , "ISH_GP_0" ),19 , "ISH_GP_1" ),20 , "ISH_GP_2" ),21 , "ISH_GP_3" ),22 , "ISH_GP_4" ),23 , "ISH_GP_5" ),24 , "ESPI_CLK_LOOPBK" ),/* GPP_B */ 25 , "GSPI0_CS1B" ),26 , "GSPI1_CS1B" ),27 , "VRALERTB" ),28 , "CPU_GP_2" ),29 , "CPU_GP_3" ),30 , "SRCCLKREQB_0" ),31 , "SRCCLKREQB_1" ),32 , "SRCCLKREQB_2" ),33 , "SRCCLKREQB_3" ),34 , "SRCCLKREQB_4" ),35 , "SRCCLKREQB_5" ),36 , "SSP_MCLK" ),37 , "SLP_S0B" ),38 , "PLTRSTB" ),39 , "SPKR" ),40 , "GSPI0_CS0B" ),41 , "GSPI0_CLK" ),42 , "GSPI0_MISO" ),43 , "GSPI0_MOSI" ),44 , "GSPI1_CS0B" ),45 , "GSPI1_CLK" ),46 , "GSPI1_MISO" ),47 , "GSPI1_MOSI" ),48 , "SML1ALERTB" ),49 , "GSPI0_CLK_LOOPBK" ),50 , "GSPI1_CLK_LOOPBK" ),/* GPP_C */ 51 , "SMBCLK" ),52 , "SMBDATA" ),53 , "SMBALERTB" ),54 , "SML0CLK" ),55 , "SML0DATA" ),56 , "SML0ALERTB" ),57 , "SML1CLK" ),58 , "SML1DATA" ),59 , "UART0_RXD" ),60 , "UART0_TXD" ),61 , "UART0_RTSB" ),62 , "UART0_CTSB" ),63 , "UART1_RXD" ),64 , "UART1_TXD" ),65 , "UART1_RTSB" ),66 , "UART1_CTSB" ),67 , "I2C0_SDA" ),68 , "I2C0_SCL" ),69 , "I2C1_SDA" ),70 , "I2C1_SCL" ),71 , "UART2_RXD" ),72 , "UART2_TXD" ),73 , "UART2_RTSB" ),74 , "UART2_CTSB" ),/* GPP_D */ 75 , "SPI1_CSB" ),76 , "SPI1_CLK" ),77 , "SPI1_MISO_IO_1" ),78 , "SPI1_MOSI_IO_0" ),79 , "ISH_I2C2_SDA" ),80 , "SSP2_SFRM" ),81 , "SSP2_TXD" ),82 , "SSP2_RXD" ),83 , "SSP2_SCLK" ),84 , "ISH_SPI_CSB" ),85 , "ISH_SPI_CLK" ),86 , "ISH_SPI_MISO" ),87 , "ISH_SPI_MOSI" ),88 , "ISH_UART0_RXD" ),89 , "ISH_UART0_TXD" ),90 , "ISH_UART0_RTSB" ),91 , "ISH_UART0_CTSB" ),92 , "DMIC_CLK_1" ),93 , "DMIC_DATA_1" ),94 , "DMIC_CLK_0" ),95 , "DMIC_DATA_0" ),96 , "SPI1_IO_2" ),97 , "SPI1_IO_3" ),98 , "ISH_I2C2_SCL" ),/* GPP_G */ 99 , "SD3_CMD" ),100 , "SD3_D0" ),101 , "SD3_D1" ),102 , "SD3_D2" ),103 , "SD3_D3" ),104 , "SD3_CDB" ),105 , "SD3_CLK" ),106 , "SD3_WP" ),/* AZA */ 107 , "HDA_BCLK" ),108 , "HDA_RSTB" ),109 , "HDA_SYNC" ),110 , "HDA_SDO" ),111 , "HDA_SDI_0" ),112 , "HDA_SDI_1" ),113 , "SSP1_SFRM" ),114 , "SSP1_TXD" ),/* vGPIO */ 115 , "CNV_BTEN" ),116 , "CNV_GNEN" ),117 , "CNV_WFEN" ),118 , "CNV_WCEN" ),119 , "CNV_BT_HOST_WAKEB" ),120 , "vCNV_GNSS_HOST_WAKEB" ),121 , "vSD3_CD_B" ),122 , "CNV_BT_IF_SELECT" ),123 , "vCNV_BT_UART_TXD" ),124 , "vCNV_BT_UART_RXD" ),125 , "vCNV_BT_UART_CTS_B" ),126 , "vCNV_BT_UART_RTS_B" ),127 , "vCNV_MFUART1_TXD" ),128 , "vCNV_MFUART1_RXD" ),129 , "vCNV_MFUART1_CTS_B" ),130 , "vCNV_MFUART1_RTS_B" ),131 , "vCNV_GNSS_UART_TXD" ),132 , "vCNV_GNSS_UART_RXD" ),133 , "vCNV_GNSS_UART_CTS_B" ),134 , "vCNV_GNSS_UART_RTS_B" ),135 , "vUART0_TXD" ),136 , "vUART0_RXD" ),137 , "vUART0_CTS_B" ),138 , "vUART0_RTSB" ),139 , "vISH_UART0_TXD" ),140 , "vISH_UART0_RXD" ),141 , "vISH_UART0_CTS_B" ),142 , "vISH_UART0_RTSB" ),143 , "vISH_UART1_TXD" ),144 , "vISH_UART1_RXD" ),145 , "vISH_UART1_CTS_B" ),146 , "vISH_UART1_RTS_B" ),147 , "vCNV_BT_I2S_BCLK" ),148 , "vCNV_BT_I2S_WS_SYNC" ),149 , "vCNV_BT_I2S_SDO" ),150 , "vCNV_BT_I2S_SDI" ),151 , "vSSP2_SCLK" ),152 , "vSSP2_SFRM" ),153 , "vSSP2_TXD" ),154 , "vSSP2_RXD" ),/* GPP_K */ 155 , "FAN_TACH_0" ),156 , "FAN_TACH_1" ),157 , "FAN_TACH_2" ),158 , "FAN_TACH_3" ),159 , "FAN_TACH_4" ),160 , "FAN_TACH_5" ),161 , "FAN_TACH_6" ),162 , "FAN_TACH_7" ),163 , "FAN_PWM_0" ),164 , "FAN_PWM_1" ),165 , "FAN_PWM_2" ),166 , "FAN_PWM_3" ),167 , "GSXDOUT" ),168 , "GSXSLOAD" ),169 , "GSXDIN" ),170 , "GSXSRESETB" ),171 , "GSXCLK" ),172 , "ADR_COMPLETE" ),173 , "NMIB" ),174 , "SMIB" ),175 , "CORE_VID_0" ),176 , "CORE_VID_1" ),177 , "IMGCLKOUT_0" ),178 , "IMGCLKOUT_1" ),/* GPP_H */ 179 , "SRCCLKREQB_6" ),180 , "SRCCLKREQB_7" ),181 , "SRCCLKREQB_8" ),182 , "SRCCLKREQB_9" ),183 , "SRCCLKREQB_10" ),184 , "SRCCLKREQB_11" ),185 , "SRCCLKREQB_12" ),186 , "SRCCLKREQB_13" ),187 , "SRCCLKREQB_14" ),188 , "SRCCLKREQB_15" ),189 , "SML2CLK" ),190 , "SML2DATA" ),191 , "SML2ALERTB" ),192 , "SML3CLK" ),193 , "SML3DATA" ),194 , "SML3ALERTB" ),195 , "SML4CLK" ),196 , "SML4DATA" ),197 , "SML4ALERTB" ),198 , "ISH_I2C0_SDA" ),199 , "ISH_I2C0_SCL" ),200 , "ISH_I2C1_SDA" ),201 , "ISH_I2C1_SCL" ),202 , "TIME_SYNC_0" ),/* GPP_E */ 203 , "SATAXPCIE_0" ),204 , "SATAXPCIE_1" ),205 , "SATAXPCIE_2" ),206 , "CPU_GP_0" ),207 , "SATA_DEVSLP_0" ),208 , "SATA_DEVSLP_1" ),209 , "SATA_DEVSLP_2" ),210 , "CPU_GP_1" ),211 , "SATA_LEDB" ),212 , "USB2_OCB_0" ),213 , "USB2_OCB_1" ),214 , "USB2_OCB_2" ),215 , "USB2_OCB_3" ),/* GPP_F */ 216 , "SATAXPCIE_3" ),217 , "SATAXPCIE_4" ),218 , "SATAXPCIE_5" ),219 , "SATAXPCIE_6" ),220 , "SATAXPCIE_7" ),221 , "SATA_DEVSLP_3" ),222 , "SATA_DEVSLP_4" ),223 , "SATA_DEVSLP_5" ),224 , "SATA_DEVSLP_6" ),225 , "SATA_DEVSLP_7" ),226 , "SATA_SCLOCK" ),227 , "SATA_SLOAD" ),228 , "SATA_SDATAOUT1" ),229 , "SATA_SDATAOUT0" ),230 , "EXT_PWR_GATEB" ),231 , "USB2_OCB_4" ),232 , "USB2_OCB_5" ),233 , "USB2_OCB_6" ),234 , "USB2_OCB_7" ),235 , "L_VDDEN" ),236 , "L_BKLTEN" ),237 , "L_BKLTCTL" ),238 , "DDPF_CTRLCLK" ),239 , "DDPF_CTRLDATA" ),/* SPI */ 240 , "SPI0_IO_2" ),241 , "SPI0_IO_3" ),242 , "SPI0_MOSI_IO_0" ),243 , "SPI0_MISO_IO_1" ),244 , "SPI0_TPM_CSB" ),245 , "SPI0_FLASH_0_CSB" ),246 , "SPI0_FLASH_1_CSB" ),247 , "SPI0_CLK" ),248 , "SPI0_CLK_LOOPBK" ),/* CPU */ 249 , "HDACPU_SDI" ),250 , "HDACPU_SDO" ),251 , "HDACPU_SCLK" ),252 , "PM_SYNC" ),253 , "PECI" ),254 , "CPUPWRGD" ),255 , "THRMTRIPB" ),256 , "PLTRST_CPUB" ),257 , "PM_DOWN" ),258 , "TRIGGER_IN" ),259 , "TRIGGER_OUT" ),/* JTAG */ 260 , "JTAG_TDO" ),261 , "JTAGX" ),262 , "PRDYB" ),263 , "PREQB" ),264 , "CPU_TRSTB" ),265 , "JTAG_TDI" ),266 , "JTAG_TMS" ),267 , "JTAG_TCK" ),268 , "ITP_PMODE" ),/* GPP_I */ 269 , "DDSP_HPD_0" ),270 , "DDSP_HPD_1" ),271 , "DDSP_HPD_2" ),272 , "DDSP_HPD_3" ),273 , "EDP_HPD" ),274 , "DDPB_CTRLCLK" ),275 , "DDPB_CTRLDATA" ),276 , "DDPC_CTRLCLK" ),277 , "DDPC_CTRLDATA" ),278 , "DDPD_CTRLCLK" ),279 , "DDPD_CTRLDATA" ),280 , "M2_SKT2_CFG_0" ),281 , "M2_SKT2_CFG_1" ),282 , "M2_SKT2_CFG_2" ),283 , "M2_SKT2_CFG_3" ),284 , "SYS_PWROK" ),285 , "SYS_RESETB" ),286 , "MLK_RSTB" ),/* GPP_J */ 287 , "CNV_PA_BLANKING" ),288 , "CNV_GNSS_FTA" ),289 , "CNV_GNSS_SYSCK" ),290 , "CNV_RF_RESET_B" ),291 , "CNV_BRI_DT" ),292 , "CNV_BRI_RSP" ),293 , "CNV_RGI_DT" ),294 , "CNV_RGI_RSP" ),295 , "CNV_MFUART2_RXD" ),296 , "CNV_MFUART2_TXD" ),297 , "CNV_MODEM_CLKREQ" ),298 , "A4WP_PRESENT" ),static const struct intel_padgroup cnlh_community0_gpps[] = {0 , 0 , 24 , 0 ), /* GPP_A */ 1 , 25 , 50 , 32 ), /* GPP_B */ static const struct intel_padgroup cnlh_community1_gpps[] = {0 , 51 , 74 , 64 ), /* GPP_C */ 1 , 75 , 98 , 96 ), /* GPP_D */ 2 , 99 , 106 , 128 ), /* GPP_G */ 3 , 107 , 114 , INTEL_GPIO_BASE_NOMAP), /* AZA */ 4 , 115 , 146 , 160 ), /* vGPIO_0 */ 5 , 147 , 154 , INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */ static const struct intel_padgroup cnlh_community3_gpps[] = {0 , 155 , 178 , 192 ), /* GPP_K */ 1 , 179 , 202 , 224 ), /* GPP_H */ 2 , 203 , 215 , 256 ), /* GPP_E */ 3 , 216 , 239 , 288 ), /* GPP_F */ 4 , 240 , 248 , INTEL_GPIO_BASE_NOMAP), /* SPI */ static const struct intel_padgroup cnlh_community4_gpps[] = {0 , 249 , 259 , INTEL_GPIO_BASE_NOMAP), /* CPU */ 1 , 260 , 268 , INTEL_GPIO_BASE_NOMAP), /* JTAG */ 2 , 269 , 286 , 320 ), /* GPP_I */ 3 , 287 , 298 , 352 ), /* GPP_J */ static const unsigned int cnlh_spi0_pins[] = { 40 , 41 , 42 , 43 };static const unsigned int cnlh_spi1_pins[] = { 44 , 45 , 46 , 47 };static const unsigned int cnlh_spi2_pins[] = { 84 , 85 , 86 , 87 };static const unsigned int cnlh_uart0_pins[] = { 59 , 60 , 61 , 62 };static const unsigned int cnlh_uart1_pins[] = { 63 , 64 , 65 , 66 };static const unsigned int cnlh_uart2_pins[] = { 71 , 72 , 73 , 74 };static const unsigned int cnlh_i2c0_pins[] = { 67 , 68 };static const unsigned int cnlh_i2c1_pins[] = { 69 , 70 };static const unsigned int cnlh_i2c2_pins[] = { 88 , 89 };static const unsigned int cnlh_i2c3_pins[] = { 79 , 98 };static const struct intel_pingroup cnlh_groups[] = {"spi0_grp" , cnlh_spi0_pins, 1 ),"spi1_grp" , cnlh_spi1_pins, 1 ),"spi2_grp" , cnlh_spi2_pins, 3 ),"uart0_grp" , cnlh_uart0_pins, 1 ),"uart1_grp" , cnlh_uart1_pins, 1 ),"uart2_grp" , cnlh_uart2_pins, 1 ),"i2c0_grp" , cnlh_i2c0_pins, 1 ),"i2c1_grp" , cnlh_i2c1_pins, 1 ),"i2c2_grp" , cnlh_i2c2_pins, 3 ),"i2c3_grp" , cnlh_i2c3_pins, 2 ),static const char * const cnlh_spi0_groups[] = { "spi0_grp" };static const char * const cnlh_spi1_groups[] = { "spi1_grp" };static const char * const cnlh_spi2_groups[] = { "spi2_grp" };static const char * const cnlh_uart0_groups[] = { "uart0_grp" };static const char * const cnlh_uart1_groups[] = { "uart1_grp" };static const char * const cnlh_uart2_groups[] = { "uart2_grp" };static const char * const cnlh_i2c0_groups[] = { "i2c0_grp" };static const char * const cnlh_i2c1_groups[] = { "i2c1_grp" };static const char * const cnlh_i2c2_groups[] = { "i2c2_grp" };static const char * const cnlh_i2c3_groups[] = { "i2c3_grp" };static const struct intel_function cnlh_functions[] = {"spi0" , cnlh_spi0_groups),"spi1" , cnlh_spi1_groups),"spi2" , cnlh_spi2_groups),"uart0" , cnlh_uart0_groups),"uart1" , cnlh_uart1_groups),"uart2" , cnlh_uart2_groups),"i2c0" , cnlh_i2c0_groups),"i2c1" , cnlh_i2c1_groups),"i2c2" , cnlh_i2c2_groups),"i2c3" , cnlh_i2c3_groups),static const struct intel_community cnlh_communities[] = {0 , 0 , 50 , cnlh_community0_gpps),1 , 51 , 154 , cnlh_community1_gpps),2 , 155 , 248 , cnlh_community3_gpps),3 , 249 , 298 , cnlh_community4_gpps),static const struct intel_pinctrl_soc_data cnlh_soc_data = {/* Cannon Lake-LP */ static const struct pinctrl_pin_desc cnllp_pins[] = {/* GPP_A */ 0 , "RCINB" ),1 , "LAD_0" ),2 , "LAD_1" ),3 , "LAD_2" ),4 , "LAD_3" ),5 , "LFRAMEB" ),6 , "SERIRQ" ),7 , "PIRQAB" ),8 , "CLKRUNB" ),9 , "CLKOUT_LPC_0" ),10 , "CLKOUT_LPC_1" ),11 , "PMEB" ),12 , "BM_BUSYB" ),13 , "SUSWARNB_SUSPWRDNACK" ),14 , "SUS_STATB" ),15 , "SUSACKB" ),16 , "SD_1P8_SEL" ),17 , "SD_PWR_EN_B" ),18 , "ISH_GP_0" ),19 , "ISH_GP_1" ),20 , "ISH_GP_2" ),21 , "ISH_GP_3" ),22 , "ISH_GP_4" ),23 , "ISH_GP_5" ),24 , "ESPI_CLK_LOOPBK" ),/* GPP_B */ 25 , "CORE_VID_0" ),26 , "CORE_VID_1" ),27 , "VRALERTB" ),28 , "CPU_GP_2" ),29 , "CPU_GP_3" ),30 , "SRCCLKREQB_0" ),31 , "SRCCLKREQB_1" ),32 , "SRCCLKREQB_2" ),33 , "SRCCLKREQB_3" ),34 , "SRCCLKREQB_4" ),35 , "SRCCLKREQB_5" ),36 , "EXT_PWR_GATEB" ),37 , "SLP_S0B" ),38 , "PLTRSTB" ),39 , "SPKR" ),40 , "GSPI0_CS0B" ),41 , "GSPI0_CLK" ),42 , "GSPI0_MISO" ),43 , "GSPI0_MOSI" ),44 , "GSPI1_CS0B" ),45 , "GSPI1_CLK" ),46 , "GSPI1_MISO" ),47 , "GSPI1_MOSI" ),48 , "SML1ALERTB" ),49 , "GSPI0_CLK_LOOPBK" ),50 , "GSPI1_CLK_LOOPBK" ),/* GPP_G */ 51 , "SD3_CMD" ),52 , "SD3_D0_SD4_RCLK_P" ),53 , "SD3_D1_SD4_RCLK_N" ),54 , "SD3_D2" ),55 , "SD3_D3" ),56 , "SD3_CDB" ),57 , "SD3_CLK" ),58 , "SD3_WP" ),/* SPI */ 59 , "SPI0_IO_2" ),60 , "SPI0_IO_3" ),61 , "SPI0_MOSI_IO_0" ),62 , "SPI0_MISO_IO_1" ),63 , "SPI0_TPM_CSB" ),64 , "SPI0_FLASH_0_CSB" ),65 , "SPI0_FLASH_1_CSB" ),66 , "SPI0_CLK" ),67 , "SPI0_CLK_LOOPBK" ),/* GPP_D */ 68 , "SPI1_CSB" ),69 , "SPI1_CLK" ),70 , "SPI1_MISO_IO_1" ),71 , "SPI1_MOSI_IO_0" ),72 , "IMGCLKOUT_0" ),73 , "ISH_I2C0_SDA" ),74 , "ISH_I2C0_SCL" ),75 , "ISH_I2C1_SDA" ),76 , "ISH_I2C1_SCL" ),77 , "ISH_SPI_CSB" ),78 , "ISH_SPI_CLK" ),79 , "ISH_SPI_MISO" ),80 , "ISH_SPI_MOSI" ),81 , "ISH_UART0_RXD" ),82 , "ISH_UART0_TXD" ),83 , "ISH_UART0_RTSB" ),84 , "ISH_UART0_CTSB" ),85 , "DMIC_CLK_1" ),86 , "DMIC_DATA_1" ),87 , "DMIC_CLK_0" ),88 , "DMIC_DATA_0" ),89 , "SPI1_IO_2" ),90 , "SPI1_IO_3" ),91 , "SSP_MCLK" ),92 , "GSPI2_CLK_LOOPBK" ),/* GPP_F */ 93 , "CNV_GNSS_PA_BLANKING" ),94 , "CNV_GNSS_FTA" ),95 , "CNV_GNSS_SYSCK" ),96 , "EMMC_HIP_MON" ),97 , "CNV_BRI_DT" ),98 , "CNV_BRI_RSP" ),99 , "CNV_RGI_DT" ),100 , "CNV_RGI_RSP" ),101 , "CNV_MFUART2_RXD" ),102 , "CNV_MFUART2_TXD" ),103 , "GPP_F_10" ),104 , "EMMC_CMD" ),105 , "EMMC_DATA_0" ),106 , "EMMC_DATA_1" ),107 , "EMMC_DATA_2" ),108 , "EMMC_DATA_3" ),109 , "EMMC_DATA_4" ),110 , "EMMC_DATA_5" ),111 , "EMMC_DATA_6" ),112 , "EMMC_DATA_7" ),113 , "EMMC_RCLK" ),114 , "EMMC_CLK" ),115 , "EMMC_RESETB" ),116 , "A4WP_PRESENT" ),/* GPP_H */ 117 , "SSP2_SCLK" ),118 , "SSP2_SFRM" ),119 , "SSP2_TXD" ),120 , "SSP2_RXD" ),121 , "I2C2_SDA" ),122 , "I2C2_SCL" ),123 , "I2C3_SDA" ),124 , "I2C3_SCL" ),125 , "I2C4_SDA" ),126 , "I2C4_SCL" ),127 , "I2C5_SDA" ),128 , "I2C5_SCL" ),129 , "M2_SKT2_CFG_0" ),130 , "M2_SKT2_CFG_1" ),131 , "M2_SKT2_CFG_2" ),132 , "M2_SKT2_CFG_3" ),133 , "DDPF_CTRLCLK" ),134 , "DDPF_CTRLDATA" ),135 , "CPU_VCCIO_PWR_GATEB" ),136 , "TIMESYNC_0" ),137 , "IMGCLKOUT_1" ),138 , "GPPC_H_21" ),139 , "GPPC_H_22" ),140 , "GPPC_H_23" ),/* vGPIO */ 141 , "CNV_BTEN" ),142 , "CNV_GNEN" ),143 , "CNV_WFEN" ),144 , "CNV_WCEN" ),145 , "CNV_BT_HOST_WAKEB" ),146 , "CNV_BT_IF_SELECT" ),147 , "vCNV_BT_UART_TXD" ),148 , "vCNV_BT_UART_RXD" ),149 , "vCNV_BT_UART_CTS_B" ),150 , "vCNV_BT_UART_RTS_B" ),151 , "vCNV_MFUART1_TXD" ),152 , "vCNV_MFUART1_RXD" ),153 , "vCNV_MFUART1_CTS_B" ),154 , "vCNV_MFUART1_RTS_B" ),155 , "vCNV_GNSS_UART_TXD" ),156 , "vCNV_GNSS_UART_RXD" ),157 , "vCNV_GNSS_UART_CTS_B" ),158 , "vCNV_GNSS_UART_RTS_B" ),159 , "vUART0_TXD" ),160 , "vUART0_RXD" ),161 , "vUART0_CTS_B" ),162 , "vUART0_RTS_B" ),163 , "vISH_UART0_TXD" ),164 , "vISH_UART0_RXD" ),165 , "vISH_UART0_CTS_B" ),166 , "vISH_UART0_RTS_B" ),167 , "vISH_UART1_TXD" ),168 , "vISH_UART1_RXD" ),169 , "vISH_UART1_CTS_B" ),170 , "vISH_UART1_RTS_B" ),171 , "vCNV_BT_I2S_BCLK" ),172 , "vCNV_BT_I2S_WS_SYNC" ),173 , "vCNV_BT_I2S_SDO" ),174 , "vCNV_BT_I2S_SDI" ),175 , "vSSP2_SCLK" ),176 , "vSSP2_SFRM" ),177 , "vSSP2_TXD" ),178 , "vSSP2_RXD" ),179 , "vCNV_GNSS_HOST_WAKEB" ),180 , "vSD3_CD_B" ),/* GPP_C */ 181 , "SMBCLK" ),182 , "SMBDATA" ),183 , "SMBALERTB" ),184 , "SML0CLK" ),185 , "SML0DATA" ),186 , "SML0ALERTB" ),187 , "SML1CLK" ),188 , "SML1DATA" ),189 , "UART0_RXD" ),190 , "UART0_TXD" ),191 , "UART0_RTSB" ),192 , "UART0_CTSB" ),193 , "UART1_RXD" ),194 , "UART1_TXD" ),195 , "UART1_RTSB" ),196 , "UART1_CTSB" ),197 , "I2C0_SDA" ),198 , "I2C0_SCL" ),199 , "I2C1_SDA" ),200 , "I2C1_SCL" ),201 , "UART2_RXD" ),202 , "UART2_TXD" ),203 , "UART2_RTSB" ),204 , "UART2_CTSB" ),/* GPP_E */ 205 , "SATAXPCIE_0" ),206 , "SATAXPCIE_1" ),207 , "SATAXPCIE_2" ),208 , "CPU_GP_0" ),209 , "SATA_DEVSLP_0" ),210 , "SATA_DEVSLP_1" ),211 , "SATA_DEVSLP_2" ),212 , "CPU_GP_1" ),213 , "SATA_LEDB" ),214 , "USB2_OCB_0" ),215 , "USB2_OCB_1" ),216 , "USB2_OCB_2" ),217 , "USB2_OCB_3" ),218 , "DDSP_HPD_0" ),219 , "DDSP_HPD_1" ),220 , "DDSP_HPD_2" ),221 , "DDSP_HPD_3" ),222 , "EDP_HPD" ),223 , "DDPB_CTRLCLK" ),224 , "DDPB_CTRLDATA" ),225 , "DDPC_CTRLCLK" ),226 , "DDPC_CTRLDATA" ),227 , "DDPD_CTRLCLK" ),228 , "DDPD_CTRLDATA" ),/* JTAG */ 229 , "JTAG_TDO" ),230 , "JTAGX" ),231 , "PRDYB" ),232 , "PREQB" ),233 , "CPU_TRSTB" ),234 , "JTAG_TDI" ),235 , "JTAG_TMS" ),236 , "JTAG_TCK" ),237 , "ITP_PMODE" ),/* HVCMOS */ 238 , "L_BKLTEN" ),239 , "L_BKLTCTL" ),240 , "L_VDDEN" ),241 , "SYS_PWROK" ),242 , "SYS_RESETB" ),243 , "MLK_RSTB" ),static const unsigned int cnllp_spi0_pins[] = { 40 , 41 , 42 , 43 , 7 };static const unsigned int cnllp_spi0_modes[] = { 1 , 1 , 1 , 1 , 2 };static const unsigned int cnllp_spi1_pins[] = { 44 , 45 , 46 , 47 , 11 };static const unsigned int cnllp_spi1_modes[] = { 1 , 1 , 1 , 1 , 2 };static const unsigned int cnllp_spi2_pins[] = { 77 , 78 , 79 , 80 , 83 };static const unsigned int cnllp_spi2_modes[] = { 3 , 3 , 3 , 3 , 2 };static const unsigned int cnllp_i2c0_pins[] = { 197 , 198 };static const unsigned int cnllp_i2c1_pins[] = { 199 , 200 };static const unsigned int cnllp_i2c2_pins[] = { 121 , 122 };static const unsigned int cnllp_i2c3_pins[] = { 123 , 124 };static const unsigned int cnllp_i2c4_pins[] = { 125 , 126 };static const unsigned int cnllp_i2c5_pins[] = { 127 , 128 };static const unsigned int cnllp_uart0_pins[] = { 189 , 190 , 191 , 192 };static const unsigned int cnllp_uart1_pins[] = { 193 , 194 , 195 , 196 };static const unsigned int cnllp_uart2_pins[] = { 201 , 202 , 203 , 204 };static const struct intel_pingroup cnllp_groups[] = {"spi0_grp" , cnllp_spi0_pins, cnllp_spi0_modes),"spi1_grp" , cnllp_spi1_pins, cnllp_spi1_modes),"spi2_grp" , cnllp_spi2_pins, cnllp_spi2_modes),"i2c0_grp" , cnllp_i2c0_pins, 1 ),"i2c1_grp" , cnllp_i2c1_pins, 1 ),"i2c2_grp" , cnllp_i2c2_pins, 1 ),"i2c3_grp" , cnllp_i2c3_pins, 1 ),"i2c4_grp" , cnllp_i2c4_pins, 1 ),"i2c5_grp" , cnllp_i2c5_pins, 1 ),"uart0_grp" , cnllp_uart0_pins, 1 ),"uart1_grp" , cnllp_uart1_pins, 1 ),"uart2_grp" , cnllp_uart2_pins, 1 ),static const char * const cnllp_spi0_groups[] = { "spi0_grp" };static const char * const cnllp_spi1_groups[] = { "spi1_grp" };static const char * const cnllp_spi2_groups[] = { "spi2_grp" };static const char * const cnllp_i2c0_groups[] = { "i2c0_grp" };static const char * const cnllp_i2c1_groups[] = { "i2c1_grp" };static const char * const cnllp_i2c2_groups[] = { "i2c2_grp" };static const char * const cnllp_i2c3_groups[] = { "i2c3_grp" };static const char * const cnllp_i2c4_groups[] = { "i2c4_grp" };static const char * const cnllp_i2c5_groups[] = { "i2c5_grp" };static const char * const cnllp_uart0_groups[] = { "uart0_grp" };static const char * const cnllp_uart1_groups[] = { "uart1_grp" };static const char * const cnllp_uart2_groups[] = { "uart2_grp" };static const struct intel_function cnllp_functions[] = {"spi0" , cnllp_spi0_groups),"spi1" , cnllp_spi1_groups),"spi2" , cnllp_spi2_groups),"i2c0" , cnllp_i2c0_groups),"i2c1" , cnllp_i2c1_groups),"i2c2" , cnllp_i2c2_groups),"i2c3" , cnllp_i2c3_groups),"i2c4" , cnllp_i2c4_groups),"i2c5" , cnllp_i2c5_groups),"uart0" , cnllp_uart0_groups),"uart1" , cnllp_uart1_groups),"uart2" , cnllp_uart2_groups),static const struct intel_padgroup cnllp_community0_gpps[] = {0 , 0 , 24 , 0 ), /* GPP_A */ 1 , 25 , 50 , 32 ), /* GPP_B */ 2 , 51 , 58 , 64 ), /* GPP_G */ 3 , 59 , 67 , INTEL_GPIO_BASE_NOMAP), /* SPI */ static const struct intel_padgroup cnllp_community1_gpps[] = {0 , 68 , 92 , 96 ), /* GPP_D */ 1 , 93 , 116 , 128 ), /* GPP_F */ 2 , 117 , 140 , 160 ), /* GPP_H */ 3 , 141 , 172 , 192 ), /* vGPIO */ 4 , 173 , 180 , 224 ), /* vGPIO */ static const struct intel_padgroup cnllp_community4_gpps[] = {0 , 181 , 204 , 256 ), /* GPP_C */ 1 , 205 , 228 , 288 ), /* GPP_E */ 2 , 229 , 237 , INTEL_GPIO_BASE_NOMAP), /* JTAG */ 3 , 238 , 243 , INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ static const struct intel_community cnllp_communities[] = {0 , 0 , 67 , cnllp_community0_gpps),1 , 68 , 180 , cnllp_community1_gpps),2 , 181 , 243 , cnllp_community4_gpps),static const struct intel_pinctrl_soc_data cnllp_soc_data = {static const struct acpi_device_id cnl_pinctrl_acpi_match[] = {"INT3450" , (kernel_ulong_t)&cnlh_soc_data },"INT34BB" , (kernel_ulong_t)&cnllp_soc_data },static struct platform_driver cnl_pinctrl_driver = {"cannonlake-pinctrl" ,"Mika Westerberg <mika.westerberg@linux.intel.com>" );"Intel Cannon Lake PCH pinctrl/GPIO driver" );"GPL v2" );"PINCTRL_INTEL" );
Messung V0.5 in Prozent C=95 H=98 G=96
¤ Dauer der Verarbeitung: 0.17 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
