// SPDX-License-Identifier: GPL-2.0 /* * Intel Broxton SoC pinctrl/GPIO driver * * Copyright (C) 2015, 2016 Intel Corporation * Author: Mika Westerberg <mika.westerberg@linux.intel.com> #include <linux/mod_devicetable.h>#include <linux/module.h>#include <linux/platform_device.h>#include <linux/pm.h>#include <linux/pinctrl/pinctrl.h>#include "pinctrl-intel.h" #define BXT_PAD_OWN 0 x020#define BXT_PADCFGLOCK 0 x060#define BXT_HOSTSW_OWN 0 x080#define BXT_GPI_IS 0 x100#define BXT_GPI_IE 0 x110#define BXT_COMMUNITY(b, s, e) \32 , 4 , BXT)/* BXT */ static const struct pinctrl_pin_desc bxt_north_pins[] = {0 , "GPIO_0" ),1 , "GPIO_1" ),2 , "GPIO_2" ),3 , "GPIO_3" ),4 , "GPIO_4" ),5 , "GPIO_5" ),6 , "GPIO_6" ),7 , "GPIO_7" ),8 , "GPIO_8" ),9 , "GPIO_9" ),10 , "GPIO_10" ),11 , "GPIO_11" ),12 , "GPIO_12" ),13 , "GPIO_13" ),14 , "GPIO_14" ),15 , "GPIO_15" ),16 , "GPIO_16" ),17 , "GPIO_17" ),18 , "GPIO_18" ),19 , "GPIO_19" ),20 , "GPIO_20" ),21 , "GPIO_21" ),22 , "GPIO_22" ),23 , "GPIO_23" ),24 , "GPIO_24" ),25 , "GPIO_25" ),26 , "GPIO_26" ),27 , "GPIO_27" ),28 , "GPIO_28" ),29 , "GPIO_29" ),30 , "GPIO_30" ),31 , "GPIO_31" ),32 , "GPIO_32" ),33 , "GPIO_33" ),34 , "PWM0" ),35 , "PWM1" ),36 , "PWM2" ),37 , "PWM3" ),38 , "LPSS_UART0_RXD" ),39 , "LPSS_UART0_TXD" ),40 , "LPSS_UART0_RTS_B" ),41 , "LPSS_UART0_CTS_B" ),42 , "LPSS_UART1_RXD" ),43 , "LPSS_UART1_TXD" ),44 , "LPSS_UART1_RTS_B" ),45 , "LPSS_UART1_CTS_B" ),46 , "LPSS_UART2_RXD" ),47 , "LPSS_UART2_TXD" ),48 , "LPSS_UART2_RTS_B" ),49 , "LPSS_UART2_CTS_B" ),50 , "ISH_UART0_RXD" ),51 , "ISH_UART0_TXT" ),52 , "ISH_UART0_RTS_B" ),53 , "ISH_UART0_CTS_B" ),54 , "ISH_UART1_RXD" ),55 , "ISH_UART1_TXT" ),56 , "ISH_UART1_RTS_B" ),57 , "ISH_UART1_CTS_B" ),58 , "ISH_UART2_RXD" ),59 , "ISH_UART2_TXD" ),60 , "ISH_UART2_RTS_B" ),61 , "ISH_UART2_CTS_B" ),62 , "GP_CAMERASB00" ),63 , "GP_CAMERASB01" ),64 , "GP_CAMERASB02" ),65 , "GP_CAMERASB03" ),66 , "GP_CAMERASB04" ),67 , "GP_CAMERASB05" ),68 , "GP_CAMERASB06" ),69 , "GP_CAMERASB07" ),70 , "GP_CAMERASB08" ),71 , "GP_CAMERASB09" ),72 , "GP_CAMERASB10" ),73 , "GP_CAMERASB11" ),74 , "TCK" ),75 , "TRST_B" ),76 , "TMS" ),77 , "TDI" ),78 , "CX_PMODE" ),79 , "CX_PREQ_B" ),80 , "JTAGX" ),81 , "CX_PRDY_B" ),82 , "TDO" ),static const unsigned int bxt_north_pwm0_pins[] = { 34 };static const unsigned int bxt_north_pwm1_pins[] = { 35 };static const unsigned int bxt_north_pwm2_pins[] = { 36 };static const unsigned int bxt_north_pwm3_pins[] = { 37 };static const unsigned int bxt_north_uart0_pins[] = { 38 , 39 , 40 , 41 };static const unsigned int bxt_north_uart1_pins[] = { 42 , 43 , 44 , 45 };static const unsigned int bxt_north_uart2_pins[] = { 46 , 47 , 48 , 49 };static const unsigned int bxt_north_uart0b_pins[] = { 50 , 51 , 52 , 53 };static const unsigned int bxt_north_uart1b_pins[] = { 54 , 55 , 56 , 57 };static const unsigned int bxt_north_uart2b_pins[] = { 58 , 59 , 60 , 61 };static const unsigned int bxt_north_uart3_pins[] = { 58 , 59 , 60 , 61 };static const struct intel_pingroup bxt_north_groups[] = {"pwm0_grp" , bxt_north_pwm0_pins, 1 ),"pwm1_grp" , bxt_north_pwm1_pins, 1 ),"pwm2_grp" , bxt_north_pwm2_pins, 1 ),"pwm3_grp" , bxt_north_pwm3_pins, 1 ),"uart0_grp" , bxt_north_uart0_pins, 1 ),"uart1_grp" , bxt_north_uart1_pins, 1 ),"uart2_grp" , bxt_north_uart2_pins, 1 ),"uart0b_grp" , bxt_north_uart0b_pins, 2 ),"uart1b_grp" , bxt_north_uart1b_pins, 2 ),"uart2b_grp" , bxt_north_uart2b_pins, 2 ),"uart3_grp" , bxt_north_uart3_pins, 3 ),static const char * const bxt_north_pwm0_groups[] = { "pwm0_grp" };static const char * const bxt_north_pwm1_groups[] = { "pwm1_grp" };static const char * const bxt_north_pwm2_groups[] = { "pwm2_grp" };static const char * const bxt_north_pwm3_groups[] = { "pwm3_grp" };static const char * const bxt_north_uart0_groups[] = {"uart0_grp" , "uart0b_grp" ,static const char * const bxt_north_uart1_groups[] = {"uart1_grp" , "uart1b_grp" ,static const char * const bxt_north_uart2_groups[] = {"uart2_grp" , "uart2b_grp" ,static const char * const bxt_north_uart3_groups[] = { "uart3_grp" };static const struct intel_function bxt_north_functions[] = {"pwm0" , bxt_north_pwm0_groups),"pwm1" , bxt_north_pwm1_groups),"pwm2" , bxt_north_pwm2_groups),"pwm3" , bxt_north_pwm3_groups),"uart0" , bxt_north_uart0_groups),"uart1" , bxt_north_uart1_groups),"uart2" , bxt_north_uart2_groups),"uart3" , bxt_north_uart3_groups),static const struct intel_community bxt_north_communities[] = {0 , 0 , 82 ),static const struct intel_pinctrl_soc_data bxt_north_soc_data = {"1" ,static const struct pinctrl_pin_desc bxt_northwest_pins[] = {0 , "PMC_SPI_FS0" ),1 , "PMC_SPI_FS1" ),2 , "PMC_SPI_FS2" ),3 , "PMC_SPI_RXD" ),4 , "PMC_SPI_TXD" ),5 , "PMC_SPI_CLK" ),6 , "PMC_UART_RXD" ),7 , "PMC_UART_TXD" ),8 , "PMIC_PWRGOOD" ),9 , "PMIC_RESET_B" ),10 , "RTC_CLK" ),11 , "PMIC_SDWN_B" ),12 , "PMIC_BCUDISW2" ),13 , "PMIC_BCUDISCRIT" ),14 , "PMIC_THERMTRIP_B" ),15 , "PMIC_STDBY" ),16 , "SVID0_ALERT_B" ),17 , "SVID0_DATA" ),18 , "SVID0_CLK" ),19 , "PMIC_I2C_SCL" ),20 , "PMIC_I2C_SDA" ),21 , "AVS_I2S1_MCLK" ),22 , "AVS_I2S1_BCLK" ),23 , "AVS_I2S1_WS_SYNC" ),24 , "AVS_I2S1_SDI" ),25 , "AVS_I2S1_SDO" ),26 , "AVS_M_CLK_A1" ),27 , "AVS_M_CLK_B1" ),28 , "AVS_M_DATA_1" ),29 , "AVS_M_CLK_AB2" ),30 , "AVS_M_DATA_2" ),31 , "AVS_I2S2_MCLK" ),32 , "AVS_I2S2_BCLK" ),33 , "AVS_I2S2_WS_SYNC" ),34 , "AVS_I2S2_SDI" ),35 , "AVS_I2S2_SDOK" ),36 , "AVS_I2S3_BCLK" ),37 , "AVS_I2S3_WS_SYNC" ),38 , "AVS_I2S3_SDI" ),39 , "AVS_I2S3_SDO" ),40 , "AVS_I2S4_BCLK" ),41 , "AVS_I2S4_WS_SYNC" ),42 , "AVS_I2S4_SDI" ),43 , "AVS_I2S4_SDO" ),44 , "PROCHOT_B" ),45 , "FST_SPI_CS0_B" ),46 , "FST_SPI_CS1_B" ),47 , "FST_SPI_MOSI_IO0" ),48 , "FST_SPI_MISO_IO1" ),49 , "FST_SPI_IO2" ),50 , "FST_SPI_IO3" ),51 , "FST_SPI_CLK" ),52 , "FST_SPI_CLK_FB" ),53 , "GP_SSP_0_CLK" ),54 , "GP_SSP_0_FS0" ),55 , "GP_SSP_0_FS1" ),56 , "GP_SSP_0_FS2" ),57 , "GP_SSP_0_RXD" ),58 , "GP_SSP_0_TXD" ),59 , "GP_SSP_1_CLK" ),60 , "GP_SSP_1_FS0" ),61 , "GP_SSP_1_FS1" ),62 , "GP_SSP_1_FS2" ),63 , "GP_SSP_1_FS3" ),64 , "GP_SSP_1_RXD" ),65 , "GP_SSP_1_TXD" ),66 , "GP_SSP_2_CLK" ),67 , "GP_SSP_2_FS0" ),68 , "GP_SSP_2_FS1" ),69 , "GP_SSP_2_FS2" ),70 , "GP_SSP_2_RXD" ),71 , "GP_SSP_2_TXD" ),static const unsigned int bxt_northwest_ssp0_pins[] = { 53 , 54 , 55 , 56 , 57 , 58 };static const unsigned int bxt_northwest_ssp1_pins[] = {59 , 60 , 61 , 62 , 63 , 64 , 65 static const unsigned int bxt_northwest_ssp2_pins[] = { 66 , 67 , 68 , 69 , 70 , 71 };static const unsigned int bxt_northwest_uart3_pins[] = { 67 , 68 , 69 , 70 };static const struct intel_pingroup bxt_northwest_groups[] = {"ssp0_grp" , bxt_northwest_ssp0_pins, 1 ),"ssp1_grp" , bxt_northwest_ssp1_pins, 1 ),"ssp2_grp" , bxt_northwest_ssp2_pins, 1 ),"uart3_grp" , bxt_northwest_uart3_pins, 2 ),static const char * const bxt_northwest_ssp0_groups[] = { "ssp0_grp" };static const char * const bxt_northwest_ssp1_groups[] = { "ssp1_grp" };static const char * const bxt_northwest_ssp2_groups[] = { "ssp2_grp" };static const char * const bxt_northwest_uart3_groups[] = { "uart3_grp" };static const struct intel_function bxt_northwest_functions[] = {"ssp0" , bxt_northwest_ssp0_groups),"ssp1" , bxt_northwest_ssp1_groups),"ssp2" , bxt_northwest_ssp2_groups),"uart3" , bxt_northwest_uart3_groups),static const struct intel_community bxt_northwest_communities[] = {0 , 0 , 71 ),static const struct intel_pinctrl_soc_data bxt_northwest_soc_data = {"2" ,static const struct pinctrl_pin_desc bxt_west_pins[] = {0 , "LPSS_I2C0_SDA" ),1 , "LPSS_I2C0_SCL" ),2 , "LPSS_I2C1_SDA" ),3 , "LPSS_I2C1_SCL" ),4 , "LPSS_I2C2_SDA" ),5 , "LPSS_I2C2_SCL" ),6 , "LPSS_I2C3_SDA" ),7 , "LPSS_I2C3_SCL" ),8 , "LPSS_I2C4_SDA" ),9 , "LPSS_I2C4_SCL" ),10 , "LPSS_I2C5_SDA" ),11 , "LPSS_I2C5_SCL" ),12 , "LPSS_I2C6_SDA" ),13 , "LPSS_I2C6_SCL" ),14 , "LPSS_I2C7_SDA" ),15 , "LPSS_I2C7_SCL" ),16 , "ISH_I2C0_SDA" ),17 , "ISH_I2C0_SCL" ),18 , "ISH_I2C1_SDA" ),19 , "ISH_I2C1_SCL" ),20 , "ISH_I2C2_SDA" ),21 , "ISH_I2C2_SCL" ),22 , "ISH_GPIO_0" ),23 , "ISH_GPIO_1" ),24 , "ISH_GPIO_2" ),25 , "ISH_GPIO_3" ),26 , "ISH_GPIO_4" ),27 , "ISH_GPIO_5" ),28 , "ISH_GPIO_6" ),29 , "ISH_GPIO_7" ),30 , "ISH_GPIO_8" ),31 , "ISH_GPIO_9" ),32 , "MODEM_CLKREQ" ),33 , "DGCLKDBG_PMC_0" ),34 , "DGCLKDBG_PMC_1" ),35 , "DGCLKDBG_PMC_2" ),36 , "DGCLKDBG_ICLK_0" ),37 , "DGCLKDBG_ICLK_1" ),38 , "OSC_CLK_OUT_0" ),39 , "OSC_CLK_OUT_1" ),40 , "OSC_CLK_OUT_2" ),41 , "OSC_CLK_OUT_3" ),static const unsigned int bxt_west_i2c0_pins[] = { 0 , 1 };static const unsigned int bxt_west_i2c1_pins[] = { 2 , 3 };static const unsigned int bxt_west_i2c2_pins[] = { 4 , 5 };static const unsigned int bxt_west_i2c3_pins[] = { 6 , 7 };static const unsigned int bxt_west_i2c4_pins[] = { 8 , 9 };static const unsigned int bxt_west_i2c5_pins[] = { 10 , 11 };static const unsigned int bxt_west_i2c6_pins[] = { 12 , 13 };static const unsigned int bxt_west_i2c7_pins[] = { 14 , 15 };static const unsigned int bxt_west_i2c5b_pins[] = { 16 , 17 };static const unsigned int bxt_west_i2c6b_pins[] = { 18 , 19 };static const unsigned int bxt_west_i2c7b_pins[] = { 20 , 21 };static const struct intel_pingroup bxt_west_groups[] = {"i2c0_grp" , bxt_west_i2c0_pins, 1 ),"i2c1_grp" , bxt_west_i2c1_pins, 1 ),"i2c2_grp" , bxt_west_i2c2_pins, 1 ),"i2c3_grp" , bxt_west_i2c3_pins, 1 ),"i2c4_grp" , bxt_west_i2c4_pins, 1 ),"i2c5_grp" , bxt_west_i2c5_pins, 1 ),"i2c6_grp" , bxt_west_i2c6_pins, 1 ),"i2c7_grp" , bxt_west_i2c7_pins, 1 ),"i2c5b_grp" , bxt_west_i2c5b_pins, 2 ),"i2c6b_grp" , bxt_west_i2c6b_pins, 2 ),"i2c7b_grp" , bxt_west_i2c7b_pins, 2 ),static const char * const bxt_west_i2c0_groups[] = { "i2c0_grp" };static const char * const bxt_west_i2c1_groups[] = { "i2c1_grp" };static const char * const bxt_west_i2c2_groups[] = { "i2c2_grp" };static const char * const bxt_west_i2c3_groups[] = { "i2c3_grp" };static const char * const bxt_west_i2c4_groups[] = { "i2c4_grp" };static const char * const bxt_west_i2c5_groups[] = { "i2c5_grp" , "i2c5b_grp" };static const char * const bxt_west_i2c6_groups[] = { "i2c6_grp" , "i2c6b_grp" };static const char * const bxt_west_i2c7_groups[] = { "i2c7_grp" , "i2c7b_grp" };static const struct intel_function bxt_west_functions[] = {"i2c0" , bxt_west_i2c0_groups),"i2c1" , bxt_west_i2c1_groups),"i2c2" , bxt_west_i2c2_groups),"i2c3" , bxt_west_i2c3_groups),"i2c4" , bxt_west_i2c4_groups),"i2c5" , bxt_west_i2c5_groups),"i2c6" , bxt_west_i2c6_groups),"i2c7" , bxt_west_i2c7_groups),static const struct intel_community bxt_west_communities[] = {0 , 0 , 41 ),static const struct intel_pinctrl_soc_data bxt_west_soc_data = {"3" ,static const struct pinctrl_pin_desc bxt_southwest_pins[] = {0 , "EMMC0_CLK" ),1 , "EMMC0_D0" ),2 , "EMMC0_D1" ),3 , "EMMC0_D2" ),4 , "EMMC0_D3" ),5 , "EMMC0_D4" ),6 , "EMMC0_D5" ),7 , "EMMC0_D6" ),8 , "EMMC0_D7" ),9 , "EMMC0_CMD" ),10 , "SDIO_CLK" ),11 , "SDIO_D0" ),12 , "SDIO_D1" ),13 , "SDIO_D2" ),14 , "SDIO_D3" ),15 , "SDIO_CMD" ),16 , "SDCARD_CLK" ),17 , "SDCARD_D0" ),18 , "SDCARD_D1" ),19 , "SDCARD_D2" ),20 , "SDCARD_D3" ),21 , "SDCARD_CD_B" ),22 , "SDCARD_CMD" ),23 , "SDCARD_LVL_CLK_FB" ),24 , "SDCARD_LVL_CMD_DIR" ),25 , "SDCARD_LVL_DAT_DIR" ),26 , "EMMC0_STROBE" ),27 , "SDIO_PWR_DOWN_B" ),28 , "SDCARD_PWR_DOWN_B" ),29 , "SDCARD_LVL_SEL" ),30 , "SDCARD_LVL_WP" ),static const unsigned int bxt_southwest_emmc0_pins[] = {0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 26 ,static const unsigned int bxt_southwest_sdio_pins[] = {10 , 11 , 12 , 13 , 14 , 15 , 27 ,static const unsigned int bxt_southwest_sdcard_pins[] = {16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 28 , 29 , 30 ,static const struct intel_pingroup bxt_southwest_groups[] = {"emmc0_grp" , bxt_southwest_emmc0_pins, 1 ),"sdio_grp" , bxt_southwest_sdio_pins, 1 ),"sdcard_grp" , bxt_southwest_sdcard_pins, 1 ),static const char * const bxt_southwest_emmc0_groups[] = { "emmc0_grp" };static const char * const bxt_southwest_sdio_groups[] = { "sdio_grp" };static const char * const bxt_southwest_sdcard_groups[] = { "sdcard_grp" };static const struct intel_function bxt_southwest_functions[] = {"emmc0" , bxt_southwest_emmc0_groups),"sdio" , bxt_southwest_sdio_groups),"sdcard" , bxt_southwest_sdcard_groups),static const struct intel_community bxt_southwest_communities[] = {0 , 0 , 30 ),static const struct intel_pinctrl_soc_data bxt_southwest_soc_data = {"4" ,static const struct pinctrl_pin_desc bxt_south_pins[] = {0 , "HV_DDI0_DDC_SDA" ),1 , "HV_DDI0_DDC_SCL" ),2 , "HV_DDI1_DDC_SDA" ),3 , "HV_DDI1_DDC_SCL" ),4 , "DBI_SDA" ),5 , "DBI_SCL" ),6 , "PANEL0_VDDEN" ),7 , "PANEL0_BKLTEN" ),8 , "PANEL0_BKLTCTL" ),9 , "PANEL1_VDDEN" ),10 , "PANEL1_BKLTEN" ),11 , "PANEL1_BKLTCTL" ),12 , "DBI_CSX" ),13 , "DBI_RESX" ),14 , "GP_INTD_DSI_TE1" ),15 , "GP_INTD_DSI_TE2" ),16 , "USB_OC0_B" ),17 , "USB_OC1_B" ),18 , "MEX_WAKE0_B" ),19 , "MEX_WAKE1_B" ),static const struct intel_community bxt_south_communities[] = {0 , 0 , 19 ),static const struct intel_pinctrl_soc_data bxt_south_soc_data = {"5" ,static const struct intel_pinctrl_soc_data *bxt_pinctrl_soc_data[] = {/* APL */ static const struct pinctrl_pin_desc apl_north_pins[] = {0 , "GPIO_0" ),1 , "GPIO_1" ),2 , "GPIO_2" ),3 , "GPIO_3" ),4 , "GPIO_4" ),5 , "GPIO_5" ),6 , "GPIO_6" ),7 , "GPIO_7" ),8 , "GPIO_8" ),9 , "GPIO_9" ),10 , "GPIO_10" ),11 , "GPIO_11" ),12 , "GPIO_12" ),13 , "GPIO_13" ),14 , "GPIO_14" ),15 , "GPIO_15" ),16 , "GPIO_16" ),17 , "GPIO_17" ),18 , "GPIO_18" ),19 , "GPIO_19" ),20 , "GPIO_20" ),21 , "GPIO_21" ),22 , "GPIO_22" ),23 , "GPIO_23" ),24 , "GPIO_24" ),25 , "GPIO_25" ),26 , "GPIO_26" ),27 , "GPIO_27" ),28 , "GPIO_28" ),29 , "GPIO_29" ),30 , "GPIO_30" ),31 , "GPIO_31" ),32 , "GPIO_32" ),33 , "GPIO_33" ),34 , "PWM0" ),35 , "PWM1" ),36 , "PWM2" ),37 , "PWM3" ),38 , "LPSS_UART0_RXD" ),39 , "LPSS_UART0_TXD" ),40 , "LPSS_UART0_RTS_B" ),41 , "LPSS_UART0_CTS_B" ),42 , "LPSS_UART1_RXD" ),43 , "LPSS_UART1_TXD" ),44 , "LPSS_UART1_RTS_B" ),45 , "LPSS_UART1_CTS_B" ),46 , "LPSS_UART2_RXD" ),47 , "LPSS_UART2_TXD" ),48 , "LPSS_UART2_RTS_B" ),49 , "LPSS_UART2_CTS_B" ),50 , "GP_CAMERASB00" ),51 , "GP_CAMERASB01" ),52 , "GP_CAMERASB02" ),53 , "GP_CAMERASB03" ),54 , "GP_CAMERASB04" ),55 , "GP_CAMERASB05" ),56 , "GP_CAMERASB06" ),57 , "GP_CAMERASB07" ),58 , "GP_CAMERASB08" ),59 , "GP_CAMERASB09" ),60 , "GP_CAMERASB10" ),61 , "GP_CAMERASB11" ),62 , "TCK" ),63 , "TRST_B" ),64 , "TMS" ),65 , "TDI" ),66 , "CX_PMODE" ),67 , "CX_PREQ_B" ),68 , "JTAGX" ),69 , "CX_PRDY_B" ),70 , "TDO" ),71 , "CNV_BRI_DT" ),72 , "CNV_BRI_RSP" ),73 , "CNV_RGI_DT" ),74 , "CNV_RGI_RSP" ),75 , "SVID0_ALERT_B" ),76 , "SVID0_DATA" ),77 , "SVID0_CLK" ),static const unsigned int apl_north_pwm0_pins[] = { 34 };static const unsigned int apl_north_pwm1_pins[] = { 35 };static const unsigned int apl_north_pwm2_pins[] = { 36 };static const unsigned int apl_north_pwm3_pins[] = { 37 };static const unsigned int apl_north_uart0_pins[] = { 38 , 39 , 40 , 41 };static const unsigned int apl_north_uart1_pins[] = { 42 , 43 , 44 , 45 };static const unsigned int apl_north_uart2_pins[] = { 46 , 47 , 48 , 49 };static const struct intel_pingroup apl_north_groups[] = {"pwm0_grp" , apl_north_pwm0_pins, 1 ),"pwm1_grp" , apl_north_pwm1_pins, 1 ),"pwm2_grp" , apl_north_pwm2_pins, 1 ),"pwm3_grp" , apl_north_pwm3_pins, 1 ),"uart0_grp" , apl_north_uart0_pins, 1 ),"uart1_grp" , apl_north_uart1_pins, 1 ),"uart2_grp" , apl_north_uart2_pins, 1 ),static const char * const apl_north_pwm0_groups[] = { "pwm0_grp" };static const char * const apl_north_pwm1_groups[] = { "pwm1_grp" };static const char * const apl_north_pwm2_groups[] = { "pwm2_grp" };static const char * const apl_north_pwm3_groups[] = { "pwm3_grp" };static const char * const apl_north_uart0_groups[] = { "uart0_grp" };static const char * const apl_north_uart1_groups[] = { "uart1_grp" };static const char * const apl_north_uart2_groups[] = { "uart2_grp" };static const struct intel_function apl_north_functions[] = {"pwm0" , apl_north_pwm0_groups),"pwm1" , apl_north_pwm1_groups),"pwm2" , apl_north_pwm2_groups),"pwm3" , apl_north_pwm3_groups),"uart0" , apl_north_uart0_groups),"uart1" , apl_north_uart1_groups),"uart2" , apl_north_uart2_groups),static const struct intel_community apl_north_communities[] = {0 , 0 , 77 ),static const struct intel_pinctrl_soc_data apl_north_soc_data = {"1" ,static const struct pinctrl_pin_desc apl_northwest_pins[] = {0 , "HV_DDI0_DDC_SDA" ),1 , "HV_DDI0_DDC_SCL" ),2 , "HV_DDI1_DDC_SDA" ),3 , "HV_DDI1_DDC_SCL" ),4 , "DBI_SDA" ),5 , "DBI_SCL" ),6 , "PANEL0_VDDEN" ),7 , "PANEL0_BKLTEN" ),8 , "PANEL0_BKLTCTL" ),9 , "PANEL1_VDDEN" ),10 , "PANEL1_BKLTEN" ),11 , "PANEL1_BKLTCTL" ),12 , "DBI_CSX" ),13 , "DBI_RESX" ),14 , "GP_INTD_DSI_TE1" ),15 , "GP_INTD_DSI_TE2" ),16 , "USB_OC0_B" ),17 , "USB_OC1_B" ),18 , "PMC_SPI_FS0" ),19 , "PMC_SPI_FS1" ),20 , "PMC_SPI_FS2" ),21 , "PMC_SPI_RXD" ),22 , "PMC_SPI_TXD" ),23 , "PMC_SPI_CLK" ),24 , "PMIC_PWRGOOD" ),25 , "PMIC_RESET_B" ),26 , "PMIC_SDWN_B" ),27 , "PMIC_BCUDISW2" ),28 , "PMIC_BCUDISCRIT" ),29 , "PMIC_THERMTRIP_B" ),30 , "PMIC_STDBY" ),31 , "PROCHOT_B" ),32 , "PMIC_I2C_SCL" ),33 , "PMIC_I2C_SDA" ),34 , "AVS_I2S1_MCLK" ),35 , "AVS_I2S1_BCLK" ),36 , "AVS_I2S1_WS_SYNC" ),37 , "AVS_I2S1_SDI" ),38 , "AVS_I2S1_SDO" ),39 , "AVS_M_CLK_A1" ),40 , "AVS_M_CLK_B1" ),41 , "AVS_M_DATA_1" ),42 , "AVS_M_CLK_AB2" ),43 , "AVS_M_DATA_2" ),44 , "AVS_I2S2_MCLK" ),45 , "AVS_I2S2_BCLK" ),46 , "AVS_I2S2_WS_SYNC" ),47 , "AVS_I2S2_SDI" ),48 , "AVS_I2S2_SDO" ),49 , "AVS_I2S3_BCLK" ),50 , "AVS_I2S3_WS_SYNC" ),51 , "AVS_I2S3_SDI" ),52 , "AVS_I2S3_SDO" ),53 , "FST_SPI_CS0_B" ),54 , "FST_SPI_CS1_B" ),55 , "FST_SPI_MOSI_IO0" ),56 , "FST_SPI_MISO_IO1" ),57 , "FST_SPI_IO2" ),58 , "FST_SPI_IO3" ),59 , "FST_SPI_CLK" ),60 , "FST_SPI_CLK_FB" ),61 , "GP_SSP_0_CLK" ),62 , "GP_SSP_0_FS0" ),63 , "GP_SSP_0_FS1" ),64 , "GP_SSP_0_RXD" ),65 , "GP_SSP_0_TXD" ),66 , "GP_SSP_1_CLK" ),67 , "GP_SSP_1_FS0" ),68 , "GP_SSP_1_FS1" ),69 , "GP_SSP_1_RXD" ),70 , "GP_SSP_1_TXD" ),71 , "GP_SSP_2_CLK" ),72 , "GP_SSP_2_FS0" ),73 , "GP_SSP_2_FS1" ),74 , "GP_SSP_2_FS2" ),75 , "GP_SSP_2_RXD" ),76 , "GP_SSP_2_TXD" ),static const unsigned int apl_northwest_ssp0_pins[] = { 61 , 62 , 63 , 64 , 65 };static const unsigned int apl_northwest_ssp1_pins[] = { 66 , 67 , 68 , 69 , 70 };static const unsigned int apl_northwest_ssp2_pins[] = { 71 , 72 , 73 , 74 , 75 , 76 };static const unsigned int apl_northwest_uart3_pins[] = { 67 , 68 , 69 , 70 };static const struct intel_pingroup apl_northwest_groups[] = {"ssp0_grp" , apl_northwest_ssp0_pins, 1 ),"ssp1_grp" , apl_northwest_ssp1_pins, 1 ),"ssp2_grp" , apl_northwest_ssp2_pins, 1 ),"uart3_grp" , apl_northwest_uart3_pins, 2 ),static const char * const apl_northwest_ssp0_groups[] = { "ssp0_grp" };static const char * const apl_northwest_ssp1_groups[] = { "ssp1_grp" };static const char * const apl_northwest_ssp2_groups[] = { "ssp2_grp" };static const char * const apl_northwest_uart3_groups[] = { "uart3_grp" };static const struct intel_function apl_northwest_functions[] = {"ssp0" , apl_northwest_ssp0_groups),"ssp1" , apl_northwest_ssp1_groups),"ssp2" , apl_northwest_ssp2_groups),"uart3" , apl_northwest_uart3_groups),static const struct intel_community apl_northwest_communities[] = {0 , 0 , 76 ),static const struct intel_pinctrl_soc_data apl_northwest_soc_data = {"2" ,static const struct pinctrl_pin_desc apl_west_pins[] = {0 , "LPSS_I2C0_SDA" ),1 , "LPSS_I2C0_SCL" ),2 , "LPSS_I2C1_SDA" ),3 , "LPSS_I2C1_SCL" ),4 , "LPSS_I2C2_SDA" ),5 , "LPSS_I2C2_SCL" ),6 , "LPSS_I2C3_SDA" ),7 , "LPSS_I2C3_SCL" ),8 , "LPSS_I2C4_SDA" ),9 , "LPSS_I2C4_SCL" ),10 , "LPSS_I2C5_SDA" ),11 , "LPSS_I2C5_SCL" ),12 , "LPSS_I2C6_SDA" ),13 , "LPSS_I2C6_SCL" ),14 , "LPSS_I2C7_SDA" ),15 , "LPSS_I2C7_SCL" ),16 , "ISH_GPIO_0" ),17 , "ISH_GPIO_1" ),18 , "ISH_GPIO_2" ),19 , "ISH_GPIO_3" ),20 , "ISH_GPIO_4" ),21 , "ISH_GPIO_5" ),22 , "ISH_GPIO_6" ),23 , "ISH_GPIO_7" ),24 , "ISH_GPIO_8" ),25 , "ISH_GPIO_9" ),26 , "PCIE_CLKREQ0_B" ),27 , "PCIE_CLKREQ1_B" ),28 , "PCIE_CLKREQ2_B" ),29 , "PCIE_CLKREQ3_B" ),30 , "OSC_CLK_OUT_0" ),31 , "OSC_CLK_OUT_1" ),32 , "OSC_CLK_OUT_2" ),33 , "OSC_CLK_OUT_3" ),34 , "OSC_CLK_OUT_4" ),35 , "PMU_AC_PRESENT" ),36 , "PMU_BATLOW_B" ),37 , "PMU_PLTRST_B" ),38 , "PMU_PWRBTN_B" ),39 , "PMU_RESETBUTTON_B" ),40 , "PMU_SLP_S0_B" ),41 , "PMU_SLP_S3_B" ),42 , "PMU_SLP_S4_B" ),43 , "PMU_SUSCLK" ),44 , "PMU_WAKE_B" ),45 , "SUS_STAT_B" ),46 , "SUSPWRDNACK" ),static const unsigned int apl_west_i2c0_pins[] = { 0 , 1 };static const unsigned int apl_west_i2c1_pins[] = { 2 , 3 };static const unsigned int apl_west_i2c2_pins[] = { 4 , 5 };static const unsigned int apl_west_i2c3_pins[] = { 6 , 7 };static const unsigned int apl_west_i2c4_pins[] = { 8 , 9 };static const unsigned int apl_west_i2c5_pins[] = { 10 , 11 };static const unsigned int apl_west_i2c6_pins[] = { 12 , 13 };static const unsigned int apl_west_i2c7_pins[] = { 14 , 15 };static const unsigned int apl_west_uart2_pins[] = { 20 , 21 , 22 , 34 };static const struct intel_pingroup apl_west_groups[] = {"i2c0_grp" , apl_west_i2c0_pins, 1 ),"i2c1_grp" , apl_west_i2c1_pins, 1 ),"i2c2_grp" , apl_west_i2c2_pins, 1 ),"i2c3_grp" , apl_west_i2c3_pins, 1 ),"i2c4_grp" , apl_west_i2c4_pins, 1 ),"i2c5_grp" , apl_west_i2c5_pins, 1 ),"i2c6_grp" , apl_west_i2c6_pins, 1 ),"i2c7_grp" , apl_west_i2c7_pins, 1 ),"uart2_grp" , apl_west_uart2_pins, 3 ),static const char * const apl_west_i2c0_groups[] = { "i2c0_grp" };static const char * const apl_west_i2c1_groups[] = { "i2c1_grp" };static const char * const apl_west_i2c2_groups[] = { "i2c2_grp" };static const char * const apl_west_i2c3_groups[] = { "i2c3_grp" };static const char * const apl_west_i2c4_groups[] = { "i2c4_grp" };static const char * const apl_west_i2c5_groups[] = { "i2c5_grp" };static const char * const apl_west_i2c6_groups[] = { "i2c6_grp" };static const char * const apl_west_i2c7_groups[] = { "i2c7_grp" };static const char * const apl_west_uart2_groups[] = { "uart2_grp" };static const struct intel_function apl_west_functions[] = {"i2c0" , apl_west_i2c0_groups),"i2c1" , apl_west_i2c1_groups),"i2c2" , apl_west_i2c2_groups),"i2c3" , apl_west_i2c3_groups),"i2c4" , apl_west_i2c4_groups),"i2c5" , apl_west_i2c5_groups),"i2c6" , apl_west_i2c6_groups),"i2c7" , apl_west_i2c7_groups),"uart2" , apl_west_uart2_groups),static const struct intel_community apl_west_communities[] = {0 , 0 , 46 ),static const struct intel_pinctrl_soc_data apl_west_soc_data = {"3" ,static const struct pinctrl_pin_desc apl_southwest_pins[] = {0 , "PCIE_WAKE0_B" ),1 , "PCIE_WAKE1_B" ),2 , "PCIE_WAKE2_B" ),3 , "PCIE_WAKE3_B" ),4 , "EMMC0_CLK" ),5 , "EMMC0_D0" ),6 , "EMMC0_D1" ),7 , "EMMC0_D2" ),8 , "EMMC0_D3" ),9 , "EMMC0_D4" ),10 , "EMMC0_D5" ),11 , "EMMC0_D6" ),12 , "EMMC0_D7" ),13 , "EMMC0_CMD" ),14 , "SDIO_CLK" ),15 , "SDIO_D0" ),16 , "SDIO_D1" ),17 , "SDIO_D2" ),18 , "SDIO_D3" ),19 , "SDIO_CMD" ),20 , "SDCARD_CLK" ),21 , "SDCARD_CLK_FB" ),22 , "SDCARD_D0" ),23 , "SDCARD_D1" ),24 , "SDCARD_D2" ),25 , "SDCARD_D3" ),26 , "SDCARD_CD_B" ),27 , "SDCARD_CMD" ),28 , "SDCARD_LVL_WP" ),29 , "EMMC0_STROBE" ),30 , "SDIO_PWR_DOWN_B" ),31 , "SMB_ALERTB" ),32 , "SMB_CLK" ),33 , "SMB_DATA" ),34 , "LPC_ILB_SERIRQ" ),35 , "LPC_CLKOUT0" ),36 , "LPC_CLKOUT1" ),37 , "LPC_AD0" ),38 , "LPC_AD1" ),39 , "LPC_AD2" ),40 , "LPC_AD3" ),41 , "LPC_CLKRUNB" ),42 , "LPC_FRAMEB" ),static const unsigned int apl_southwest_emmc0_pins[] = {4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 29 ,static const unsigned int apl_southwest_sdio_pins[] = {14 , 15 , 16 , 17 , 18 , 19 , 30 ,static const unsigned int apl_southwest_sdcard_pins[] = {20 , 21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 ,static const unsigned int apl_southwest_i2c7_pins[] = { 32 , 33 };static const struct intel_pingroup apl_southwest_groups[] = {"emmc0_grp" , apl_southwest_emmc0_pins, 1 ),"sdio_grp" , apl_southwest_sdio_pins, 1 ),"sdcard_grp" , apl_southwest_sdcard_pins, 1 ),"i2c7_grp" , apl_southwest_i2c7_pins, 2 ),static const char * const apl_southwest_emmc0_groups[] = { "emmc0_grp" };static const char * const apl_southwest_sdio_groups[] = { "sdio_grp" };static const char * const apl_southwest_sdcard_groups[] = { "sdcard_grp" };static const char * const apl_southwest_i2c7_groups[] = { "i2c7_grp" };static const struct intel_function apl_southwest_functions[] = {"emmc0" , apl_southwest_emmc0_groups),"sdio" , apl_southwest_sdio_groups),"sdcard" , apl_southwest_sdcard_groups),"i2c7" , apl_southwest_i2c7_groups),static const struct intel_community apl_southwest_communities[] = {0 , 0 , 42 ),static const struct intel_pinctrl_soc_data apl_southwest_soc_data = {"4" ,static const struct intel_pinctrl_soc_data *apl_pinctrl_soc_data[] = {static const struct acpi_device_id bxt_pinctrl_acpi_match[] = {"INT3452" , (kernel_ulong_t)apl_pinctrl_soc_data },"INT34D1" , (kernel_ulong_t)bxt_pinctrl_soc_data },static const struct platform_device_id bxt_pinctrl_platform_ids[] = {"apollolake-pinctrl" , (kernel_ulong_t)apl_pinctrl_soc_data },"broxton-pinctrl" , (kernel_ulong_t)bxt_pinctrl_soc_data },static struct platform_driver bxt_pinctrl_driver = {"broxton-pinctrl" ,static int __init bxt_pinctrl_init(void )return platform_driver_register(&bxt_pinctrl_driver);static void __exit bxt_pinctrl_exit(void )"Mika Westerberg <mika.westerberg@linux.intel.com>" );"Intel Broxton SoC pinctrl/GPIO driver" );"GPL v2" );"PINCTRL_INTEL" );
Messung V0.5 in Prozent C=96 H=98 G=96
¤ Dauer der Verarbeitung: 0.14 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
