// SPDX-License-Identifier: GPL-2.0-only /* * UFS PHY driver data for Google Tensor gs101 SoC * * Copyright (C) 2024 Linaro Ltd * Author: Peter Griffin <peter.griffin@linaro.org> #include "phy-samsung-ufs.h" #define TENSOR_GS101_PHY_CTRL 0 x3ec8#define TENSOR_GS101_PHY_CTRL_MASK 0 x1#define TENSOR_GS101_PHY_CTRL_EN BIT(0 )#define PHY_GS101_LANE_OFFSET 0 x200#define TRSV_REG338 0 x338#define LN0_MON_RX_CAL_DONE BIT(3 )#define TRSV_REG339 0 x339#define LN0_MON_RX_CDR_FLD_CK_MODE_DONE BIT(3 )#define TRSV_REG222 0 x222#define LN0_OVRD_RX_CDR_EN BIT(4 )#define LN0_RX_CDR_EN BIT(3 )#define PHY_PMA_TRSV_ADDR(reg, lane) (PHY_APB_ADDR((reg) + \#define PHY_TRSV_REG_CFG_GS101(o, v, d) \/* Calibration for phy initialization */ static const struct samsung_ufs_phy_cfg tensor_gs101_pre_init_cfg[] = {0 x43, 0 x10, PWR_MODE_ANY),0 x3C, 0 x14, PWR_MODE_ANY),0 x46, 0 x48, PWR_MODE_ANY),0 x200, 0 x00, PWR_MODE_ANY),0 x201, 0 x06, PWR_MODE_ANY),0 x202, 0 x06, PWR_MODE_ANY),0 x203, 0 x0a, PWR_MODE_ANY),0 x204, 0 x00, PWR_MODE_ANY),0 x205, 0 x11, PWR_MODE_ANY),0 x207, 0 x0c, PWR_MODE_ANY),0 x2E1, 0 xc0, PWR_MODE_ANY),0 x22D, 0 xb8, PWR_MODE_ANY),0 x234, 0 x60, PWR_MODE_ANY),0 x238, 0 x13, PWR_MODE_ANY),0 x239, 0 x48, PWR_MODE_ANY),0 x23A, 0 x01, PWR_MODE_ANY),0 x23B, 0 x25, PWR_MODE_ANY),0 x23C, 0 x2a, PWR_MODE_ANY),0 x23D, 0 x01, PWR_MODE_ANY),0 x23E, 0 x13, PWR_MODE_ANY),0 x23F, 0 x13, PWR_MODE_ANY),0 x240, 0 x4a, PWR_MODE_ANY),0 x243, 0 x40, PWR_MODE_ANY),0 x244, 0 x02, PWR_MODE_ANY),0 x25D, 0 x00, PWR_MODE_ANY),0 x25E, 0 x3f, PWR_MODE_ANY),0 x25F, 0 xff, PWR_MODE_ANY),0 x273, 0 x33, PWR_MODE_ANY),0 x274, 0 x50, PWR_MODE_ANY),0 x284, 0 x02, PWR_MODE_ANY),0 x285, 0 x02, PWR_MODE_ANY),0 x2A2, 0 x04, PWR_MODE_ANY),0 x25D, 0 x01, PWR_MODE_ANY),0 x2FA, 0 x01, PWR_MODE_ANY),0 x286, 0 x03, PWR_MODE_ANY),0 x287, 0 x03, PWR_MODE_ANY),0 x288, 0 x03, PWR_MODE_ANY),0 x289, 0 x03, PWR_MODE_ANY),0 x2B3, 0 x04, PWR_MODE_ANY),0 x2B6, 0 x0b, PWR_MODE_ANY),0 x2B7, 0 x0b, PWR_MODE_ANY),0 x2B8, 0 x0b, PWR_MODE_ANY),0 x2B9, 0 x0b, PWR_MODE_ANY),0 x2BA, 0 x0b, PWR_MODE_ANY),0 x2BB, 0 x06, PWR_MODE_ANY),0 x2BC, 0 x06, PWR_MODE_ANY),0 x2BD, 0 x06, PWR_MODE_ANY),0 x29E, 0 x06, PWR_MODE_ANY),0 x2E4, 0 x1a, PWR_MODE_ANY),0 x2ED, 0 x25, PWR_MODE_ANY),0 x269, 0 x1a, PWR_MODE_ANY),0 x2F4, 0 x2f, PWR_MODE_ANY),0 x34B, 0 x01, PWR_MODE_ANY),0 x34C, 0 x23, PWR_MODE_ANY),0 x34D, 0 x23, PWR_MODE_ANY),0 x34E, 0 x45, PWR_MODE_ANY),0 x34F, 0 x00, PWR_MODE_ANY),0 x350, 0 x31, PWR_MODE_ANY),0 x351, 0 x00, PWR_MODE_ANY),0 x352, 0 x02, PWR_MODE_ANY),0 x353, 0 x00, PWR_MODE_ANY),0 x354, 0 x01, PWR_MODE_ANY),0 x43, 0 x18, PWR_MODE_ANY),0 x43, 0 x00, PWR_MODE_ANY),static const struct samsung_ufs_phy_cfg tensor_gs101_pre_pwr_hs_config[] = {0 x369, 0 x11, PWR_MODE_ANY),0 x246, 0 x03, PWR_MODE_ANY),/* Calibration for HS mode series A/B */ static const struct samsung_ufs_phy_cfg tensor_gs101_post_pwr_hs_config[] = {0 x8, 0 x60, PWR_MODE_PWM_ANY),0 x222, 0 x08, PWR_MODE_PWM_ANY),0 x246, 0 x01, PWR_MODE_ANY),static const struct samsung_ufs_phy_cfg *tensor_gs101_ufs_phy_cfgs[CFG_TAG_MAX] = {static const char * const tensor_gs101_ufs_phy_clks[] = {"ref_clk" ,static int gs101_phy_wait_for_calibration(struct phy *phy, u8 lane)struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);const unsigned int timeout_us = 40000 ;const unsigned int sleep_us = 40 ;int err;if (err) {"failed to get phy cal done %d\n" , err);return err;#define DELAY_IN_US 40 #define RETRY_CNT 100 static int gs101_phy_wait_for_cdr_lock(struct phy *phy, u8 lane)struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);int i;for (i = 0 ; i < RETRY_CNT; i++) {if (val & LN0_MON_RX_CDR_FLD_CK_MODE_DONE)return 0 ;/* Override and enable clock data recovery */ "failed to get cdr lock\n" );return -ETIMEDOUT;const struct samsung_ufs_phy_drvdata tensor_gs101_ufs_phy = {
Messung V0.5 in Prozent C=97 H=96 G=96
¤ Dauer der Verarbeitung: 0.9 Sekunden
(vorverarbeitet am 2026-06-08)
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