// SPDX-License-Identifier: GPL-2.0-only /* * UFS PHY driver data for Samsung ExynosAuto v920 SoC * * Copyright (C) 2024 Samsung Electronics Co., Ltd. #include "phy-samsung-ufs.h" #define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL 0 x708#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_MASK 0 x1#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0 )#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0 x5e#define EXYNOSAUTOV920_CDR_LOCK_OFFSET 0 xce4#define PHY_EXYNOSAUTOV920_LANE_OFFSET 0 x200#define PHY_TRSV_REG_CFG_AUTOV920(o, v, d) \/* Calibration for phy initialization */ static const struct samsung_ufs_phy_cfg exynosautov920_pre_init_cfg[] = {0 x29, 0 x22, PWR_MODE_ANY),0 x43, 0 x10, PWR_MODE_ANY),0 x3c, 0 x14, PWR_MODE_ANY),0 x46, 0 x48, PWR_MODE_ANY),0 x04, 0 x95, PWR_MODE_ANY),0 x06, 0 x30, PWR_MODE_ANY),0 x200, 0 x00, PWR_MODE_ANY),0 x201, 0 x06, PWR_MODE_ANY),0 x202, 0 x06, PWR_MODE_ANY),0 x203, 0 x0a, PWR_MODE_ANY),0 x204, 0 x00, PWR_MODE_ANY),0 x205, 0 x10, PWR_MODE_ANY),0 x207, 0 x0c, PWR_MODE_ANY),0 x2e1, 0 xc0, PWR_MODE_ANY),0 x22d, 0 xf8, PWR_MODE_ANY),0 x234, 0 x60, PWR_MODE_ANY),0 x238, 0 x13, PWR_MODE_ANY),0 x239, 0 x48, PWR_MODE_ANY),0 x23a, 0 x01, PWR_MODE_ANY),0 x23b, 0 x29, PWR_MODE_ANY),0 x23c, 0 x2a, PWR_MODE_ANY),0 x23d, 0 x01, PWR_MODE_ANY),0 x23e, 0 x14, PWR_MODE_ANY),0 x23f, 0 x13, PWR_MODE_ANY),0 x240, 0 x4a, PWR_MODE_ANY),0 x243, 0 x40, PWR_MODE_ANY),0 x244, 0 x02, PWR_MODE_ANY),0 x25d, 0 x00, PWR_MODE_ANY),0 x25e, 0 x3f, PWR_MODE_ANY),0 x25f, 0 xff, PWR_MODE_ANY),0 x26f, 0 xf0, PWR_MODE_ANY),0 x273, 0 x33, PWR_MODE_ANY),0 x274, 0 x50, PWR_MODE_ANY),0 x284, 0 x02, PWR_MODE_ANY),0 x285, 0 x02, PWR_MODE_ANY),0 x2a2, 0 x04, PWR_MODE_ANY),0 x27d, 0 x01, PWR_MODE_ANY),0 x2fa, 0 x01, PWR_MODE_ANY),0 x286, 0 x03, PWR_MODE_ANY),0 x287, 0 x03, PWR_MODE_ANY),0 x288, 0 x03, PWR_MODE_ANY),0 x289, 0 x03, PWR_MODE_ANY),0 x2b3, 0 x04, PWR_MODE_ANY),0 x2b6, 0 x0b, PWR_MODE_ANY),0 x2b7, 0 x0b, PWR_MODE_ANY),0 x2b8, 0 x0b, PWR_MODE_ANY),0 x2b9, 0 x0b, PWR_MODE_ANY),0 x2ba, 0 x0b, PWR_MODE_ANY),0 x2bb, 0 x06, PWR_MODE_ANY),0 x2bc, 0 x06, PWR_MODE_ANY),0 x2bd, 0 x06, PWR_MODE_ANY),0 x2be, 0 x06, PWR_MODE_ANY),0 x34b, 0 x01, PWR_MODE_ANY),0 x34c, 0 x24, PWR_MODE_ANY),0 x34d, 0 x23, PWR_MODE_ANY),0 x34e, 0 x45, PWR_MODE_ANY),0 x34f, 0 x00, PWR_MODE_ANY),0 x350, 0 x31, PWR_MODE_ANY),0 x351, 0 x00, PWR_MODE_ANY),0 x352, 0 x02, PWR_MODE_ANY),0 x353, 0 x00, PWR_MODE_ANY),0 x354, 0 x01, PWR_MODE_ANY),0 x43, 0 x18, PWR_MODE_ANY),0 x43, 0 x00, PWR_MODE_ANY),/* Calibration for HS mode series A/B */ static const struct samsung_ufs_phy_cfg exynosautov920_pre_pwr_hs_cfg[] = {0 x369, 0 x11, PWR_MODE_ANY),0 x246, 0 x03, PWR_MODE_ANY),static const struct samsung_ufs_phy_cfg exynosautov920_post_pwr_hs_cfg[] = {#define DELAY_IN_US 40 #define RETRY_CNT 100 #define EXYNOSAUTOV920_CDR_LOCK_MASK 0 x8int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane)struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);struct samsung_ufs_phy_cfg cfg[4 ] = {0 x222, 0 x10, PWR_MODE_ANY),0 x222, 0 x18, PWR_MODE_ANY),0 x246, 0 x01, PWR_MODE_ANY),for (i = 0 ; i < RETRY_CNT; i++) {if ((reg & EXYNOSAUTOV920_CDR_LOCK_MASK)2 ], lane);return 0 ;/* Disable and enable CDR */ 0 ], lane);1 ], lane);"failed to get phy cdr lock\n" );return -ETIMEDOUT;static const struct samsung_ufs_phy_cfg *exynosautov920_ufs_phy_cfgs[CFG_TAG_MAX] = {static const char * const exynosautov920_ufs_phy_clks[] = {"ref_clk" ,const struct samsung_ufs_phy_drvdata exynosautov920_ufs_phy = {
Messung V0.5 in Prozent C=94 H=92 G=92
¤ Dauer der Verarbeitung: 0.12 Sekunden
(vorverarbeitet am 2026-06-08)
¤ *© Formatika GbR, Deutschland
