// SPDX-License-Identifier: GPL-2.0-only /* * Samsung Exynos SoC series PCIe PHY driver * * Phy provider for PCIe controller on Exynos SoC series * * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd. * Jaehoon Chung <jh80.chung@samsung.com> #include <linux/io.h>#include <linux/mfd/syscon.h>#include <linux/of_platform.h>#include <linux/platform_device.h>#include <linux/phy/phy.h>#include <linux/regmap.h>#define PCIE_PHY_OFFSET(x) ((x) * 0 x4)/* Sysreg FSYS register offsets and bits for Exynos5433 */ #define PCIE_EXYNOS5433_PHY_MAC_RESET 0 x0208#define PCIE_MAC_RESET_MASK 0 xFF#define PCIE_MAC_RESET BIT(4 )#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0 x1010#define PCIE_REFCLK_GATING_EN BIT(0 )#define PCIE_EXYNOS5433_PHY_COMMON_RESET 0 x1020#define PCIE_PHY_RESET BIT(0 )#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0 x1040#define PCIE_GLOBAL_RESET BIT(0 )#define PCIE_REFCLK BIT(1 )#define PCIE_REFCLK_MASK 0 x16#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5 )/* PMU PCIE PHY isolation control */ #define EXYNOS5433_PMU_PCIE_PHY_OFFSET 0 x730/* For Exynos pcie phy */ struct exynos_pcie_phy {void __iomem *base;struct regmap *pmureg;struct regmap *fsysreg;static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)/* Exynos5433 specific functions */ static int exynos5433_pcie_phy_init(struct phy *phy)struct exynos_pcie_phy *ep = phy_get_drvdata(phy);0 ), 1 );0 );0 );1 );0 );/* PHY refclk 24MHz */ 0 );0 x11, PCIE_PHY_OFFSET(0 x3));/* band gap reference on */ 0 , PCIE_PHY_OFFSET(0 x20));0 , PCIE_PHY_OFFSET(0 x4b));/* jitter tuning */ 0 x34, PCIE_PHY_OFFSET(0 x4));0 x02, PCIE_PHY_OFFSET(0 x7));0 x41, PCIE_PHY_OFFSET(0 x21));0 x7F, PCIE_PHY_OFFSET(0 x14));0 xC0, PCIE_PHY_OFFSET(0 x15));0 x61, PCIE_PHY_OFFSET(0 x36));/* D0 uninit.. */ 0 x44, PCIE_PHY_OFFSET(0 x3D));/* 24MHz */ 0 x94, PCIE_PHY_OFFSET(0 x8));0 xA7, PCIE_PHY_OFFSET(0 x9));0 x93, PCIE_PHY_OFFSET(0 xA));0 x6B, PCIE_PHY_OFFSET(0 xC));0 xA5, PCIE_PHY_OFFSET(0 xF));0 x34, PCIE_PHY_OFFSET(0 x16));0 xA3, PCIE_PHY_OFFSET(0 x17));0 xA7, PCIE_PHY_OFFSET(0 x1A));0 x71, PCIE_PHY_OFFSET(0 x23));0 x4C, PCIE_PHY_OFFSET(0 x24));0 x0E, PCIE_PHY_OFFSET(0 x26));0 x14, PCIE_PHY_OFFSET(0 x7));0 x48, PCIE_PHY_OFFSET(0 x43));0 x44, PCIE_PHY_OFFSET(0 x44));0 x03, PCIE_PHY_OFFSET(0 x45));0 xA7, PCIE_PHY_OFFSET(0 x48));0 x13, PCIE_PHY_OFFSET(0 x54));0 x04, PCIE_PHY_OFFSET(0 x31));0 , PCIE_PHY_OFFSET(0 x32));0 );return 0 ;static int exynos5433_pcie_phy_exit(struct phy *phy)struct exynos_pcie_phy *ep = phy_get_drvdata(phy);0 ), 0 );return 0 ;static const struct phy_ops exynos5433_phy_ops = {exit = exynos5433_pcie_phy_exit,static const struct of_device_id exynos_pcie_phy_match[] = {"samsung,exynos5433-pcie-phy" ,static int exynos_pcie_phy_probe(struct platform_device *pdev)struct device *dev = &pdev->dev;struct exynos_pcie_phy *exynos_phy;struct phy *generic_phy;struct phy_provider *phy_provider;sizeof (*exynos_phy), GFP_KERNEL);if (!exynos_phy)return -ENOMEM;0 );if (IS_ERR(exynos_phy->base))return PTR_ERR(exynos_phy->base);"samsung,pmu-syscon" );if (IS_ERR(exynos_phy->pmureg)) {"PMU regmap lookup failed.\n" );return PTR_ERR(exynos_phy->pmureg);"samsung,fsys-sysreg" );if (IS_ERR(exynos_phy->fsysreg)) {"FSYS sysreg regmap lookup failed.\n" );return PTR_ERR(exynos_phy->fsysreg);if (IS_ERR(generic_phy)) {"failed to create PHY\n" );return PTR_ERR(generic_phy);return PTR_ERR_OR_ZERO(phy_provider);static struct platform_driver exynos_pcie_phy_driver = {"exynos_pcie_phy" ,true ,
Messung V0.5 in Prozent C=95 H=94 G=94
¤ Dauer der Verarbeitung: 0.11 Sekunden
(vorverarbeitet am 2026-06-07)
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