/* SPDX-License-Identifier: GPL-2.0+ * Microchip Sparx5 SerDes driver * * Copyright (c) 2024 Microchip Technology Inc. /* This file is autogenerated by cml-utils 2023-04-13 15:02:00 +0200. * Commit ID: 5ac560288d46048f872ecdb8add53717f1efc0e1 #ifndef _SPARX5_SERDES_REGS_H_#define _SPARX5_SERDES_REGS_H_#include <linux/bitfield.h>#include <linux/types.h>#include <linux/bug.h>enum sparx5_serdes_target {enum sparx5_serdes_tsize_enum {/* sparx5_serdes.c */ extern const unsigned int *tsize;#define TSIZE(o) tsize[o]#define __REG(...) __VA_ARGS__/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */ #define SD10G_LANE_LANE_01(t) \#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\#define SD10G_LANE_LANE_01_CFG_RXDET_EN BIT(4)#define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\#define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\#define SD10G_LANE_LANE_01_CFG_RXDET_STR BIT(5)#define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\#define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */ #define SD10G_LANE_LANE_02(t) \#define SD10G_LANE_LANE_02_CFG_EN_ADV BIT(0)#define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\#define SD10G_LANE_LANE_02_CFG_EN_ADV_GET(x)\#define SD10G_LANE_LANE_02_CFG_EN_MAIN BIT(1)#define SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(x)\#define SD10G_LANE_LANE_02_CFG_EN_MAIN_GET(x)\#define SD10G_LANE_LANE_02_CFG_EN_DLY BIT(2)#define SD10G_LANE_LANE_02_CFG_EN_DLY_SET(x)\#define SD10G_LANE_LANE_02_CFG_EN_DLY_GET(x)\#define SD10G_LANE_LANE_02_CFG_EN_DLY2 BIT(3)#define SD10G_LANE_LANE_02_CFG_EN_DLY2_SET(x)\#define SD10G_LANE_LANE_02_CFG_EN_DLY2_GET(x)\#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0 GENMASK(7, 4)#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET(x)\#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_03 */ #define SD10G_LANE_LANE_03(t) \#define SD10G_LANE_LANE_03_CFG_TAP_MAIN BIT(0)#define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\#define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_04 */ #define SD10G_LANE_LANE_04(t) \#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0 GENMASK(4, 0)#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_06 */ #define SD10G_LANE_LANE_06(t) \#define SD10G_LANE_LANE_06_CFG_PD_DRIVER BIT(0)#define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\#define SD10G_LANE_LANE_06_CFG_PD_DRIVER_GET(x)\#define SD10G_LANE_LANE_06_CFG_PD_CLK BIT(1)#define SD10G_LANE_LANE_06_CFG_PD_CLK_SET(x)\#define SD10G_LANE_LANE_06_CFG_PD_CLK_GET(x)\#define SD10G_LANE_LANE_06_CFG_PD_CML BIT(2)#define SD10G_LANE_LANE_06_CFG_PD_CML_SET(x)\#define SD10G_LANE_LANE_06_CFG_PD_CML_GET(x)\#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN BIT(3)#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET(x)\#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_GET(x)\#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN BIT(4)#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET(x)\#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_GET(x)\#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH BIT(5)#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET(x)\#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0B */ #define SD10G_LANE_LANE_0B(t) \#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0 GENMASK(3, 0)#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_GET(x)\#define SD10G_LANE_LANE_0B_CFG_PD_CTLE BIT(4)#define SD10G_LANE_LANE_0B_CFG_PD_CTLE_SET(x)\#define SD10G_LANE_LANE_0B_CFG_PD_CTLE_GET(x)\#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN BIT(5)#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_SET(x)\#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_GET(x)\#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE BIT(6)#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET(x)\#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_GET(x)\#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ BIT(7)#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_SET(x)\#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0C */ #define SD10G_LANE_LANE_0C(t) \#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE BIT(0)#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_GET(x)\#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ BIT(1)#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_SET(x)\#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_GET(x)\#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE BIT(2)#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_SET(x)\#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_GET(x)\#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ BIT(3)#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_SET(x)\#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_GET(x)\#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE BIT(4)#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET(x)\#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_GET(x)\#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ BIT(5)#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_SET(x)\#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_GET(x)\#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS BIT(6)#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_SET(x)\#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_GET(x)\#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12 BIT(7)#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_SET(x)\#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0D */ #define SD10G_LANE_LANE_0D(t) \#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0 GENMASK(1, 0)#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_GET(x)\#define SD10G_LANE_LANE_0D_CFG_EQR_BYP BIT(4)#define SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(x)\#define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0E */ #define SD10G_LANE_LANE_0E(t) \#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0 GENMASK(3, 0)#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_GET(x)\#define SD10G_LANE_LANE_0E_CFG_RXLB_EN BIT(4)#define SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(x)\#define SD10G_LANE_LANE_0E_CFG_RXLB_EN_GET(x)\#define SD10G_LANE_LANE_0E_CFG_TXLB_EN BIT(5)#define SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(x)\#define SD10G_LANE_LANE_0E_CFG_TXLB_EN_GET(x)\#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN BIT(6)#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET(x)\#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0F */ #define SD10G_LANE_LANE_0F(t) \#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0 GENMASK(7, 0)#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_13 */ #define SD10G_LANE_LANE_13(t) \#define SD10G_LANE_LANE_13_CFG_DCDR_PD BIT(0)#define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\#define SD10G_LANE_LANE_13_CFG_DCDR_PD_GET(x)\#define SD10G_LANE_LANE_13_CFG_PHID_1T BIT(1)#define SD10G_LANE_LANE_13_CFG_PHID_1T_SET(x)\#define SD10G_LANE_LANE_13_CFG_PHID_1T_GET(x)\#define SD10G_LANE_LANE_13_CFG_CDRCK_EN BIT(2)#define SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(x)\#define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_14 */ #define SD10G_LANE_LANE_14(t) \#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0 GENMASK(7, 0)#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_15 */ #define SD10G_LANE_LANE_15(t) \#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8 GENMASK(7, 0)#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_16 */ #define SD10G_LANE_LANE_16(t) \#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16 GENMASK(7, 0)#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_1A */ #define SD10G_LANE_LANE_1A(t) \#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN BIT(0)#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_GET(x)\#define SD10G_LANE_LANE_1A_CFG_PI_EN BIT(1)#define SD10G_LANE_LANE_1A_CFG_PI_EN_SET(x)\#define SD10G_LANE_LANE_1A_CFG_PI_EN_GET(x)\#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN BIT(2)#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET(x)\#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_GET(x)\#define SD10G_LANE_LANE_1A_CFG_PI_STEPS BIT(3)#define SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(x)\#define SD10G_LANE_LANE_1A_CFG_PI_STEPS_GET(x)\#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0 GENMASK(5, 4)#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET(x)\#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_22 */ #define SD10G_LANE_LANE_22(t) \#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1 GENMASK(4, 0)#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_23 */ #define SD10G_LANE_LANE_23(t) \#define SD10G_LANE_LANE_23_CFG_DFE_PD BIT(0)#define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\#define SD10G_LANE_LANE_23_CFG_DFE_PD_GET(x)\#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG BIT(1)#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET(x)\#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_GET(x)\#define SD10G_LANE_LANE_23_CFG_DFECK_EN BIT(2)#define SD10G_LANE_LANE_23_CFG_DFECK_EN_SET(x)\#define SD10G_LANE_LANE_23_CFG_DFECK_EN_GET(x)\#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD BIT(3)#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET(x)\#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_GET(x)\#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0 GENMASK(6, 4)#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_SET(x)\#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_24 */ #define SD10G_LANE_LANE_24(t) \#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0 GENMASK(3, 0)#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_GET(x)\#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0 GENMASK(7, 4)#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_SET(x)\#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_26 */ #define SD10G_LANE_LANE_26(t) \#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0 GENMASK(7, 0)#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_2F */ #define SD10G_LANE_LANE_2F(t) \#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0 GENMASK(2, 0)#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_GET(x)\#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0 GENMASK(7, 4)#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET(x)\#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_30 */ #define SD10G_LANE_LANE_30(t) \#define SD10G_LANE_LANE_30_CFG_SUMMER_EN BIT(0)#define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\#define SD10G_LANE_LANE_30_CFG_SUMMER_EN_GET(x)\#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0 GENMASK(6, 4)#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET(x)\#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_31 */ #define SD10G_LANE_LANE_31(t) \#define SD10G_LANE_LANE_31_CFG_PI_RSTN BIT(0)#define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\#define SD10G_LANE_LANE_31_CFG_PI_RSTN_GET(x)\#define SD10G_LANE_LANE_31_CFG_CDR_RSTN BIT(1)#define SD10G_LANE_LANE_31_CFG_CDR_RSTN_SET(x)\#define SD10G_LANE_LANE_31_CFG_CDR_RSTN_GET(x)\#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG BIT(2)#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET(x)\#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_GET(x)\#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN BIT(3)#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_SET(x)\#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_GET(x)\#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8 BIT(4)#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_SET(x)\#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_GET(x)\#define SD10G_LANE_LANE_31_CFG_R50_EN BIT(5)#define SD10G_LANE_LANE_31_CFG_R50_EN_SET(x)\#define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_32 */ #define SD10G_LANE_LANE_32(t) \#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0 GENMASK(1, 0)#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_GET(x)\#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET(x)\#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_33 */ #define SD10G_LANE_LANE_33(t) \#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 GENMASK(5, 4)#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET(x)\#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_35 */ #define SD10G_LANE_LANE_35(t) \#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0 GENMASK(1, 0)#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_GET(x)\#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0 GENMASK(5, 4)#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET(x)\#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_36 */ #define SD10G_LANE_LANE_36(t) \#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0 GENMASK(1, 0)#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_GET(x)\#define SD10G_LANE_LANE_36_CFG_EID_LP BIT(4)#define SD10G_LANE_LANE_36_CFG_EID_LP_SET(x)\#define SD10G_LANE_LANE_36_CFG_EID_LP_GET(x)\#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH BIT(5)#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_SET(x)\#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_GET(x)\#define SD10G_LANE_LANE_36_CFG_PRBS_SEL BIT(6)#define SD10G_LANE_LANE_36_CFG_PRBS_SEL_SET(x)\#define SD10G_LANE_LANE_36_CFG_PRBS_SEL_GET(x)\#define SD10G_LANE_LANE_36_CFG_PRBS_SETB BIT(7)#define SD10G_LANE_LANE_36_CFG_PRBS_SETB_SET(x)\#define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_37 */ #define SD10G_LANE_LANE_37(t) \#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD BIT(0)#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_GET(x)\#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE BIT(1)#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_SET(x)\#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_GET(x)\#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF BIT(2)#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET(x)\#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_GET(x)\#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0 GENMASK(5, 4)#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET(x)\#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_39 */ #define SD10G_LANE_LANE_39(t) \#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0 GENMASK(2, 0)#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_GET(x)\#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH BIT(4)#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET(x)\#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3A */ #define SD10G_LANE_LANE_3A(t) \#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0 GENMASK(3, 0)#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_GET(x)\#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0 GENMASK(7, 4)#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET(x)\#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3C */ #define SD10G_LANE_LANE_3C(t) \#define SD10G_LANE_LANE_3C_CFG_DIS_ACC BIT(0)#define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\#define SD10G_LANE_LANE_3C_CFG_DIS_ACC_GET(x)\#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER BIT(1)#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET(x)\#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_40 */ #define SD10G_LANE_LANE_40(t) \#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0 GENMASK(7, 0)#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_41 */ #define SD10G_LANE_LANE_41(t) \#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8 GENMASK(7, 0)#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_42 */ #define SD10G_LANE_LANE_42(t) \#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0 GENMASK(2, 0)#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_GET(x)\#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0 GENMASK(6, 4)#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_SET(x)\#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_48 */ #define SD10G_LANE_LANE_48(t) \#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0 GENMASK(3, 0)#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_GET(x)\#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL BIT(4)#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_SET(x)\#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_GET(x)\#define SD10G_LANE_LANE_48_CFG_CLK_ENQ BIT(5)#define SD10G_LANE_LANE_48_CFG_CLK_ENQ_SET(x)\#define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_50 */ #define SD10G_LANE_LANE_50(t) \#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0 GENMASK(1, 0)#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_GET(x)\#define SD10G_LANE_LANE_50_CFG_SSC_RESETB BIT(4)#define SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(x)\#define SD10G_LANE_LANE_50_CFG_SSC_RESETB_GET(x)\#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL BIT(5)#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET(x)\#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_GET(x)\#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL BIT(6)#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_SET(x)\#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_GET(x)\#define SD10G_LANE_LANE_50_CFG_JT_EN BIT(7)#define SD10G_LANE_LANE_50_CFG_JT_EN_SET(x)\#define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_2:LANE_52 */ #define SD10G_LANE_LANE_52(t) \#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0 GENMASK(5, 0)#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_4:LANE_83 */ #define SD10G_LANE_LANE_83(t) \#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE BIT(0)#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_GET(x)\#define SD10G_LANE_LANE_83_R_TX_POL_INV BIT(1)#define SD10G_LANE_LANE_83_R_TX_POL_INV_SET(x)\#define SD10G_LANE_LANE_83_R_TX_POL_INV_GET(x)\#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE BIT(2)#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_SET(x)\#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_GET(x)\#define SD10G_LANE_LANE_83_R_RX_POL_INV BIT(3)#define SD10G_LANE_LANE_83_R_RX_POL_INV_SET(x)\#define SD10G_LANE_LANE_83_R_RX_POL_INV_GET(x)\#define SD10G_LANE_LANE_83_R_DFE_RSTN BIT(4)#define SD10G_LANE_LANE_83_R_DFE_RSTN_SET(x)\#define SD10G_LANE_LANE_83_R_DFE_RSTN_GET(x)\#define SD10G_LANE_LANE_83_R_CDR_RSTN BIT(5)#define SD10G_LANE_LANE_83_R_CDR_RSTN_SET(x)\#define SD10G_LANE_LANE_83_R_CDR_RSTN_GET(x)\#define SD10G_LANE_LANE_83_R_CTLE_RSTN BIT(6)#define SD10G_LANE_LANE_83_R_CTLE_RSTN_SET(x)\#define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_93 */ #define SD10G_LANE_LANE_93(t) \#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN BIT(0)#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_GET(x)\#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT BIT(1)#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(x)\#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_GET(x)\#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE BIT(2)#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_SET(x)\#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_GET(x)\#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL BIT(3)#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(x)\#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_GET(x)\#define SD10G_LANE_LANE_93_R_REG_MANUAL BIT(4)#define SD10G_LANE_LANE_93_R_REG_MANUAL_SET(x)\#define SD10G_LANE_LANE_93_R_REG_MANUAL_GET(x)\#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT BIT(5)#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(x)\#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_GET(x)\#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT BIT(6)#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(x)\#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_GET(x)\#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT BIT(7)#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_SET(x)\#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_94 */ #define SD10G_LANE_LANE_94(t) \#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0 GENMASK(2, 0)#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_GET(x)\#define SD10G_LANE_LANE_94_R_ISCAN_REG BIT(4)#define SD10G_LANE_LANE_94_R_ISCAN_REG_SET(x)\#define SD10G_LANE_LANE_94_R_ISCAN_REG_GET(x)\#define SD10G_LANE_LANE_94_R_TXEQ_REG BIT(5)#define SD10G_LANE_LANE_94_R_TXEQ_REG_SET(x)\#define SD10G_LANE_LANE_94_R_TXEQ_REG_GET(x)\#define SD10G_LANE_LANE_94_R_MISC_REG BIT(6)#define SD10G_LANE_LANE_94_R_MISC_REG_SET(x)\#define SD10G_LANE_LANE_94_R_MISC_REG_GET(x)\#define SD10G_LANE_LANE_94_R_SWING_REG BIT(7)#define SD10G_LANE_LANE_94_R_SWING_REG_SET(x)\#define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_9E */ #define SD10G_LANE_LANE_9E(t) \#define SD10G_LANE_LANE_9E_R_RXEQ_REG BIT(0)#define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\#define SD10G_LANE_LANE_9E_R_RXEQ_REG_GET(x)\#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN BIT(1)#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_SET(x)\#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_GET(x)\#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN BIT(2)#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET(x)\#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A1 */ #define SD10G_LANE_LANE_A1(t) \#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0 GENMASK(1, 0)#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_GET(x)\#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT BIT(4)#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(x)\#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_GET(x)\#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT BIT(5)#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(x)\#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_GET(x)\#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT BIT(6)#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(x)\#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_GET(x)\#define SD10G_LANE_LANE_A1_R_PCLK_GATING BIT(7)#define SD10G_LANE_LANE_A1_R_PCLK_GATING_SET(x)\#define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A2 */ #define SD10G_LANE_LANE_A2(t) \#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0)#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */ #define SD10G_LANE_LANE_DF(t) \#define SD10G_LANE_LANE_DF_LOL_UDL BIT(0)#define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\#define SD10G_LANE_LANE_DF_LOL_UDL_GET(x)\#define SD10G_LANE_LANE_DF_LOL BIT(1)#define SD10G_LANE_LANE_DF_LOL_SET(x)\#define SD10G_LANE_LANE_DF_LOL_GET(x)\#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED BIT(2)#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\#define SD10G_LANE_LANE_DF_SQUELCH BIT(3)#define SD10G_LANE_LANE_DF_SQUELCH_SET(x)\#define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_0:CMU_09 */ #define SD25G_LANE_CMU_09(t) \#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN BIT(0)#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_GET(x)\#define SD25G_LANE_CMU_09_CFG_EN_DUMMY BIT(1)#define SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(x)\#define SD25G_LANE_CMU_09_CFG_EN_DUMMY_GET(x)\#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET BIT(2)#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_SET(x)\#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_GET(x)\#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD BIT(3)#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_SET(x)\#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_GET(x)\#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0 GENMASK(5, 4)#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_SET(x)\#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_0:CMU_0B */ #define SD25G_LANE_CMU_0B(t) \#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT BIT(0)#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_GET(x)\#define SD25G_LANE_CMU_0B_CFG_DISLOL BIT(1)#define SD25G_LANE_CMU_0B_CFG_DISLOL_SET(x)\#define SD25G_LANE_CMU_0B_CFG_DISLOL_GET(x)\#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN BIT(2)#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_SET(x)\#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_GET(x)\#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN BIT(3)#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(x)\#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_GET(x)\#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD BIT(4)#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_SET(x)\#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_GET(x)\#define SD25G_LANE_CMU_0B_CFG_DISLOS BIT(5)#define SD25G_LANE_CMU_0B_CFG_DISLOS_SET(x)\#define SD25G_LANE_CMU_0B_CFG_DISLOS_GET(x)\#define SD25G_LANE_CMU_0B_CFG_DCLOL BIT(6)#define SD25G_LANE_CMU_0B_CFG_DCLOL_SET(x)\#define SD25G_LANE_CMU_0B_CFG_DCLOL_GET(x)\#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN BIT(7)#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_SET(x)\#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_0:CMU_0C */ #define SD25G_LANE_CMU_0C(t) \#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET BIT(0)#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(x)\#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_GET(x)\#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN BIT(1)#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_SET(x)\#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_GET(x)\#define SD25G_LANE_CMU_0C_CFG_VCO_PD BIT(2)#define SD25G_LANE_CMU_0C_CFG_VCO_PD_SET(x)\#define SD25G_LANE_CMU_0C_CFG_VCO_PD_GET(x)\#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP BIT(3)#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_SET(x)\#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_GET(x)\#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0 GENMASK(5, 4)#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET(x)\#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_0:CMU_0D */ #define SD25G_LANE_CMU_0D(t) \#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD BIT(0)#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_SET(x)\#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_GET(x)\#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN BIT(1)#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_SET(x)\#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_GET(x)\#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP BIT(2)#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_SET(x)\#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_GET(x)\#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP BIT(3)#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_SET(x)\#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_GET(x)\#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0 GENMASK(5, 4)#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET(x)\#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_0:CMU_0E */ #define SD25G_LANE_CMU_0E(t) \#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0 GENMASK(3, 0)#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(x)\#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_GET(x)\#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD BIT(4)#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_SET(x)\#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_0:CMU_13 */ #define SD25G_LANE_CMU_13(t) \#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0 GENMASK(3, 0)#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(x)\#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_GET(x)\#define SD25G_LANE_CMU_13_CFG_JT_EN BIT(4)#define SD25G_LANE_CMU_13_CFG_JT_EN_SET(x)\#define SD25G_LANE_CMU_13_CFG_JT_EN_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_0:CMU_18 */ #define SD25G_LANE_CMU_18(t) \#define SD25G_LANE_CMU_18_R_PLL_RSTN BIT(0)#define SD25G_LANE_CMU_18_R_PLL_RSTN_SET(x)\#define SD25G_LANE_CMU_18_R_PLL_RSTN_GET(x)\#define SD25G_LANE_CMU_18_R_PLL_LOL_SET BIT(1)#define SD25G_LANE_CMU_18_R_PLL_LOL_SET_SET(x)\#define SD25G_LANE_CMU_18_R_PLL_LOL_SET_GET(x)\#define SD25G_LANE_CMU_18_R_PLL_LOS_SET BIT(2)#define SD25G_LANE_CMU_18_R_PLL_LOS_SET_SET(x)\#define SD25G_LANE_CMU_18_R_PLL_LOS_SET_GET(x)\#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0 GENMASK(5, 4)#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_SET(x)\#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_0:CMU_19 */ #define SD25G_LANE_CMU_19(t) \#define SD25G_LANE_CMU_19_R_CK_RESETB BIT(0)#define SD25G_LANE_CMU_19_R_CK_RESETB_SET(x)\#define SD25G_LANE_CMU_19_R_CK_RESETB_GET(x)\#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN BIT(1)#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_SET(x)\#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_0:CMU_1A */ #define SD25G_LANE_CMU_1A(t) \#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0 GENMASK(2, 0)#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(x)\#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_GET(x)\#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT BIT(4)#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET(x)\#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_GET(x)\#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE BIT(5)#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_SET(x)\#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_GET(x)\#define SD25G_LANE_CMU_1A_R_REG_MANUAL BIT(6)#define SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(x)\#define SD25G_LANE_CMU_1A_R_REG_MANUAL_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_1:CMU_2A */ #define SD25G_LANE_CMU_2A(t) \#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0 GENMASK(1, 0)#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_SET(x)\#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_GET(x)\#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE BIT(4)#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_SET(x)\#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_GET(x)\#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS BIT(5)#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(x)\#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_1:CMU_30 */ #define SD25G_LANE_CMU_30(t) \#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 GENMASK(2, 0)#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET(x)\#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_GET(x)\#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0 GENMASK(6, 4)#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET(x)\#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_1:CMU_31 */ #define SD25G_LANE_CMU_31(t) \#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0 GENMASK(7, 0)#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(x)\#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_2:CMU_40 */ #define SD25G_LANE_CMU_40(t) \#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL BIT(0)#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_SET(x)\#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_GET(x)\#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD BIT(1)#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_SET(x)\#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_GET(x)\#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK BIT(2)#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_SET(x)\#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_GET(x)\#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN BIT(3)#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(x)\#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_GET(x)\#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN BIT(4)#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_SET(x)\#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_GET(x)\#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST BIT(5)#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_SET(x)\#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_2:CMU_45 */ #define SD25G_LANE_CMU_45(t) \#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0 GENMASK(7, 0)#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(x)\#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_2:CMU_46 */ #define SD25G_LANE_CMU_46(t) \#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8 GENMASK(7, 0)#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET(x)\#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_3:CMU_C0 */ #define SD25G_LANE_CMU_C0(t) \#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0 GENMASK(3, 0)#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_SET(x)\#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_GET(x)\#define SD25G_LANE_CMU_C0_PLL_LOL_UDL BIT(4)#define SD25G_LANE_CMU_C0_PLL_LOL_UDL_SET(x)\#define SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:CMU_GRP_4:CMU_FF */ #define SD25G_LANE_CMU_FF(t) \#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX GENMASK(7, 0)#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(x)\#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:LANE_GRP_0:LANE_00 */ #define SD25G_LANE_LANE_00(t) \#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0 GENMASK(3, 0)#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_SET(x)\#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_GET(x)\#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET(x)\#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:LANE_GRP_0:LANE_01 */ #define SD25G_LANE_LANE_01(t) \#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0 GENMASK(5, 4)#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET(x)\#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:LANE_GRP_0:LANE_03 */ #define SD25G_LANE_LANE_03(t) \#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0 GENMASK(4, 0)#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(x)\#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_GET(x)\/* SPARX5 ONLY */ /* SD25G_TARGET:LANE_GRP_0:LANE_04 */ #define SD25G_LANE_LANE_04(t) \#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN BIT(0)#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(x)\#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_GET(x)\#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN BIT(1)#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(x)\#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_GET(x)\#define SD25G_LANE_LANE_04_LN_CFG_PD_CML BIT(2)#define SD25G_LANE_LANE_04_LN_CFG_PD_CML_SET(x)\#define SD25G_LANE_LANE_04_LN_CFG_PD_CML_GET(x)\#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK BIT(3)
Messung V0.5 C=95 H=100 G=97
¤ Dauer der Verarbeitung: 0.16 Sekunden
(vorverarbeitet)
¤ *© Formatika GbR, Deutschland
