#define PCIE_AHB_TRANS_BASE0_L 0x438 #define PCIE_AHB_TRANS_BASE0_H 0x43c #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0)) #define PCIE_AXI_WINDOW0 0x448 #define WIN_ENABLE BIT(7) /* * Define PCIe to AHB window size as 2^33 to support max 8GB address space * translate, support least 4GB DRAM size access from EP DMA(physical DRAM * start from 0x40000000).
*/ #define PCIE2AHB_SIZE 0x21
/** * struct mtk_pcie_soc - differentiate between host generations * @need_fix_class_id: whether this host's class ID needed to be fixed or not * @need_fix_device_id: whether this host's device ID needed to be fixed or not * @no_msi: Bridge has no MSI support, and relies on an external block * @device_id: device ID which this host need to be fixed * @ops: pointer to configuration access functions * @startup: pointer to controller setting functions * @setup_irq: pointer to initialize IRQ functions
*/ struct mtk_pcie_soc { bool need_fix_class_id; bool need_fix_device_id; bool no_msi; unsignedint device_id; struct pci_ops *ops; int (*startup)(struct mtk_pcie_port *port); int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
};
/** * struct mtk_pcie_port - PCIe port information * @base: IO mapped register base * @list: port list * @pcie: pointer to PCIe host info * @reset: pointer to port reset control * @sys_ck: pointer to transaction/data link layer clock * @ahb_ck: pointer to AHB slave interface operating clock for CSR access * and RC initiated MMIO access * @axi_ck: pointer to application layer MMIO channel operating clock * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock * when pcie_mac_ck/pcie_pipe_ck is turned off * @obff_ck: pointer to OBFF functional block operating clock * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock * @phy: pointer to PHY control block * @slot: port slot * @irq: GIC irq * @irq_domain: legacy INTx IRQ domain * @inner_domain: inner IRQ domain * @lock: protect the msi_irq_in_use bitmap * @msi_irq_in_use: bit map for assigned MSI IRQ
*/ struct mtk_pcie_port { void __iomem *base; struct list_head list; struct mtk_pcie *pcie; struct reset_control *reset; struct clk *sys_ck; struct clk *ahb_ck; struct clk *axi_ck; struct clk *aux_ck; struct clk *obff_ck; struct clk *pipe_ck; struct phy *phy;
u32 slot; int irq; struct irq_domain *irq_domain; struct irq_domain *inner_domain; struct mutex lock;
DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
};
/** * struct mtk_pcie - PCIe host information * @dev: pointer to PCIe device * @base: IO mapped register base * @cfg: IO mapped register map for PCIe config * @free_ck: free-run reference clock * @ports: pointer to PCIe port information * @soc: pointer to SoC-dependent operations
*/ struct mtk_pcie { struct device *dev; void __iomem *base; struct regmap *cfg; struct clk *free_ck;
/* * Walk the bus hierarchy to get the devfn value * of the port in the root bus.
*/ while (bus && bus->number) {
dev = bus->self;
bus = dev->bus;
devfn = dev->devfn;
}
list_for_each_entry(port, &pcie->ports, list) if (port->slot == PCI_SLOT(devfn)) return port;
return NULL;
}
staticint mtk_pcie_config_read(struct pci_bus *bus, unsignedint devfn, int where, int size, u32 *val)
{ struct mtk_pcie_port *port;
u32 bn = bus->number;
port = mtk_pcie_find_port(bus, devfn); if (!port) return PCIBIOS_DEVICE_NOT_FOUND;
status = readl(port->base + PCIE_INT_STATUS); if (status & INTX_MASK) {
for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { /* Clear the INTx */
writel(1 << bit, port->base + PCIE_INT_STATUS);
generic_handle_domain_irq(port->irq_domain,
bit - INTX_SHIFT);
}
}
if (IS_ENABLED(CONFIG_PCI_MSI)) { if (status & MSI_STATUS){ unsignedlong imsi_status;
/* * The interrupt status can be cleared even if the * MSI status remains pending. As such, given the * edge-triggered interrupt type, its status should * be cleared before being dispatched to the * handler of the underlying device.
*/
writel(MSI_STATUS, port->base + PCIE_INT_STATUS); while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM)
generic_handle_domain_irq(port->inner_domain, bit);
}
}
}
entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); if (entry)
mem = entry->res; if (!mem) return -EINVAL;
/* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ if (pcie->base) {
val = readl(pcie->base + PCIE_SYS_CFG_V2);
val |= PCIE_CSR_LTSSM_EN(port->slot) |
PCIE_CSR_ASPM_L1_EN(port->slot);
writel(val, pcie->base + PCIE_SYS_CFG_V2);
} elseif (pcie->cfg) {
val = PCIE_CSR_LTSSM_EN(port->slot) |
PCIE_CSR_ASPM_L1_EN(port->slot);
regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val);
}
/* Assert all reset signals */
writel(0, port->base + PCIE_RST_CTRL);
/* * Enable PCIe link down reset, if link status changed from link up to * link down, this will reset MAC control registers and configuration * space.
*/
writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
/* * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should * be delayed 100ms (TPVPERL) for the power and clock to become stable.
*/
msleep(100);
/* De-assert PHY, PE, PIPE, MAC and configuration reset */
val = readl(port->base + PCIE_RST_CTRL);
val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
PCIE_MAC_SRSTB | PCIE_CRSTB;
writel(val, port->base + PCIE_RST_CTRL);
/* Set up vendor ID and class code */ if (soc->need_fix_class_id) {
val = PCI_VENDOR_ID_MEDIATEK;
writew(val, port->base + PCIE_CONF_VEND_ID);
val = PCI_CLASS_BRIDGE_PCI;
writew(val, port->base + PCIE_CONF_CLASS_ID);
}
if (soc->need_fix_device_id)
writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
/* 100ms timeout value should be enough for Gen1/2 training */
err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
!!(val & PCIE_PORT_LINKUP_V2), 20,
100 * USEC_PER_MSEC); if (err) return -ETIMEDOUT;
/* Set INTx mask */
val = readl(port->base + PCIE_INT_MASK);
val &= ~INTX_MASK;
writel(val, port->base + PCIE_INT_MASK);
if (IS_ENABLED(CONFIG_PCI_MSI))
mtk_pcie_enable_msi(port);
/* Set AHB to PCIe translation windows */
val = lower_32_bits(mem->start) |
AHB2PCIE_SIZE(fls(resource_size(mem)));
writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
val = upper_32_bits(mem->start);
writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
/* Set PCIe to AXI translation memory space.*/
val = PCIE2AHB_SIZE | WIN_ENABLE;
writel(val, port->base + PCIE_AXI_WINDOW0);
/* assert port PERST_N */
val = readl(pcie->base + PCIE_SYS_CFG);
val |= PCIE_PORT_PERST(port->slot);
writel(val, pcie->base + PCIE_SYS_CFG);
/* de-assert port PERST_N */
val = readl(pcie->base + PCIE_SYS_CFG);
val &= ~PCIE_PORT_PERST(port->slot);
writel(val, pcie->base + PCIE_SYS_CFG);
/* 100ms timeout value should be enough for Gen1/2 training */
err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
!!(val & PCIE_PORT_LINKUP), 20,
100 * USEC_PER_MSEC); if (err) return -ETIMEDOUT;
/* enable interrupt */
val = readl(pcie->base + PCIE_INT_ENABLE);
val |= PCIE_PORT_INT_EN(port->slot);
writel(val, pcie->base + PCIE_INT_ENABLE);
/* map to all DDR region. We need to set it before cfg operation. */
writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
port->base + PCIE_BAR0_SETUP);
/* configure class code and revision ID */
writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
/* configure FC credit */
writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
pcie->base + PCIE_CFG_ADDR);
val = readl(pcie->base + PCIE_CFG_DATA);
val &= ~PCIE_FC_CREDIT_MASK;
val |= PCIE_FC_CREDIT_VAL(0x806c);
writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
pcie->base + PCIE_CFG_ADDR);
writel(val, pcie->base + PCIE_CFG_DATA);
/* configure RC FTS number to 250 when it leaves L0s */
writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
pcie->base + PCIE_CFG_ADDR);
val = readl(pcie->base + PCIE_CFG_DATA);
val &= ~PCIE_FTS_NUM_MASK;
val |= PCIE_FTS_NUM_L0(0x50);
writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
pcie->base + PCIE_CFG_ADDR);
writel(val, pcie->base + PCIE_CFG_DATA);
snprintf(name, sizeof(name), "sys_ck%d", slot);
port->sys_ck = devm_clk_get(dev, name); if (IS_ERR(port->sys_ck)) {
dev_err(dev, "failed to get sys_ck%d clock\n", slot); return PTR_ERR(port->sys_ck);
}
/* sys_ck might be divided into the following parts in some chips */
snprintf(name, sizeof(name), "ahb_ck%d", slot);
port->ahb_ck = devm_clk_get_optional(dev, name); if (IS_ERR(port->ahb_ck)) return PTR_ERR(port->ahb_ck);
/* get shared registers, which are optional */
regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys"); if (regs) {
pcie->base = devm_ioremap_resource(dev, regs); if (IS_ERR(pcie->base)) return PTR_ERR(pcie->base);
}
cfg_node = of_find_compatible_node(NULL, NULL, "mediatek,generic-pciecfg"); if (cfg_node) {
pcie->cfg = syscon_node_to_regmap(cfg_node);
of_node_put(cfg_node); if (IS_ERR(pcie->cfg)) return PTR_ERR(pcie->cfg);
}
pcie->free_ck = devm_clk_get(dev, "free_ck"); if (IS_ERR(pcie->free_ck)) { if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) return -EPROBE_DEFER;
pcie->free_ck = NULL;
}
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
/* enable top level clock */
err = clk_prepare_enable(pcie->free_ck); if (err) {
dev_err(dev, "failed to enable free_ck\n"); goto err_free_ck;
}
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