// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * Copyright (c) 2022, Richard Acayan. All rights reserved. #include <linux/module.h>#include <linux/of.h>#include <linux/platform_device.h>#include "pinctrl-msm.h" #define NORTH 0 x00500000#define SOUTH 0 x00900000#define WEST 0 x00100000#define REG_SIZE 0 x1000#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \"gpio" #id , \## id## _pins, \## id## _pins)), \int []){ \/* gpio mode */ \ ## f1, \## f2, \## f3, \## f4, \## f5, \## f6, \## f7, \## f8, \## f9 \10 , \0 x4 + REG_SIZE * id, \0 x8 + REG_SIZE * id, \0 xc + REG_SIZE * id, \0 x8 + REG_SIZE * id, \2 , \0 , \6 , \9 , \0 , \1 , \0 , \0 , \5 , \3 , \4 , \1 , \2 , \2 , \/* * A dummy pingroup is a pin group that cannot be assigned a function and has * no registers to control or monitor it. #define PINGROUP_DUMMY(id) \"gpio" #id , \## id## _pins, \## id## _pins)), \0 , \0 , \0 , \0 , \0 , \1 , \1 , \1 , \1 , \1 , \1 , \1 , \1 , \1 , \1 , \1 , \1 , \1 , \#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \#pg_name , \## _pins, \## _pins)), \0 , \0 , \0 , \0 , \1 , \1 , \1 , \1 , \1 , \1 , \1 , \1 , \1 , \1 , \1 , \#define UFS_RESET(pg_name, offset) \#pg_name , \## _pins, \## _pins)), \0 x4, \0 , \0 , \0 , \1 , \3 , \0 , \1 , \1 , \0 , \1 , \1 , \1 , \1 , \1 , \1 , \1 , \static const struct pinctrl_pin_desc sdm670_pins[] = {0 , "GPIO_0" ),1 , "GPIO_1" ),2 , "GPIO_2" ),3 , "GPIO_3" ),4 , "GPIO_4" ),5 , "GPIO_5" ),6 , "GPIO_6" ),7 , "GPIO_7" ),8 , "GPIO_8" ),9 , "GPIO_9" ),10 , "GPIO_10" ),11 , "GPIO_11" ),12 , "GPIO_12" ),13 , "GPIO_13" ),14 , "GPIO_14" ),15 , "GPIO_15" ),16 , "GPIO_16" ),17 , "GPIO_17" ),18 , "GPIO_18" ),19 , "GPIO_19" ),20 , "GPIO_20" ),21 , "GPIO_21" ),22 , "GPIO_22" ),23 , "GPIO_23" ),24 , "GPIO_24" ),25 , "GPIO_25" ),26 , "GPIO_26" ),27 , "GPIO_27" ),28 , "GPIO_28" ),29 , "GPIO_29" ),30 , "GPIO_30" ),31 , "GPIO_31" ),32 , "GPIO_32" ),33 , "GPIO_33" ),34 , "GPIO_34" ),35 , "GPIO_35" ),36 , "GPIO_36" ),37 , "GPIO_37" ),38 , "GPIO_38" ),39 , "GPIO_39" ),40 , "GPIO_40" ),41 , "GPIO_41" ),42 , "GPIO_42" ),43 , "GPIO_43" ),44 , "GPIO_44" ),45 , "GPIO_45" ),46 , "GPIO_46" ),47 , "GPIO_47" ),48 , "GPIO_48" ),49 , "GPIO_49" ),50 , "GPIO_50" ),51 , "GPIO_51" ),52 , "GPIO_52" ),53 , "GPIO_53" ),54 , "GPIO_54" ),55 , "GPIO_55" ),56 , "GPIO_56" ),57 , "GPIO_57" ),58 , "GPIO_58" ),59 , "GPIO_59" ),60 , "GPIO_60" ),61 , "GPIO_61" ),62 , "GPIO_62" ),63 , "GPIO_63" ),64 , "GPIO_64" ),65 , "GPIO_65" ),66 , "GPIO_66" ),67 , "GPIO_67" ),68 , "GPIO_68" ),69 , "GPIO_69" ),70 , "GPIO_70" ),71 , "GPIO_71" ),72 , "GPIO_72" ),73 , "GPIO_73" ),74 , "GPIO_74" ),75 , "GPIO_75" ),76 , "GPIO_76" ),77 , "GPIO_77" ),78 , "GPIO_78" ),79 , "GPIO_79" ),80 , "GPIO_80" ),81 , "GPIO_81" ),82 , "GPIO_82" ),83 , "GPIO_83" ),84 , "GPIO_84" ),85 , "GPIO_85" ),86 , "GPIO_86" ),87 , "GPIO_87" ),88 , "GPIO_88" ),89 , "GPIO_89" ),90 , "GPIO_90" ),91 , "GPIO_91" ),92 , "GPIO_92" ),93 , "GPIO_93" ),94 , "GPIO_94" ),95 , "GPIO_95" ),96 , "GPIO_96" ),97 , "GPIO_97" ),98 , "GPIO_98" ),99 , "GPIO_99" ),100 , "GPIO_100" ),101 , "GPIO_101" ),102 , "GPIO_102" ),103 , "GPIO_103" ),104 , "GPIO_104" ),105 , "GPIO_105" ),106 , "GPIO_106" ),107 , "GPIO_107" ),108 , "GPIO_108" ),109 , "GPIO_109" ),110 , "GPIO_110" ),111 , "GPIO_111" ),112 , "GPIO_112" ),113 , "GPIO_113" ),114 , "GPIO_114" ),115 , "GPIO_115" ),116 , "GPIO_116" ),117 , "GPIO_117" ),118 , "GPIO_118" ),119 , "GPIO_119" ),120 , "GPIO_120" ),121 , "GPIO_121" ),122 , "GPIO_122" ),123 , "GPIO_123" ),124 , "GPIO_124" ),125 , "GPIO_125" ),126 , "GPIO_126" ),127 , "GPIO_127" ),128 , "GPIO_128" ),129 , "GPIO_129" ),130 , "GPIO_130" ),131 , "GPIO_131" ),132 , "GPIO_132" ),133 , "GPIO_133" ),134 , "GPIO_134" ),135 , "GPIO_135" ),136 , "GPIO_136" ),137 , "GPIO_137" ),138 , "GPIO_138" ),139 , "GPIO_139" ),140 , "GPIO_140" ),141 , "GPIO_141" ),142 , "GPIO_142" ),143 , "GPIO_143" ),144 , "GPIO_144" ),145 , "GPIO_145" ),146 , "GPIO_146" ),147 , "GPIO_147" ),148 , "GPIO_148" ),149 , "GPIO_149" ),150 , "UFS_RESET" ),151 , "SDC1_RCLK" ),152 , "SDC1_CLK" ),153 , "SDC1_CMD" ),154 , "SDC1_DATA" ),155 , "SDC2_CLK" ),156 , "SDC2_CMD" ),157 , "SDC2_DATA" ),#define DECLARE_MSM_GPIO_PINS(pin) \static const unsigned int gpio## pin## _pins[] = { pin }0 );1 );2 );3 );4 );5 );6 );7 );8 );9 );10 );11 );12 );13 );14 );15 );16 );17 );18 );19 );20 );21 );22 );23 );24 );25 );26 );27 );28 );29 );30 );31 );32 );33 );34 );35 );36 );37 );38 );39 );40 );41 );42 );43 );44 );45 );46 );47 );48 );49 );50 );51 );52 );53 );54 );55 );56 );57 );58 );59 );60 );61 );62 );63 );64 );65 );66 );67 );68 );69 );70 );71 );72 );73 );74 );75 );76 );77 );78 );79 );80 );81 );82 );83 );84 );85 );86 );87 );88 );89 );90 );91 );92 );93 );94 );95 );96 );97 );98 );99 );100 );101 );102 );103 );104 );105 );106 );107 );108 );109 );110 );111 );112 );113 );114 );115 );116 );117 );118 );119 );120 );121 );122 );123 );124 );125 );126 );127 );128 );129 );130 );131 );132 );133 );134 );135 );136 );137 );138 );139 );140 );141 );142 );143 );144 );145 );146 );147 );148 );149 );static const unsigned int ufs_reset_pins[] = { 150 };static const unsigned int sdc1_rclk_pins[] = { 151 };static const unsigned int sdc1_clk_pins[] = { 152 };static const unsigned int sdc1_cmd_pins[] = { 153 };static const unsigned int sdc1_data_pins[] = { 154 };static const unsigned int sdc2_clk_pins[] = { 155 };static const unsigned int sdc2_cmd_pins[] = { 156 };static const unsigned int sdc2_data_pins[] = { 157 };enum sdm670_functions {static const char * const gpio_groups[] = {"gpio0" , "gpio1" , "gpio2" , "gpio3" , "gpio4" , "gpio5" , "gpio6" , "gpio7" ,"gpio8" , "gpio9" , "gpio10" , "gpio11" , "gpio12" , "gpio13" , "gpio14" ,"gpio15" , "gpio16" , "gpio17" , "gpio18" , "gpio19" , "gpio20" , "gpio21" ,"gpio22" , "gpio23" , "gpio24" , "gpio25" , "gpio26" , "gpio27" , "gpio28" ,"gpio29" , "gpio30" , "gpio31" , "gpio32" , "gpio33" , "gpio34" , "gpio35" ,"gpio36" , "gpio37" , "gpio38" , "gpio39" , "gpio40" , "gpio41" , "gpio42" ,"gpio43" , "gpio44" , "gpio45" , "gpio46" , "gpio47" , "gpio48" , "gpio49" ,"gpio50" , "gpio51" , "gpio52" , "gpio53" , "gpio54" , "gpio55" , "gpio56" ,"gpio57" , "gpio65" , "gpio66" , "gpio67" , "gpio68" , "gpio75" , "gpio76" ,"gpio77" , "gpio78" , "gpio79" , "gpio80" , "gpio81" , "gpio82" , "gpio83" ,"gpio84" , "gpio85" , "gpio86" , "gpio87" , "gpio88" , "gpio89" , "gpio90" ,"gpio91" , "gpio92" , "gpio93" , "gpio94" , "gpio95" , "gpio96" , "gpio97" ,"gpio98" , "gpio99" , "gpio100" , "gpio101" , "gpio102" , "gpio103" ,"gpio105" , "gpio106" , "gpio107" , "gpio108" , "gpio109" , "gpio110" ,"gpio111" , "gpio112" , "gpio113" , "gpio114" , "gpio115" , "gpio116" ,"gpio117" , "gpio118" , "gpio119" , "gpio120" , "gpio121" , "gpio122" ,"gpio123" , "gpio124" , "gpio125" , "gpio126" , "gpio127" , "gpio128" ,"gpio129" , "gpio130" , "gpio131" , "gpio132" , "gpio133" , "gpio134" ,"gpio135" , "gpio136" , "gpio137" , "gpio138" , "gpio139" , "gpio140" ,"gpio141" , "gpio142" , "gpio143" , "gpio144" , "gpio145" , "gpio146" ,"gpio147" , "gpio148" , "gpio149" ,static const char * const qup0_groups[] = {"gpio0" , "gpio1" , "gpio2" , "gpio3" ,static const char * const qup9_groups[] = {"gpio4" , "gpio5" , "gpio6" , "gpio7" ,static const char * const qdss_cti_groups[] = {"gpio4" , "gpio5" , "gpio51" , "gpio52" , "gpio90" , "gpio91" ,static const char * const ddr_pxi0_groups[] = {"gpio6" , "gpio7" ,static const char * const ddr_bist_groups[] = {"gpio7" , "gpio8" , "gpio9" , "gpio10" ,static const char * const atest_tsens2_groups[] = {"gpio7" ,static const char * const vsense_trigger_groups[] = {"gpio7" ,static const char * const atest_usb1_groups[] = {"gpio7" ,static const char * const qup_l4_groups[] = {"gpio8" , "gpio35" , "gpio75" , "gpio105" , "gpio123" ,static const char * const gp_pdm1_groups[] = {"gpio8" , "gpio66" ,static const char * const qup_l5_groups[] = {"gpio9" , "gpio36" , "gpio76" , "gpio106" , "gpio124" ,static const char * const mdp_vsync_groups[] = {"gpio10" , "gpio11" , "gpio12" , "gpio97" , "gpio98" ,static const char * const qup_l6_groups[] = {"gpio10" , "gpio37" , "gpio77" , "gpio107" , "gpio125" ,static const char * const wlan2_adc1_groups[] = {"gpio10" ,static const char * const atest_usb11_groups[] = {"gpio10" ,static const char * const ddr_pxi2_groups[] = {"gpio10" , "gpio11" ,static const char * const edp_lcd_groups[] = {"gpio11" ,static const char * const dbg_out_groups[] = {"gpio11" ,static const char * const wlan2_adc0_groups[] = {"gpio11" ,static const char * const atest_usb10_groups[] = {"gpio11" ,static const char * const m_voc_groups[] = {"gpio12" ,static const char * const tsif1_sync_groups[] = {"gpio12" ,static const char * const ddr_pxi3_groups[] = {"gpio12" , "gpio13" ,static const char * const cam_mclk_groups[] = {"gpio13" , "gpio14" , "gpio15" , "gpio16" ,static const char * const pll_bypassnl_groups[] = {"gpio13" ,static const char * const qdss_groups[] = {"gpio13" , "gpio14" , "gpio15" , "gpio16" , "gpio17" , "gpio18" , "gpio19" ,"gpio20" , "gpio21" , "gpio22" , "gpio23" , "gpio24" , "gpio25" , "gpio26" ,"gpio27" , "gpio28" , "gpio29" , "gpio30" , "gpio41" , "gpio42" , "gpio43" ,"gpio44" , "gpio75" , "gpio76" , "gpio77" , "gpio79" , "gpio80" , "gpio93" ,"gpio117" , "gpio118" , "gpio119" , "gpio120" , "gpio121" , "gpio122" ,"gpio123" , "gpio124" ,static const char * const pll_reset_groups[] = {"gpio14" ,static const char * const cci_i2c_groups[] = {"gpio17" , "gpio18" , "gpio19" , "gpio20" ,static const char * const qup1_groups[] = {"gpio17" , "gpio18" , "gpio19" , "gpio20" ,static const char * const cci_timer0_groups[] = {"gpio21" ,static const char * const gcc_gp2_groups[] = {"gpio21" ,static const char * const cci_timer1_groups[] = {"gpio22" ,static const char * const gcc_gp3_groups[] = {"gpio22" ,static const char * const cci_timer2_groups[] = {"gpio23" ,static const char * const cci_timer3_groups[] = {"gpio24" ,static const char * const cci_async_groups[] = {"gpio24" , "gpio25" , "gpio26" ,static const char * const cci_timer4_groups[] = {"gpio25" ,static const char * const jitter_bist_groups[] = {"gpio26" , "gpio35" ,static const char * const qup2_groups[] = {"gpio27" , "gpio28" , "gpio29" , "gpio30" ,static const char * const pll_bist_groups[] = {"gpio27" , "gpio36" ,static const char * const agera_pll_groups[] = {"gpio28" , "gpio37" ,static const char * const atest_tsens_groups[] = {"gpio29" ,static const char * const phase_flag_groups[] = {"gpio29" , "gpio30" , "gpio52" , "gpio53" , "gpio54" , "gpio55" , "gpio56" ,"gpio57" , "gpio75" , "gpio76" , "gpio77" , "gpio89" , "gpio90" , "gpio96" ,"gpio99" , "gpio100" , "gpio101" , "gpio137" , "gpio138" , "gpio139" ,"gpio140" , "gpio141" , "gpio142" , "gpio143" ,static const char * const qup11_groups[] = {"gpio31" , "gpio32" , "gpio33" , "gpio34" ,static const char * const qup14_groups[] = {"gpio31" , "gpio32" , "gpio33" , "gpio34" ,static const char * const pci_e0_groups[] = {"gpio35" , "gpio36" ,static const char * const usb_phy_groups[] = {"gpio38" ,static const char * const lpass_slimbus_groups[] = {"gpio39" ,static const char * const sd_write_groups[] = {"gpio40" ,static const char * const tsif1_error_groups[] = {"gpio40" ,static const char * const qup3_groups[] = {"gpio41" , "gpio42" , "gpio43" , "gpio44" ,static const char * const qup6_groups[] = {"gpio45" , "gpio46" , "gpio47" , "gpio48" ,static const char * const qup12_groups[] = {"gpio49" , "gpio50" , "gpio51" , "gpio52" ,static const char * const qup10_groups[] = {"gpio53" , "gpio54" , "gpio55" , "gpio56" ,static const char * const gp_pdm0_groups[] = {"gpio54" , "gpio95" ,static const char * const wlan1_adc1_groups[] = {"gpio54" ,static const char * const atest_usb13_groups[] = {"gpio54" ,static const char * const ddr_pxi1_groups[] = {"gpio54" , "gpio55" ,static const char * const wlan1_adc0_groups[] = {"gpio55" ,static const char * const atest_usb12_groups[] = {"gpio55" ,static const char * const qua_mi2s_groups[] = {"gpio57" ,static const char * const gcc_gp1_groups[] = {"gpio57" , "gpio78" ,static const char * const pri_mi2s_groups[] = {"gpio65" , "gpio67" , "gpio68" ,static const char * const qup8_groups[] = {"gpio65" , "gpio66" , "gpio67" , "gpio68" ,static const char * const wsa_clk_groups[] = {"gpio65" ,static const char * const pri_mi2s_ws_groups[] = {"gpio66" ,static const char * const wsa_data_groups[] = {"gpio66" ,static const char * const atest_usb2_groups[] = {"gpio67" ,static const char * const atest_usb23_groups[] = {"gpio68" ,static const char * const ter_mi2s_groups[] = {"gpio75" , "gpio76" , "gpio77" , "gpio78" ,static const char * const atest_usb22_groups[] = {"gpio75" ,static const char * const atest_usb21_groups[] = {"gpio76" ,static const char * const atest_usb20_groups[] = {"gpio77" ,static const char * const sec_mi2s_groups[] = {"gpio79" , "gpio80" , "gpio81" , "gpio82" , "gpio83" ,static const char * const gp_pdm2_groups[] = {"gpio79" ,static const char * const qup15_groups[] = {"gpio81" , "gpio82" , "gpio83" , "gpio84" ,static const char * const qup5_groups[] = {"gpio85" , "gpio86" , "gpio87" , "gpio88" ,static const char * const copy_gp_groups[] = {"gpio86" ,static const char * const tsif1_clk_groups[] = {"gpio89" ,static const char * const qup4_groups[] = {"gpio89" , "gpio90" , "gpio91" , "gpio92" ,static const char * const tgu_ch3_groups[] = {"gpio89" ,static const char * const tsif1_en_groups[] = {"gpio90" ,static const char * const mdp_vsync0_groups[] = {"gpio90" ,static const char * const mdp_vsync1_groups[] = {"gpio90" ,static const char * const mdp_vsync2_groups[] = {"gpio90" ,static const char * const mdp_vsync3_groups[] = {"gpio90" ,static const char * const tgu_ch0_groups[] = {"gpio90" ,static const char * const tsif1_data_groups[] = {"gpio91" ,static const char * const sdc4_cmd_groups[] = {"gpio91" ,static const char * const tgu_ch1_groups[] = {"gpio91" ,static const char * const tsif2_error_groups[] = {"gpio92" ,static const char * const vfr_1_groups[] = {"gpio92" ,static const char * const tgu_ch2_groups[] = {"gpio92" ,static const char * const sdc4_data_groups[] = {"gpio92" , "gpio94" , "gpio95" , "gpio96" ,static const char * const tsif2_clk_groups[] = {"gpio93" ,static const char * const sdc4_clk_groups[] = {"gpio93" ,static const char * const qup7_groups[] = {"gpio93" , "gpio94" , "gpio95" , "gpio96" ,static const char * const tsif2_en_groups[] = {"gpio94" ,static const char * const tsif2_data_groups[] = {"gpio95" ,static const char * const tsif2_sync_groups[] = {"gpio96" ,static const char * const ldo_en_groups[] = {"gpio97" ,static const char * const ldo_update_groups[] = {"gpio98" ,static const char * const prng_rosc_groups[] = {"gpio99" , "gpio102" ,static const char * const pci_e1_groups[] = {"gpio102" , "gpio103" ,static const char * const copy_phase_groups[] = {"gpio103" ,static const char * const uim2_data_groups[] = {"gpio105" ,static const char * const qup13_groups[] = {"gpio105" , "gpio106" , "gpio107" , "gpio108" ,static const char * const uim2_clk_groups[] = {"gpio106" ,static const char * const uim2_reset_groups[] = {"gpio107" ,static const char * const uim2_present_groups[] = {"gpio108" ,static const char * const uim1_data_groups[] = {"gpio109" ,static const char * const uim1_clk_groups[] = {"gpio110" ,static const char * const uim1_reset_groups[] = {"gpio111" ,static const char * const uim1_present_groups[] = {"gpio112" ,static const char * const uim_batt_groups[] = {"gpio113" ,static const char * const edp_hot_groups[] = {"gpio113" ,static const char * const nav_pps_groups[] = {"gpio114" , "gpio114" , "gpio115" , "gpio115" , "gpio128" , "gpio128" ,"gpio129" , "gpio129" , "gpio143" , "gpio143" ,static const char * const gps_tx_groups[] = {"gpio114" , "gpio115" , "gpio128" , "gpio129" , "gpio143" , "gpio145" ,static const char * const atest_char_groups[] = {"gpio117" , "gpio118" , "gpio119" , "gpio120" , "gpio121" ,static const char * const adsp_ext_groups[] = {"gpio118" ,static const char * const qlink_request_groups[] = {"gpio130" ,static const char * const qlink_enable_groups[] = {"gpio131" ,static const char * const pa_indicator_groups[] = {"gpio135" ,static const char * const mss_lte_groups[] = {"gpio144" , "gpio145" ,static const struct pinfunction sdm670_functions[] = {/* * Each pin is individually controlled by its own group and gpios that cannot * be requested are represented by the PINGROUP_DUMMY macro so that the group * numbers and names correspond to their respective gpio. These dummy pins do * not have a valid set of pinfuncs or a valid ctl_reg and should not be * requested. static const struct msm_pingroup sdm670_groups[] = {0 , SOUTH, qup0, _, _, _, _, _, _, _, _),1 , SOUTH, qup0, _, _, _, _, _, _, _, _),2 , SOUTH, qup0, _, _, _, _, _, _, _, _),3 , SOUTH, qup0, _, _, _, _, _, _, _, _),4 , NORTH, qup9, qdss_cti, _, _, _, _, _, _, _),5 , NORTH, qup9, qdss_cti, _, _, _, _, _, _, _),6 , NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _),7 , NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _),8 , WEST, qup_l4, gp_pdm1, ddr_bist, _, _, _, _, _, _),9 , WEST, qup_l5, ddr_bist, _, _, _, _, _, _, _),10 , NORTH, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _),11 , NORTH, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _),12 , SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _),13 , WEST, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _),14 , WEST, cam_mclk, pll_reset, qdss, _, _, _, _, _, _),15 , WEST, cam_mclk, qdss, _, _, _, _, _, _, _),16 , WEST, cam_mclk, qdss, _, _, _, _, _, _, _),17 , WEST, cci_i2c, qup1, qdss, _, _, _, _, _, _),18 , WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _),19 , WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _),20 , WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _),21 , WEST, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _),22 , WEST, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _),23 , WEST, cci_timer2, qdss, _, _, _, _, _, _, _),24 , WEST, cci_timer3, cci_async, qdss, _, _, _, _, _, _),25 , WEST, cci_timer4, cci_async, qdss, _, _, _, _, _, _),26 , WEST, cci_async, qdss, jitter_bist, _, _, _, _, _, _),27 , WEST, qup2, qdss, pll_bist, _, _, _, _, _, _),28 , WEST, qup2, qdss, agera_pll, _, _, _, _, _, _),29 , WEST, qup2, _, phase_flag, qdss, atest_tsens, _, _, _, _),30 , WEST, qup2, phase_flag, qdss, _, _, _, _, _, _),31 , WEST, qup11, qup14, _, _, _, _, _, _, _),32 , WEST, qup11, qup14, _, _, _, _, _, _, _),33 , WEST, qup11, qup14, _, _, _, _, _, _, _),34 , WEST, qup11, qup14, _, _, _, _, _, _, _),35 , NORTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _),36 , NORTH, pci_e0, qup_l5, pll_bist, _, _, _, _, _, _),37 , NORTH, qup_l6, agera_pll, _, _, _, _, _, _, _),38 , NORTH, usb_phy, _, _, _, _, _, _, _, _),39 , NORTH, lpass_slimbus, _, _, _, _, _, _, _, _),40 , NORTH, sd_write, tsif1_error, _, _, _, _, _, _, _),41 , SOUTH, qup3, _, qdss, _, _, _, _, _, _),42 , SOUTH, qup3, _, qdss, _, _, _, _, _, _),43 , SOUTH, qup3, _, qdss, _, _, _, _, _, _),44 , SOUTH, qup3, _, qdss, _, _, _, _, _, _),45 , SOUTH, qup6, _, _, _, _, _, _, _, _),46 , SOUTH, qup6, _, _, _, _, _, _, _, _),47 , SOUTH, qup6, _, _, _, _, _, _, _, _),48 , SOUTH, qup6, _, _, _, _, _, _, _, _),49 , NORTH, qup12, _, _, _, _, _, _, _, _),50 , NORTH, qup12, _, _, _, _, _, _, _, _),51 , NORTH, qup12, qdss_cti, _, _, _, _, _, _, _),52 , NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _),53 , NORTH, qup10, phase_flag, _, _, _, _, _, _, _),54 , NORTH, qup10, gp_pdm0, phase_flag, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),55 , NORTH, qup10, phase_flag, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _),56 , NORTH, qup10, phase_flag, _, _, _, _, _, _, _),57 , NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _),58 ),59 ),60 ),61 ),62 ),63 ),64 ),65 , NORTH, pri_mi2s, qup8, wsa_clk, _, _, _, _, _, _),66 , NORTH, pri_mi2s_ws, qup8, wsa_data, gp_pdm1, _, _, _, _, _),67 , NORTH, pri_mi2s, qup8, _, atest_usb2, _, _, _, _, _),68 , NORTH, pri_mi2s, qup8, _, atest_usb23, _, _, _, _, _),69 ),70 ),71 ),72 ),73 ),74 ),75 , NORTH, ter_mi2s, phase_flag, qdss, atest_usb22, qup_l4, _, _, _, _),76 , NORTH, ter_mi2s, phase_flag, qdss, atest_usb21, qup_l5, _, _, _, _),77 , NORTH, ter_mi2s, phase_flag, qdss, atest_usb20, qup_l6, _, _, _, _),78 , NORTH, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _),79 , NORTH, sec_mi2s, gp_pdm2, _, qdss, _, _, _, _, _),80 , NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _),81 , NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _),82 , NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _),83 , NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _),84 , NORTH, qup15, _, _, _, _, _, _, _, _),85 , SOUTH, qup5, _, _, _, _, _, _, _, _),86 , SOUTH, qup5, copy_gp, _, _, _, _, _, _, _),87 , SOUTH, qup5, _, _, _, _, _, _, _, _),88 , SOUTH, qup5, _, _, _, _, _, _, _, _),89 , SOUTH, tsif1_clk, qup4, tgu_ch3, phase_flag, _, _, _, _, _),90 , SOUTH, tsif1_en, mdp_vsync0, qup4, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti),91 , SOUTH, tsif1_data, sdc4_cmd, qup4, tgu_ch1, _, qdss_cti, _, _, _),92 , SOUTH, tsif2_error, sdc4_data, qup4, vfr_1, tgu_ch2, _, _, _, _),93 , SOUTH, tsif2_clk, sdc4_clk, qup7, _, qdss, _, _, _, _),94 , SOUTH, tsif2_en, sdc4_data, qup7, _, _, _, _, _, _),95 , SOUTH, tsif2_data, sdc4_data, qup7, gp_pdm0, _, _, _, _, _),96 , SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _),97 , WEST, _, _, mdp_vsync, ldo_en, _, _, _, _, _),98 , WEST, _, mdp_vsync, ldo_update, _, _, _, _, _, _),99 , NORTH, phase_flag, prng_rosc, _, _, _, _, _, _, _),100 , WEST, phase_flag, _, _, _, _, _, _, _, _),101 , WEST, _, phase_flag, _, _, _, _, _, _, _),102 , WEST, pci_e1, prng_rosc, _, _, _, _, _, _, _),103 , WEST, pci_e1, copy_phase, _, _, _, _, _, _, _),104 ),105 , NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _),106 , NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _),107 , NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _),108 , NORTH, uim2_present, qup13, _, _, _, _, _, _, _),109 , NORTH, uim1_data, _, _, _, _, _, _, _, _),110 , NORTH, uim1_clk, _, _, _, _, _, _, _, _),111 , NORTH, uim1_reset, _, _, _, _, _, _, _, _),112 , NORTH, uim1_present, _, _, _, _, _, _, _, _),113 , NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _),114 , WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _),115 , WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _),116 , SOUTH, _, _, _, _, _, _, _, _, _),117 , NORTH, _, qdss, atest_char, _, _, _, _, _, _),118 , NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _),119 , NORTH, _, qdss, atest_char, _, _, _, _, _, _),120 , NORTH, _, qdss, atest_char, _, _, _, _, _, _),121 , NORTH, _, qdss, atest_char, _, _, _, _, _, _),122 , NORTH, _, qdss, _, _, _, _, _, _, _),123 , NORTH, qup_l4, _, qdss, _, _, _, _, _, _),124 , NORTH, qup_l5, _, qdss, _, _, _, _, _, _),125 , NORTH, qup_l6, _, _, _, _, _, _, _, _),126 , NORTH, _, _, _, _, _, _, _, _, _),127 , WEST, _, _, _, _, _, _, _, _, _),128 , WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _),129 , WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _),130 , WEST, qlink_request, _, _, _, _, _, _, _, _),131 , WEST, qlink_enable, _, _, _, _, _, _, _, _),132 , WEST, _, _, _, _, _, _, _, _, _),133 , NORTH, _, _, _, _, _, _, _, _, _),134 , NORTH, _, _, _, _, _, _, _, _, _),135 , WEST, _, pa_indicator, _, _, _, _, _, _, _),136 , WEST, _, _, _, _, _, _, _, _, _),137 , WEST, _, _, phase_flag, _, _, _, _, _, _),138 , WEST, _, _, phase_flag, _, _, _, _, _, _),139 , WEST, _, phase_flag, _, _, _, _, _, _, _),140 , WEST, _, _, phase_flag, _, _, _, _, _, _),141 , WEST, _, phase_flag, _, _, _, _, _, _, _),142 , WEST, _, phase_flag, _, _, _, _, _, _, _),143 , WEST, _, nav_pps, nav_pps, gps_tx, phase_flag, _, _, _, _),144 , SOUTH, mss_lte, _, _, _, _, _, _, _, _),145 , SOUTH, mss_lte, gps_tx, _, _, _, _, _, _, _),146 , WEST, _, _, _, _, _, _, _, _, _),147 , WEST, _, _, _, _, _, _, _, _, _),148 , WEST, _, _, _, _, _, _, _, _, _),149 , WEST, _, _, _, _, _, _, _, _, _),0 x99d000),0 x99000, 15 , 0 ),0 x99000, 13 , 6 ),0 x99000, 11 , 3 ),0 x99000, 9 , 0 ),0 x9a000, 14 , 6 ),0 x9a000, 11 , 3 ),0 x9a000, 9 , 0 ),static const int sdm670_reserved_gpios[] = {58 , 59 , 60 , 61 , 62 , 63 , 64 , 69 , 70 , 71 , 72 , 73 , 74 , 104 , -1 static const struct msm_gpio_wakeirq_map sdm670_pdc_map[] = {1 , 30 }, { 3 , 31 }, { 5 , 32 }, { 10 , 33 }, { 11 , 34 },20 , 35 }, { 22 , 36 }, { 24 , 37 }, { 26 , 38 }, { 30 , 39 },31 , 117 }, { 32 , 41 }, { 34 , 42 }, { 36 , 43 }, { 37 , 44 },38 , 45 }, { 39 , 46 }, { 40 , 47 }, { 41 , 115 }, { 43 , 49 },44 , 50 }, { 46 , 51 }, { 48 , 52 }, { 49 , 118 }, { 52 , 54 },53 , 55 }, { 54 , 56 }, { 56 , 57 }, { 57 , 58 }, { 66 , 66 },68 , 67 }, { 77 , 70 }, { 78 , 71 }, { 79 , 72 }, { 80 , 73 },84 , 74 }, { 85 , 75 }, { 86 , 76 }, { 88 , 77 }, { 89 , 116 },91 , 79 }, { 92 , 80 }, { 95 , 81 }, { 96 , 82 }, { 97 , 83 },101 , 84 }, { 103 , 85 }, { 115 , 90 }, { 116 , 91 }, { 117 , 92 },118 , 93 }, { 119 , 94 }, { 120 , 95 }, { 121 , 96 }, { 122 , 97 },123 , 98 }, { 124 , 99 }, { 125 , 100 }, { 127 , 102 }, { 128 , 103 },129 , 104 }, { 130 , 105 }, { 132 , 106 }, { 133 , 107 }, { 145 , 108 },static const struct msm_pinctrl_soc_data sdm670_pinctrl = {151 ,true ,static int sdm670_pinctrl_probe(struct platform_device *pdev)return msm_pinctrl_probe(pdev, &sdm670_pinctrl);static const struct of_device_id sdm670_pinctrl_of_match[] = {"qcom,sdm670-tlmm" , },static struct platform_driver sdm670_pinctrl_driver = {"sdm670-pinctrl" ,static int __init sdm670_pinctrl_init(void )return platform_driver_register(&sdm670_pinctrl_driver);static void __exit sdm670_pinctrl_exit(void )"Qualcomm SDM670 TLMM pinctrl driver" );"GPL" );
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