/* SPDX-License-Identifier: GPL-2.0-or-later */ /*************************************************************************** * * Copyright (C) 2007-2010 SMSC * #ifndef _SMSC75XX_H#define _SMSC75XX_H/* Tx command words */ #define TX_CMD_A_LSO (0 x08000000)#define TX_CMD_A_IPE (0 x04000000)#define TX_CMD_A_TPE (0 x02000000)#define TX_CMD_A_IVTG (0 x01000000)#define TX_CMD_A_RVTG (0 x00800000)#define TX_CMD_A_FCS (0 x00400000)#define TX_CMD_A_LEN (0 x000FFFFF)#define TX_CMD_B_MSS (0 x3FFF0000)#define TX_CMD_B_MSS_SHIFT (16 )#define TX_MSS_MIN ((u16)8 )#define TX_CMD_B_VTAG (0 x0000FFFF)/* Rx command words */ #define RX_CMD_A_ICE (0 x80000000)#define RX_CMD_A_TCE (0 x40000000)#define RX_CMD_A_IPV (0 x20000000)#define RX_CMD_A_PID (0 x18000000)#define RX_CMD_A_PID_NIP (0 x00000000)#define RX_CMD_A_PID_TCP (0 x08000000)#define RX_CMD_A_PID_UDP (0 x10000000)#define RX_CMD_A_PID_PP (0 x18000000)#define RX_CMD_A_PFF (0 x04000000)#define RX_CMD_A_BAM (0 x02000000)#define RX_CMD_A_MAM (0 x01000000)#define RX_CMD_A_FVTG (0 x00800000)#define RX_CMD_A_RED (0 x00400000)#define RX_CMD_A_RWT (0 x00200000)#define RX_CMD_A_RUNT (0 x00100000)#define RX_CMD_A_LONG (0 x00080000)#define RX_CMD_A_RXE (0 x00040000)#define RX_CMD_A_DRB (0 x00020000)#define RX_CMD_A_FCS (0 x00010000)#define RX_CMD_A_UAM (0 x00008000)#define RX_CMD_A_LCSM (0 x00004000)#define RX_CMD_A_LEN (0 x00003FFF)#define RX_CMD_B_CSUM (0 xFFFF0000)#define RX_CMD_B_CSUM_SHIFT (16 )#define RX_CMD_B_VTAG (0 x0000FFFF)/* SCSRs */ #define ID_REV (0 x0000)#define FPGA_REV (0 x0004)#define BOND_CTL (0 x0008)#define INT_STS (0 x000C)#define INT_STS_RDFO_INT (0 x00400000)#define INT_STS_TXE_INT (0 x00200000)#define INT_STS_MACRTO_INT (0 x00100000)#define INT_STS_TX_DIS_INT (0 x00080000)#define INT_STS_RX_DIS_INT (0 x00040000)#define INT_STS_PHY_INT_ (0 x00020000)#define INT_STS_MAC_ERR_INT (0 x00008000)#define INT_STS_TDFU (0 x00004000)#define INT_STS_TDFO (0 x00002000)#define INT_STS_GPIOS (0 x00000FFF)#define INT_STS_CLEAR_ALL (0 xFFFFFFFF)#define HW_CFG (0 x0010)#define HW_CFG_SMDET_STS (0 x00008000)#define HW_CFG_SMDET_EN (0 x00004000)#define HW_CFG_EEM (0 x00002000)#define HW_CFG_RST_PROTECT (0 x00001000)#define HW_CFG_PORT_SWAP (0 x00000800)#define HW_CFG_PHY_BOOST (0 x00000600)#define HW_CFG_PHY_BOOST_NORMAL (0 x00000000)#define HW_CFG_PHY_BOOST_4 (0 x00002000)#define HW_CFG_PHY_BOOST_8 (0 x00004000)#define HW_CFG_PHY_BOOST_12 (0 x00006000)#define HW_CFG_LEDB (0 x00000100)#define HW_CFG_BIR (0 x00000080)#define HW_CFG_SBP (0 x00000040)#define HW_CFG_IME (0 x00000020)#define HW_CFG_MEF (0 x00000010)#define HW_CFG_ETC (0 x00000008)#define HW_CFG_BCE (0 x00000004)#define HW_CFG_LRST (0 x00000002)#define HW_CFG_SRST (0 x00000001)#define PMT_CTL (0 x0014)#define PMT_CTL_PHY_PWRUP (0 x00000400)#define PMT_CTL_RES_CLR_WKP_EN (0 x00000100)#define PMT_CTL_DEV_RDY (0 x00000080)#define PMT_CTL_SUS_MODE (0 x00000060)#define PMT_CTL_SUS_MODE_0 (0 x00000000)#define PMT_CTL_SUS_MODE_1 (0 x00000020)#define PMT_CTL_SUS_MODE_2 (0 x00000040)#define PMT_CTL_SUS_MODE_3 (0 x00000060)#define PMT_CTL_PHY_RST (0 x00000010)#define PMT_CTL_WOL_EN (0 x00000008)#define PMT_CTL_ED_EN (0 x00000004)#define PMT_CTL_WUPS (0 x00000003)#define PMT_CTL_WUPS_NO (0 x00000000)#define PMT_CTL_WUPS_ED (0 x00000001)#define PMT_CTL_WUPS_WOL (0 x00000002)#define PMT_CTL_WUPS_MULTI (0 x00000003)#define LED_GPIO_CFG (0 x0018)#define LED_GPIO_CFG_LED2_FUN_SEL (0 x80000000)#define LED_GPIO_CFG_LED10_FUN_SEL (0 x40000000)#define LED_GPIO_CFG_LEDGPIO_EN (0 x0000F000)#define LED_GPIO_CFG_LEDGPIO_EN_0 (0 x00001000)#define LED_GPIO_CFG_LEDGPIO_EN_1 (0 x00002000)#define LED_GPIO_CFG_LEDGPIO_EN_2 (0 x00004000)#define LED_GPIO_CFG_LEDGPIO_EN_3 (0 x00008000)#define LED_GPIO_CFG_GPBUF (0 x00000F00)#define LED_GPIO_CFG_GPBUF_0 (0 x00000100)#define LED_GPIO_CFG_GPBUF_1 (0 x00000200)#define LED_GPIO_CFG_GPBUF_2 (0 x00000400)#define LED_GPIO_CFG_GPBUF_3 (0 x00000800)#define LED_GPIO_CFG_GPDIR (0 x000000F0)#define LED_GPIO_CFG_GPDIR_0 (0 x00000010)#define LED_GPIO_CFG_GPDIR_1 (0 x00000020)#define LED_GPIO_CFG_GPDIR_2 (0 x00000040)#define LED_GPIO_CFG_GPDIR_3 (0 x00000080)#define LED_GPIO_CFG_GPDATA (0 x0000000F)#define LED_GPIO_CFG_GPDATA_0 (0 x00000001)#define LED_GPIO_CFG_GPDATA_1 (0 x00000002)#define LED_GPIO_CFG_GPDATA_2 (0 x00000004)#define LED_GPIO_CFG_GPDATA_3 (0 x00000008)#define GPIO_CFG (0 x001C)#define GPIO_CFG_SHIFT (24 )#define GPIO_CFG_GPEN (0 xFF000000)#define GPIO_CFG_GPBUF (0 x00FF0000)#define GPIO_CFG_GPDIR (0 x0000FF00)#define GPIO_CFG_GPDATA (0 x000000FF)#define GPIO_WAKE (0 x0020)#define GPIO_WAKE_PHY_LINKUP_EN (0 x80000000)#define GPIO_WAKE_POL (0 x0FFF0000)#define GPIO_WAKE_POL_SHIFT (16 )#define GPIO_WAKE_WK (0 x00000FFF)#define DP_SEL (0 x0024)#define DP_SEL_DPRDY (0 x80000000)#define DP_SEL_RSEL (0 x0000000F)#define DP_SEL_URX (0 x00000000)#define DP_SEL_VHF (0 x00000001)#define DP_SEL_VHF_HASH_LEN (16 )#define DP_SEL_VHF_VLAN_LEN (128 )#define DP_SEL_LSO_HEAD (0 x00000002)#define DP_SEL_FCT_RX (0 x00000003)#define DP_SEL_FCT_TX (0 x00000004)#define DP_SEL_DESCRIPTOR (0 x00000005)#define DP_SEL_WOL (0 x00000006)#define DP_CMD (0 x0028)#define DP_CMD_WRITE (0 x01)#define DP_CMD_READ (0 x00)#define DP_ADDR (0 x002C)#define DP_DATA (0 x0030)#define BURST_CAP (0 x0034)#define BURST_CAP_MASK (0 x0000000F)#define INT_EP_CTL (0 x0038)#define INT_EP_CTL_INTEP_ON (0 x80000000)#define INT_EP_CTL_RDFO_EN (0 x00400000)#define INT_EP_CTL_TXE_EN (0 x00200000)#define INT_EP_CTL_MACROTO_EN (0 x00100000)#define INT_EP_CTL_TX_DIS_EN (0 x00080000)#define INT_EP_CTL_RX_DIS_EN (0 x00040000)#define INT_EP_CTL_PHY_EN_ (0 x00020000)#define INT_EP_CTL_MAC_ERR_EN (0 x00008000)#define INT_EP_CTL_TDFU_EN (0 x00004000)#define INT_EP_CTL_TDFO_EN (0 x00002000)#define INT_EP_CTL_RX_FIFO_EN (0 x00001000)#define INT_EP_CTL_GPIOX_EN (0 x00000FFF)#define BULK_IN_DLY (0 x003C)#define BULK_IN_DLY_MASK (0 xFFFF)#define E2P_CMD (0 x0040)#define E2P_CMD_BUSY (0 x80000000)#define E2P_CMD_MASK (0 x70000000)#define E2P_CMD_READ (0 x00000000)#define E2P_CMD_EWDS (0 x10000000)#define E2P_CMD_EWEN (0 x20000000)#define E2P_CMD_WRITE (0 x30000000)#define E2P_CMD_WRAL (0 x40000000)#define E2P_CMD_ERASE (0 x50000000)#define E2P_CMD_ERAL (0 x60000000)#define E2P_CMD_RELOAD (0 x70000000)#define E2P_CMD_TIMEOUT (0 x00000400)#define E2P_CMD_LOADED (0 x00000200)#define E2P_CMD_ADDR (0 x000001FF)#define MAX_EEPROM_SIZE (512 )#define E2P_DATA (0 x0044)#define E2P_DATA_MASK_ (0 x000000FF)#define RFE_CTL (0 x0060)#define RFE_CTL_TCPUDP_CKM (0 x00001000)#define RFE_CTL_IP_CKM (0 x00000800)#define RFE_CTL_AB (0 x00000400)#define RFE_CTL_AM (0 x00000200)#define RFE_CTL_AU (0 x00000100)#define RFE_CTL_VS (0 x00000080)#define RFE_CTL_UF (0 x00000040)#define RFE_CTL_VF (0 x00000020)#define RFE_CTL_SPF (0 x00000010)#define RFE_CTL_MHF (0 x00000008)#define RFE_CTL_DHF (0 x00000004)#define RFE_CTL_DPF (0 x00000002)#define RFE_CTL_RST_RF (0 x00000001)#define VLAN_TYPE (0 x0064)#define VLAN_TYPE_MASK (0 x0000FFFF)#define FCT_RX_CTL (0 x0090)#define FCT_RX_CTL_EN (0 x80000000)#define FCT_RX_CTL_RST (0 x40000000)#define FCT_RX_CTL_SBF (0 x02000000)#define FCT_RX_CTL_OVERFLOW (0 x01000000)#define FCT_RX_CTL_FRM_DROP (0 x00800000)#define FCT_RX_CTL_RX_NOT_EMPTY (0 x00400000)#define FCT_RX_CTL_RX_EMPTY (0 x00200000)#define FCT_RX_CTL_RX_DISABLED (0 x00100000)#define FCT_RX_CTL_RXUSED (0 x0000FFFF)#define FCT_TX_CTL (0 x0094)#define FCT_TX_CTL_EN (0 x80000000)#define FCT_TX_CTL_RST (0 x40000000)#define FCT_TX_CTL_TX_NOT_EMPTY (0 x00400000)#define FCT_TX_CTL_TX_EMPTY (0 x00200000)#define FCT_TX_CTL_TX_DISABLED (0 x00100000)#define FCT_TX_CTL_TXUSED (0 x0000FFFF)#define FCT_RX_FIFO_END (0 x0098)#define FCT_RX_FIFO_END_MASK (0 x0000007F)#define FCT_TX_FIFO_END (0 x009C)#define FCT_TX_FIFO_END_MASK (0 x0000003F)#define FCT_FLOW (0 x00A0)#define FCT_FLOW_THRESHOLD_OFF (0 x00007F00)#define FCT_FLOW_THRESHOLD_OFF_SHIFT (8 )#define FCT_FLOW_THRESHOLD_ON (0 x0000007F)/* MAC CSRs */ #define MAC_CR (0 x100)#define MAC_CR_ADP (0 x00002000)#define MAC_CR_ADD (0 x00001000)#define MAC_CR_ASD (0 x00000800)#define MAC_CR_INT_LOOP (0 x00000400)#define MAC_CR_BOLMT (0 x000000C0)#define MAC_CR_FDPX (0 x00000008)#define MAC_CR_CFG (0 x00000006)#define MAC_CR_CFG_10 (0 x00000000)#define MAC_CR_CFG_100 (0 x00000002)#define MAC_CR_CFG_1000 (0 x00000004)#define MAC_CR_RST (0 x00000001)#define MAC_RX (0 x104)#define MAC_RX_MAX_SIZE (0 x3FFF0000)#define MAC_RX_MAX_SIZE_SHIFT (16 )#define MAC_RX_FCS_STRIP (0 x00000010)#define MAC_RX_FSE (0 x00000004)#define MAC_RX_RXD (0 x00000002)#define MAC_RX_RXEN (0 x00000001)#define MAC_TX (0 x108)#define MAC_TX_BFCS (0 x00000004)#define MAC_TX_TXD (0 x00000002)#define MAC_TX_TXEN (0 x00000001)#define FLOW (0 x10C)#define FLOW_FORCE_FC (0 x80000000)#define FLOW_TX_FCEN (0 x40000000)#define FLOW_RX_FCEN (0 x20000000)#define FLOW_FPF (0 x10000000)#define FLOW_PAUSE_TIME (0 x0000FFFF)#define RAND_SEED (0 x110)#define RAND_SEED_MASK (0 x0000FFFF)#define ERR_STS (0 x114)#define ERR_STS_FCS_ERR (0 x00000100)#define ERR_STS_LFRM_ERR (0 x00000080)#define ERR_STS_RUNT_ERR (0 x00000040)#define ERR_STS_COLLISION_ERR (0 x00000010)#define ERR_STS_ALIGN_ERR (0 x00000008)#define ERR_STS_URUN_ERR (0 x00000004)#define RX_ADDRH (0 x118)#define RX_ADDRH_MASK (0 x0000FFFF)#define RX_ADDRL (0 x11C)#define MII_ACCESS (0 x120)#define MII_ACCESS_PHY_ADDR (0 x0000F800)#define MII_ACCESS_PHY_ADDR_SHIFT (11 )#define MII_ACCESS_REG_ADDR (0 x000007C0)#define MII_ACCESS_REG_ADDR_SHIFT (6 )#define MII_ACCESS_READ (0 x00000000)#define MII_ACCESS_WRITE (0 x00000002)#define MII_ACCESS_BUSY (0 x00000001)#define MII_DATA (0 x124)#define MII_DATA_MASK (0 x0000FFFF)#define WUCSR (0 x140)#define WUCSR_PFDA_FR (0 x00000080)#define WUCSR_WUFR (0 x00000040)#define WUCSR_MPR (0 x00000020)#define WUCSR_BCAST_FR (0 x00000010)#define WUCSR_PFDA_EN (0 x00000008)#define WUCSR_WUEN (0 x00000004)#define WUCSR_MPEN (0 x00000002)#define WUCSR_BCST_EN (0 x00000001)#define WUF_CFGX (0 x144)#define WUF_CFGX_EN (0 x80000000)#define WUF_CFGX_ATYPE (0 x03000000)#define WUF_CFGX_ATYPE_UNICAST (0 x00000000)#define WUF_CFGX_ATYPE_MULTICAST (0 x02000000)#define WUF_CFGX_ATYPE_ALL (0 x03000000)#define WUF_CFGX_PATTERN_OFFSET (0 x007F0000)#define WUF_CFGX_PATTERN_OFFSET_SHIFT (16 )#define WUF_CFGX_CRC16 (0 x0000FFFF)#define WUF_NUM (8 )#define WUF_MASKX (0 x170)#define WUF_MASKX_AVALID (0 x80000000)#define WUF_MASKX_ATYPE (0 x40000000)#define ADDR_FILTX (0 x300)#define ADDR_FILTX_FB_VALID (0 x80000000)#define ADDR_FILTX_FB_TYPE (0 x40000000)#define ADDR_FILTX_FB_ADDRHI (0 x0000FFFF)#define ADDR_FILTX_SB_ADDRLO (0 xFFFFFFFF)#define WUCSR2 (0 x500)#define WUCSR2_NS_RCD (0 x00000040)#define WUCSR2_ARP_RCD (0 x00000020)#define WUCSR2_TCPSYN_RCD (0 x00000010)#define WUCSR2_NS_OFFLOAD (0 x00000004)#define WUCSR2_ARP_OFFLOAD (0 x00000002)#define WUCSR2_TCPSYN_OFFLOAD (0 x00000001)#define WOL_FIFO_STS (0 x504)#define IPV6_ADDRX (0 x510)#define IPV4_ADDRX (0 x590)/* Vendor-specific PHY Definitions */ /* Mode Control/Status Register */ #define PHY_MODE_CTRL_STS (17 )#define MODE_CTRL_STS_EDPWRDOWN ((u16)0 x2000)#define MODE_CTRL_STS_ENERGYON ((u16)0 x0002)#define PHY_INT_SRC (29 )#define PHY_INT_SRC_ENERGY_ON ((u16)0 x0080)#define PHY_INT_SRC_ANEG_COMP ((u16)0 x0040)#define PHY_INT_SRC_REMOTE_FAULT ((u16)0 x0020)#define PHY_INT_SRC_LINK_DOWN ((u16)0 x0010)#define PHY_INT_SRC_CLEAR_ALL ((u16)0 xffff)#define PHY_INT_MASK (30 )#define PHY_INT_MASK_ENERGY_ON ((u16)0 x0080)#define PHY_INT_MASK_ANEG_COMP ((u16)0 x0040)#define PHY_INT_MASK_REMOTE_FAULT ((u16)0 x0020)#define PHY_INT_MASK_LINK_DOWN ((u16)0 x0010)#define PHY_INT_MASK_DEFAULT (PHY_INT_MASK_ANEG_COMP | \#define PHY_SPECIAL (31 )#define PHY_SPECIAL_SPD ((u16)0 x001C)#define PHY_SPECIAL_SPD_10HALF ((u16)0 x0004)#define PHY_SPECIAL_SPD_10FULL ((u16)0 x0014)#define PHY_SPECIAL_SPD_100HALF ((u16)0 x0008)#define PHY_SPECIAL_SPD_100FULL ((u16)0 x0018)/* USB Vendor Requests */ #define USB_VENDOR_REQUEST_WRITE_REGISTER 0 xA0#define USB_VENDOR_REQUEST_READ_REGISTER 0 xA1#define USB_VENDOR_REQUEST_GET_STATS 0 xA2/* Interrupt Endpoint status word bitfields */ #define INT_ENP_RDFO_INT ((u32)BIT(22 ))#define INT_ENP_TXE_INT ((u32)BIT(21 ))#define INT_ENP_TX_DIS_INT ((u32)BIT(19 ))#define INT_ENP_RX_DIS_INT ((u32)BIT(18 ))#define INT_ENP_PHY_INT ((u32)BIT(17 ))#define INT_ENP_MAC_ERR_INT ((u32)BIT(15 ))#define INT_ENP_RX_FIFO_DATA_INT ((u32)BIT(12 ))#endif /* _SMSC75XX_H */
Messung V0.5 in Prozent C=96 H=91 G=93
¤ Dauer der Verarbeitung: 0.7 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
