// SPDX-License-Identifier: GPL-2.0 /* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */ #include <linux/pcs/pcs-xpcs.h>#include <linux/mdio.h>#include "pcs-xpcs.h" /* VR_XS_PMA_MMD */ #define TXGBE_PMA_MMD 0 x8020#define TXGBE_TX_GENCTL1 0 x11#define TXGBE_TX_GENCTL1_VBOOST_LVL GENMASK(10 , 8 )#define TXGBE_TX_GENCTL1_VBOOST_EN0 BIT(4 )#define TXGBE_TX_GEN_CTL2 0 x12#define TXGBE_TX_GEN_CTL2_TX0_WIDTH(v) FIELD_PREP(GENMASK(9 , 8 ), v)#define TXGBE_TX_RATE_CTL 0 x14#define TXGBE_TX_RATE_CTL_TX0_RATE(v) FIELD_PREP(GENMASK(2 , 0 ), v)#define TXGBE_RX_GEN_CTL2 0 x32#define TXGBE_RX_GEN_CTL2_RX0_WIDTH(v) FIELD_PREP(GENMASK(9 , 8 ), v)#define TXGBE_RX_GEN_CTL3 0 x33#define TXGBE_RX_GEN_CTL3_LOS_TRSHLD0 GENMASK(2 , 0 )#define TXGBE_RX_RATE_CTL 0 x34#define TXGBE_RX_RATE_CTL_RX0_RATE(v) FIELD_PREP(GENMASK(1 , 0 ), v)#define TXGBE_RX_EQ_ATTN_CTL 0 x37#define TXGBE_RX_EQ_ATTN_LVL0 GENMASK(2 , 0 )#define TXGBE_RX_EQ_CTL0 0 x38#define TXGBE_RX_EQ_CTL0_VGA1_GAIN(v) FIELD_PREP(GENMASK(15 , 12 ), v)#define TXGBE_RX_EQ_CTL0_VGA2_GAIN(v) FIELD_PREP(GENMASK(11 , 8 ), v)#define TXGBE_RX_EQ_CTL0_CTLE_POLE(v) FIELD_PREP(GENMASK(7 , 5 ), v)#define TXGBE_RX_EQ_CTL0_CTLE_BOOST(v) FIELD_PREP(GENMASK(4 , 0 ), v)#define TXGBE_RX_EQ_CTL4 0 x3C#define TXGBE_RX_EQ_CTL4_CONT_OFF_CAN0 BIT(4 )#define TXGBE_RX_EQ_CTL4_CONT_ADAPT0 BIT(0 )#define TXGBE_AFE_DFE_ENABLE 0 x3D#define TXGBE_DFE_EN_0 BIT(4 )#define TXGBE_AFE_EN_0 BIT(0 )#define TXGBE_DFE_TAP_CTL0 0 x3E#define TXGBE_MPLLA_CTL0 0 x51#define TXGBE_MPLLA_CTL2 0 x53#define TXGBE_MPLLA_CTL2_DIV16P5_CLK_EN BIT(10 )#define TXGBE_MPLLA_CTL2_DIV10_CLK_EN BIT(9 )#define TXGBE_MPLLA_CTL3 0 x57#define TXGBE_MISC_CTL0 0 x70#define TXGBE_MISC_CTL0_PLL BIT(15 )#define TXGBE_MISC_CTL0_CR_PARA_SEL BIT(14 )#define TXGBE_MISC_CTL0_RX_VREF(v) FIELD_PREP(GENMASK(12 , 8 ), v)#define TXGBE_VCO_CAL_LD0 0 x72#define TXGBE_VCO_CAL_REF0 0 x76static int txgbe_write_pma(struct dw_xpcs *xpcs, int reg, u16 val)return xpcs_write(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg, val);static int txgbe_modify_pma(struct dw_xpcs *xpcs, int reg, u16 mask, u16 set)return xpcs_modify(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg, mask,static void txgbe_pma_config_10gbaser(struct dw_xpcs *xpcs)0 x21);0 );0 x5));0 xF));0 x549);0 x29);0 );0 );3 ));3 ));2 ) |5 ));0 );0 xBE);0 );0 );static void txgbe_pma_config_1g(struct dw_xpcs *xpcs)0 x5));0 xF));7 ) |7 ) | TXGBE_RX_EQ_CTL0_CTLE_BOOST(6 ));0 );0 );0 x4));0 x20);0 x46);0 x540);0 x2A);0 );3 ));3 ));1 ));1 ));static int txgbe_pcs_poll_power_up(struct dw_xpcs *xpcs)int val, ret;/* Wait xpcs power-up good */ 10000 , 1000000 , false ,if (ret < 0 )"xpcs power-up timeout\n" );return ret;static int txgbe_pma_init_done(struct dw_xpcs *xpcs)int val, ret;/* wait pma initialization done */ 100000 , 10000000 , false ,if (ret < 0 )"xpcs pma initialization timeout\n" );return ret;static bool txgbe_xpcs_mode_quirk(struct dw_xpcs *xpcs)int ret;/* When txgbe do LAN reset, PCS will change to default 10GBASE-R mode */ if ((ret == MDIO_PCS_CTRL2_10GBR &&return true ;return false ;int txgbe_xpcs_switch_mode(struct dw_xpcs *xpcs, phy_interface_t interface)int ret;switch (interface) {case PHY_INTERFACE_MODE_10GBASER:case PHY_INTERFACE_MODE_SGMII:case PHY_INTERFACE_MODE_1000BASEX:break ;default :return 0 ;if (xpcs->interface == interface && !txgbe_xpcs_mode_quirk(xpcs))return 0 ;if (ret < 0 )return ret;if (interface == PHY_INTERFACE_MODE_10GBASER) {else {0 );0 );return txgbe_pma_init_done(xpcs);
Messung V0.5 in Prozent C=91 H=91 G=90
¤ Dauer der Verarbeitung: 0.12 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
