// SPDX-License-Identifier: GPL-2.0-or-later /* * smc91x.c * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices. * * Copyright (C) 1996 by Erik Stahlman * Copyright (C) 2001 Standard Microsystems Corporation * Developed by Simple Network Magic Corporation * Copyright (C) 2003 Monta Vista Software, Inc. * Unified SMC91x driver by Nicolas Pitre * * Arguments: * io = for the base address * irq = for the IRQ * nowait = 0 for normal wait states, 1 eliminates additional wait states * * original author: * Erik Stahlman <erik@vt.edu> * * hardware multicast code: * Peter Cammaert <pc@denkart.be> * * contributors: * Daris A Nevil <dnevil@snmc.com> * Nicolas Pitre <nico@fluxnic.net> * Russell King <rmk@arm.linux.org.uk> * * History: * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ" * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111 * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111 * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111 * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races, * more bus abstraction, big cleanup, etc. * 29/09/03 Russell King - add driver model support * - ethtool support * - convert to use generic MII interface * - add link up/down notification * - don't try to handle full negotiation in * smc_phy_configure * - clean up (and fix stack overrun) in PHY * MII read/write functions * 22/09/04 Nicolas Pitre big update (see commit log for details)
*/ staticconstchar version[] = "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre ";
/* * The internal workings of the driver. If you are changing anything * here with the SMC stuff, you should have the datasheet and know * what you are doing.
*/ #define CARDNAME "smc91x"
/* * Use power-down feature of the chip
*/ #define POWER_DOWN 1
/* * Wait time for memory to be free. This probably shouldn't be * tuned that much, as waiting for this means nothing else happens * in the system
*/ #define MEMORY_WAIT_TIME 16
/* * The maximum number of processing loops allowed for each call to the * IRQ handler.
*/ #define MAX_IRQ_LOOPS 8
/* * This selects whether TX packets are sent one by one to the SMC91x internal * memory and throttled until transmission completes. This may prevent * RX overruns a litle by keeping much of the memory free for RX packets * but to the expense of reduced TX throughput and increased IRQ overhead. * Note this is not a cure for a too slow data bus or too high IRQ latency.
*/ #define THROTTLE_TX_PKTS 0
/* * The MII clock high/low times. 2x this number gives the MII clock period * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!)
*/ #define MII_DELAY 1
#define DBG(n, dev, fmt, ...) \ do { \ if (SMC_DEBUG >= (n)) \
netdev_dbg(dev, fmt, ##__VA_ARGS__); \
} while (0)
#define PRINTK(dev, fmt, ...) \ do { \ if (SMC_DEBUG > 0) \
netdev_info(dev, fmt, ##__VA_ARGS__); \ else \
netdev_dbg(dev, fmt, ##__VA_ARGS__); \
} while (0)
#if SMC_DEBUG > 3 staticvoid PRINT_PKT(u_char *buf, int length)
{ int i; int remainder; int lines;
lines = length / 16;
remainder = length % 16;
for (i = 0; i < lines ; i ++) { int cur;
printk(KERN_DEBUG); for (cur = 0; cur < 8; cur++) {
u_char a, b;
a = *buf++;
b = *buf++;
pr_cont("%02x%02x ", a, b);
}
pr_cont("\n");
}
printk(KERN_DEBUG); for (i = 0; i < remainder/2 ; i++) {
u_char a, b;
a = *buf++;
b = *buf++;
pr_cont("%02x%02x ", a, b);
}
pr_cont("\n");
} #else staticinlinevoid PRINT_PKT(u_char *buf, int length) { } #endif
/* this enables an interrupt in the interrupt mask register */ #define SMC_ENABLE_INT(lp, x) do { \ unsignedchar mask; \ unsignedlong smc_enable_flags; \
spin_lock_irqsave(&lp->lock, smc_enable_flags); \
mask = SMC_GET_INT_MASK(lp); \
mask |= (x); \
SMC_SET_INT_MASK(lp, mask); \
spin_unlock_irqrestore(&lp->lock, smc_enable_flags); \
} while (0)
/* this disables an interrupt from the interrupt mask register */ #define SMC_DISABLE_INT(lp, x) do { \ unsignedchar mask; \ unsignedlong smc_disable_flags; \
spin_lock_irqsave(&lp->lock, smc_disable_flags); \
mask = SMC_GET_INT_MASK(lp); \
mask &= ~(x); \
SMC_SET_INT_MASK(lp, mask); \
spin_unlock_irqrestore(&lp->lock, smc_disable_flags); \
} while (0)
/* * Wait while MMU is busy. This is usually in the order of a few nanosecs * if at all, but let's avoid deadlocking the system if the hardware * decides to go south.
*/ #define SMC_WAIT_MMU_BUSY(lp) do { \ if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \ unsignedlong timeout = jiffies + 2; \ while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \ if (time_after(jiffies, timeout)) { \
netdev_dbg(dev, "timeout %s line %d\n", \
__FILE__, __LINE__); \ break; \
} \
cpu_relax(); \
} \
} \
} while (0)
/* * this does a soft reset on the device
*/ staticvoid smc_reset(struct net_device *dev)
{ struct smc_local *lp = netdev_priv(dev); void __iomem *ioaddr = lp->base; unsignedint ctl, cfg; struct sk_buff *pending_skb;
/* free any pending tx skb */ if (pending_skb) {
dev_kfree_skb(pending_skb);
dev->stats.tx_errors++;
dev->stats.tx_aborted_errors++;
}
/* * This resets the registers mostly to defaults, but doesn't * affect EEPROM. That seems unnecessary
*/
SMC_SELECT_BANK(lp, 0);
SMC_SET_RCR(lp, RCR_SOFTRST);
/* * Setup the Configuration Register * This is necessary because the CONFIG_REG is not affected * by a soft reset
*/
SMC_SELECT_BANK(lp, 1);
cfg = CONFIG_DEFAULT;
/* * Setup for fast accesses if requested. If the card/system * can't handle it then there will be no recovery except for * a hard reset or power cycle
*/ if (lp->cfg.flags & SMC91X_NOWAIT)
cfg |= CONFIG_NO_WAIT;
/* * Release from possible power-down state * Configuration register is not affected by Soft Reset
*/
cfg |= CONFIG_EPH_POWER_EN;
SMC_SET_CONFIG(lp, cfg);
/* this should pause enough for the chip to be happy */ /* * elaborate? What does the chip _need_? --jgarzik * * This seems to be undocumented, but something the original * driver(s) have always done. Suspect undocumented timing * info/determined empirically. --rmk
*/
udelay(1);
/* * Set the control register to automatically release successfully * transmitted packets, to make the best use out of our limited * memory
*/ if(!THROTTLE_TX_PKTS)
ctl |= CTL_AUTO_RELEASE; else
ctl &= ~CTL_AUTO_RELEASE;
SMC_SET_CTL(lp, ctl);
/* * From this point the register bank must _NOT_ be switched away * to something else than bank 2 without proper locking against * races with any tasklet or interrupt handlers until smc_shutdown() * or smc_reset() is called.
*/
}
/* * this puts the device in an inactive state
*/ staticvoid smc_shutdown(struct net_device *dev)
{ struct smc_local *lp = netdev_priv(dev); void __iomem *ioaddr = lp->base; struct sk_buff *pending_skb;
DBG(2, dev, "%s: %s\n", CARDNAME, __func__);
/* no more interrupts for me */
spin_lock_irq(&lp->lock);
SMC_SELECT_BANK(lp, 2);
SMC_SET_INT_MASK(lp, 0);
pending_skb = lp->pending_tx_skb;
lp->pending_tx_skb = NULL;
spin_unlock_irq(&lp->lock);
dev_kfree_skb(pending_skb);
/* and tell the card to stay away from that nasty outside world */
SMC_SELECT_BANK(lp, 0);
SMC_SET_RCR(lp, RCR_CLEAR);
SMC_SET_TCR(lp, TCR_CLEAR);
#ifdef POWER_DOWN /* finally, shut the chip down */
SMC_SELECT_BANK(lp, 1);
SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN); #endif
}
/* * This is the procedure to handle the receipt of a packet.
*/ staticinlinevoid smc_rcv(struct net_device *dev)
{ struct smc_local *lp = netdev_priv(dev); void __iomem *ioaddr = lp->base; unsignedint packet_number, status, packet_len;
DBG(3, dev, "%s\n", __func__);
packet_number = SMC_GET_RXFIFO(lp); if (unlikely(packet_number & RXFIFO_REMPTY)) {
PRINTK(dev, "smc_rcv with nothing on FIFO.\n"); return;
}
/* read from start of packet */
SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC);
/* First two words are status and packet length */
SMC_GET_PKT_HDR(lp, status, packet_len);
packet_len &= 0x07ff; /* mask off top bits */
DBG(2, dev, "RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n",
packet_number, status, packet_len, packet_len);
back: if (unlikely(packet_len < 6 || status & RS_ERRORS)) { if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) { /* accept VLAN packets */
status &= ~RS_TOOLONG; goto back;
} if (packet_len < 6) { /* bloody hardware */
netdev_err(dev, "fubar (rxlen %u status %x\n",
packet_len, status);
status |= RS_TOOSHORT;
}
SMC_WAIT_MMU_BUSY(lp);
SMC_SET_MMU_CMD(lp, MC_RELEASE);
dev->stats.rx_errors++; if (status & RS_ALGNERR)
dev->stats.rx_frame_errors++; if (status & (RS_TOOSHORT | RS_TOOLONG))
dev->stats.rx_length_errors++; if (status & RS_BADCRC)
dev->stats.rx_crc_errors++;
} else { struct sk_buff *skb; unsignedchar *data; unsignedint data_len;
/* set multicast stats */ if (status & RS_MULTICAST)
dev->stats.multicast++;
/* * Actual payload is packet_len - 6 (or 5 if odd byte). * We want skb_reserve(2) and the final ctrl word * (2 bytes, possibly containing the payload odd byte). * Furthermore, we add 2 bytes to allow rounding up to * multiple of 4 bytes on 32 bit buses. * Hence packet_len - 6 + 2 + 2 + 2.
*/
skb = netdev_alloc_skb(dev, packet_len); if (unlikely(skb == NULL)) {
SMC_WAIT_MMU_BUSY(lp);
SMC_SET_MMU_CMD(lp, MC_RELEASE);
dev->stats.rx_dropped++; return;
}
/* Align IP header to 32 bits */
skb_reserve(skb, 2);
/* BUG: the LAN91C111 rev A never sets this bit. Force it. */ if (lp->version == 0x90)
status |= RS_ODDFRAME;
#ifdef CONFIG_SMP /* * On SMP we have the following problem: * * A = smc_hardware_send_pkt() * B = smc_hard_start_xmit() * C = smc_interrupt() * * A and B can never be executed simultaneously. However, at least on UP, * it is possible (and even desirable) for C to interrupt execution of * A or B in order to have better RX reliability and avoid overruns. * C, just like A and B, must have exclusive access to the chip and * each of them must lock against any other concurrent access. * Unfortunately this is not possible to have C suspend execution of A or * B taking place on another CPU. On UP this is no an issue since A and B * are run from softirq context and C from hard IRQ context, and there is * no other CPU where concurrent access can happen. * If ever there is a way to force at least B and C to always be executed * on the same CPU then we could use read/write locks to protect against * any other concurrent access and C would always interrupt B. But life * isn't that easy in a SMP world...
*/ #define smc_special_trylock(lock, flags) \
({ \ int __ret; \
local_irq_save(flags); \
__ret = spin_trylock(lock); \ if (!__ret) \
local_irq_restore(flags); \
__ret; \
}) #define smc_special_lock(lock, flags) spin_lock_irqsave(lock, flags) #define smc_special_unlock(lock, flags) spin_unlock_irqrestore(lock, flags) #else #define smc_special_trylock(lock, flags) ((void)flags, true) #define smc_special_lock(lock, flags) do { flags = 0; } while (0) #define smc_special_unlock(lock, flags) do { flags = 0; } while (0) #endif
/* * This is called to actually send a packet to the chip.
*/ staticvoid smc_hardware_send_pkt(struct tasklet_struct *t)
{ struct smc_local *lp = from_tasklet(lp, t, tx_task); struct net_device *dev = lp->dev; void __iomem *ioaddr = lp->base; struct sk_buff *skb; unsignedint packet_no, len; unsignedchar *buf; unsignedlong flags;
DBG(3, dev, "%s\n", __func__);
if (!smc_special_trylock(&lp->lock, flags)) {
netif_stop_queue(dev);
tasklet_schedule(&lp->tx_task); return;
}
/* * Send the packet length (+6 for status words, length, and ctl. * The card will pad to 64 bytes with zeroes if packet is too small.
*/
SMC_PUT_PKT_HDR(lp, 0, len + 6);
/* send the actual data */
SMC_PUSH_DATA(lp, buf, len & ~1);
/* Send final ctl word with the last byte if there is one */
SMC_outw(lp, ((len & 1) ? (0x2000 | buf[len - 1]) : 0), ioaddr,
DATA_REG(lp));
/* * If THROTTLE_TX_PKTS is set, we stop the queue here. This will * have the effect of having at most one packet queued for TX * in the chip's memory at all time. * * If THROTTLE_TX_PKTS is not set then the queue is stopped only * when memory allocation (MC_ALLOC) does not succeed right away.
*/ if (THROTTLE_TX_PKTS)
netif_stop_queue(dev);
/* queue the packet for TX */
SMC_SET_MMU_CMD(lp, MC_ENQUEUE);
smc_special_unlock(&lp->lock, flags);
done: if (!THROTTLE_TX_PKTS)
netif_wake_queue(dev);
dev_consume_skb_any(skb);
}
/* * Since I am not sure if I will have enough room in the chip's ram * to store the packet, I call this routine which either sends it * now, or set the card to generates an interrupt when ready * for the packet.
*/ static netdev_tx_t
smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
{ struct smc_local *lp = netdev_priv(dev); void __iomem *ioaddr = lp->base; unsignedint numPages, poll_count, status; unsignedlong flags;
DBG(3, dev, "%s\n", __func__);
BUG_ON(lp->pending_tx_skb != NULL);
/* * The MMU wants the number of pages to be the number of 256 bytes * 'pages', minus 1 (since a packet can't ever have 0 pages :)) * * The 91C111 ignores the size bits, but earlier models don't. * * Pkt size for allocating is data length +6 (for additional status * words, length and ctl) * * If odd size then last byte is included in ctl word.
*/
numPages = ((skb->len & ~1) + (6 - 1)) >> 8; if (unlikely(numPages > 7)) {
netdev_warn(dev, "Far too big packet error.\n");
dev->stats.tx_errors++;
dev->stats.tx_dropped++;
dev_kfree_skb_any(skb); return NETDEV_TX_OK;
}
smc_special_lock(&lp->lock, flags);
/* now, try to allocate the memory */
SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages);
/* * Poll the chip for a short amount of time in case the * allocation succeeds quickly.
*/
poll_count = MEMORY_WAIT_TIME; do {
status = SMC_GET_INT(lp); if (status & IM_ALLOC_INT) {
SMC_ACK_INT(lp, IM_ALLOC_INT); break;
}
} while (--poll_count);
smc_special_unlock(&lp->lock, flags);
lp->pending_tx_skb = skb; if (!poll_count) { /* oh well, wait until the chip finds memory later */
netif_stop_queue(dev);
DBG(2, dev, "TX memory allocation deferred.\n");
SMC_ENABLE_INT(lp, IM_ALLOC_INT);
} else { /* * Allocation succeeded: push packet to the chip's own memory * immediately.
*/
smc_hardware_send_pkt(&lp->tx_task);
}
return NETDEV_TX_OK;
}
/* * This handles a TX interrupt, which is only called when: * - a TX error occurred, or * - CTL_AUTO_RELEASE is not set and TX of a packet completed.
*/ staticvoid smc_tx(struct net_device *dev)
{ struct smc_local *lp = netdev_priv(dev); void __iomem *ioaddr = lp->base; unsignedint saved_packet, packet_no, tx_status; unsignedint pkt_len __always_unused;
DBG(3, dev, "%s\n", __func__);
/* If the TX FIFO is empty then nothing to do */
packet_no = SMC_GET_TXFIFO(lp); if (unlikely(packet_no & TXFIFO_TEMPTY)) {
PRINTK(dev, "smc_tx with nothing on FIFO.\n"); return;
}
/* select packet to read from */
saved_packet = SMC_GET_PN(lp);
SMC_SET_PN(lp, packet_no);
/* read the first word (status word) from this packet */
SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ);
SMC_GET_PKT_HDR(lp, tx_status, pkt_len);
DBG(2, dev, "TX STATUS 0x%04x PNR 0x%02x\n",
tx_status, packet_no);
if (!(tx_status & ES_TX_SUC))
dev->stats.tx_errors++;
if (tx_status & ES_LOSTCARR)
dev->stats.tx_carrier_errors++;
if (tx_status & (ES_LATCOL | ES_16COL)) {
PRINTK(dev, "%s occurred on last xmit\n",
(tx_status & ES_LATCOL) ? "late collision" : "too many collisions");
dev->stats.tx_window_errors++; if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) {
netdev_info(dev, "unexpectedly large number of bad collisions. Please check duplex setting.\n");
}
}
/* kill the packet */
SMC_WAIT_MMU_BUSY(lp);
SMC_SET_MMU_CMD(lp, MC_FREEPKT);
/* Don't restore Packet Number Reg until busy bit is cleared */
SMC_WAIT_MMU_BUSY(lp);
SMC_SET_PN(lp, saved_packet);
/* * Reads a register from the MII Management serial interface
*/ staticint smc_phy_read(struct net_device *dev, int phyaddr, int phyreg)
{ struct smc_local *lp = netdev_priv(dev); void __iomem *ioaddr = lp->base; unsignedint phydata;
/* * Writes a register to the MII Management serial interface
*/ staticvoid smc_phy_write(struct net_device *dev, int phyaddr, int phyreg, int phydata)
{ struct smc_local *lp = netdev_priv(dev); void __iomem *ioaddr = lp->base;
/* * Finds and reports the PHY address
*/ staticvoid smc_phy_detect(struct net_device *dev)
{ struct smc_local *lp = netdev_priv(dev); int phyaddr;
DBG(2, dev, "%s\n", __func__);
lp->phy_type = 0;
/* * Scan all 32 PHY addresses if necessary, starting at * PHY#1 to PHY#31, and then PHY#0 last.
*/ for (phyaddr = 1; phyaddr < 33; ++phyaddr) { unsignedint id1, id2;
/* Make sure it is a valid identifier */ if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 &&
id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) { /* Save the PHY's address */
lp->mii.phy_id = phyaddr & 31;
lp->phy_type = id1 << 16 | id2; break;
}
}
}
/* * Sets the PHY to a configuration as determined by the user
*/ staticint smc_phy_fixed(struct net_device *dev)
{ struct smc_local *lp = netdev_priv(dev); void __iomem *ioaddr = lp->base; int phyaddr = lp->mii.phy_id; int bmcr, cfg1;
DBG(3, dev, "%s\n", __func__);
/* Enter Link Disable state */
cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG);
cfg1 |= PHY_CFG1_LNKDIS;
smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1);
/* Write our capabilities to the phy control register */
smc_phy_write(dev, phyaddr, MII_BMCR, bmcr);
/* Re-Configure the Receive/Phy Control register */
SMC_SELECT_BANK(lp, 0);
SMC_SET_RPC(lp, lp->rpc_cur_mode);
SMC_SELECT_BANK(lp, 2);
return 1;
}
/** * smc_phy_reset - reset the phy * @dev: net device * @phy: phy address * * Issue a software reset for the specified PHY and * wait up to 100ms for the reset to complete. We should * not access the PHY for 50ms after issuing the reset. * * The time to wait appears to be dependent on the PHY. * * Must be called with lp->lock locked.
*/ staticint smc_phy_reset(struct net_device *dev, int phy)
{ struct smc_local *lp = netdev_priv(dev); unsignedint bmcr; int timeout;
smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET);
for (timeout = 2; timeout; timeout--) {
spin_unlock_irq(&lp->lock);
msleep(50);
spin_lock_irq(&lp->lock);
/** * smc_phy_check_media - check the media status and adjust TCR * @dev: net device * @init: set true for initialisation * * Select duplex mode depending on negotiation state. This * also updates our carrier state.
*/ staticvoid smc_phy_check_media(struct net_device *dev, int init)
{ struct smc_local *lp = netdev_priv(dev); void __iomem *ioaddr = lp->base;
if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) { /* duplex state has changed */ if (lp->mii.full_duplex) {
lp->tcr_cur_mode |= TCR_SWFDUP;
} else {
lp->tcr_cur_mode &= ~TCR_SWFDUP;
}
/* * Configures the specified PHY through the MII management interface * using Autonegotiation. * Calls smc_phy_fixed() if the user has requested a certain config. * If RPC ANEG bit is set, the media selection is dependent purely on * the selection by the MII (either in the MII BMCR reg or the result * of autonegotiation.) If the RPC ANEG bit is cleared, the selection * is controlled by the RPC SPEED and RPC DPLX bits.
*/ staticvoid smc_phy_configure(struct work_struct *work)
{ struct smc_local *lp =
container_of(work, struct smc_local, phy_configure); struct net_device *dev = lp->dev; void __iomem *ioaddr = lp->base; int phyaddr = lp->mii.phy_id; int my_phy_caps; /* My PHY capabilities */ int my_ad_caps; /* My Advertised capabilities */
DBG(3, dev, "smc_program_phy()\n");
spin_lock_irq(&lp->lock);
/* * We should not be called if phy_type is zero.
*/ if (lp->phy_type == 0) goto smc_phy_configure_exit;
/* Configure the Receive/Phy Control register */
SMC_SELECT_BANK(lp, 0);
SMC_SET_RPC(lp, lp->rpc_cur_mode);
/* If the user requested no auto neg, then go set his request */ if (lp->mii.force_media) {
smc_phy_fixed(dev); goto smc_phy_configure_exit;
}
/* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR);
if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
netdev_info(dev, "Auto negotiation NOT supported\n");
smc_phy_fixed(dev); goto smc_phy_configure_exit;
}
my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */
if (my_phy_caps & BMSR_100BASE4)
my_ad_caps |= ADVERTISE_100BASE4; if (my_phy_caps & BMSR_100FULL)
my_ad_caps |= ADVERTISE_100FULL; if (my_phy_caps & BMSR_100HALF)
my_ad_caps |= ADVERTISE_100HALF; if (my_phy_caps & BMSR_10FULL)
my_ad_caps |= ADVERTISE_10FULL; if (my_phy_caps & BMSR_10HALF)
my_ad_caps |= ADVERTISE_10HALF;
/* Disable capabilities not selected by our user */ if (lp->ctl_rspeed != 100)
my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
if (!lp->ctl_rfduplx)
my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
/* * Read the register back. Without this, it appears that when * auto-negotiation is restarted, sometimes it isn't ready and * the link does not come up.
*/
smc_phy_read(dev, phyaddr, MII_ADVERTISE);
/* * smc_phy_interrupt * * Purpose: Handle interrupts relating to PHY register 18. This is * called from the "hard" interrupt handler under our private spinlock.
*/ staticvoid smc_phy_interrupt(struct net_device *dev)
{ struct smc_local *lp = netdev_priv(dev); int phyaddr = lp->mii.phy_id; int phy18;
/* * This is the main routine of the driver, to handle the device when * it needs some attention.
*/ static irqreturn_t smc_interrupt(int irq, void *dev_id)
{ struct net_device *dev = dev_id; struct smc_local *lp = netdev_priv(dev); void __iomem *ioaddr = lp->base; int status, mask, timeout, card_stats; int saved_pointer;
DBG(3, dev, "%s\n", __func__);
spin_lock(&lp->lock);
/* A preamble may be used when there is a potential race * between the interruptible transmit functions and this
* ISR. */
SMC_INTERRUPT_PREAMBLE;
/* * We return IRQ_HANDLED unconditionally here even if there was * nothing to do. There is a possibility that a packet might * get enqueued into the chip right after TX_EMPTY_INT is raised * but just before the CPU acknowledges the IRQ. * Better take an unneeded IRQ in some occasions than complexifying * the code for all cases.
*/ return IRQ_HANDLED;
}
#ifdef CONFIG_NET_POLL_CONTROLLER /* * Polling receive - used by netconsole and other diagnostic tools * to allow network i/o with interrupts disabled.
*/ staticvoid smc_poll_controller(struct net_device *dev)
{
disable_irq(dev->irq);
smc_interrupt(dev->irq, dev);
enable_irq(dev->irq);
} #endif
/* Our watchdog timed out. Called by the networking layer */ staticvoid smc_timeout(struct net_device *dev, unsignedint txqueue)
{ struct smc_local *lp = netdev_priv(dev); void __iomem *ioaddr = lp->base; int status, mask, eph_st, meminfo, fifo;
/* * Reconfiguring the PHY doesn't seem like a bad idea here, but * smc_phy_configure() calls msleep() which calls schedule_timeout() * which calls schedule(). Hence we use a work queue.
*/ if (lp->phy_type != 0)
schedule_work(&lp->phy_configure);
/* We can accept TX packets again */
netif_trans_update(dev); /* prevent tx timeout */
netif_wake_queue(dev);
}
/* * This routine will, depending on the values passed to it, * either make it accept multicast packets, go into * promiscuous mode (for TCPDUMP and cousins) or accept * a select set of multicast packets
*/ staticvoid smc_set_multicast_list(struct net_device *dev)
{ struct smc_local *lp = netdev_priv(dev); void __iomem *ioaddr = lp->base; unsignedchar multicast_table[8]; int update_multicast = 0;
/* BUG? I never disable promiscuous mode if multicasting was turned on. Now, I turn off promiscuous mode, but I don't do anything to multicasting when promiscuous mode is turned on.
*/
/* * Here, I am setting this to accept all multicast packets. * I don't need to zero the multicast table, because the flag is * checked before the table is
*/ elseif (dev->flags & IFF_ALLMULTI || netdev_mc_count(dev) > 16) {
DBG(2, dev, "RCR_ALMUL\n");
lp->rcr_cur_mode |= RCR_ALMUL;
}
/* * This sets the internal hardware table to filter out unwanted * multicast packets before they take up memory. * * The SMC chip uses a hash table where the high 6 bits of the CRC of * address are the offset into the table. If that bit is 1, then the * multicast packet is accepted. Otherwise, it's dropped silently. * * To use the 6 bits as an offset into the table, the high 3 bits are * the number of the 8 bit register, while the low 3 bits are the bit * within that register.
*/ elseif (!netdev_mc_empty(dev)) { struct netdev_hw_addr *ha;
/* table for flipping the order of 3 bits */ staticconstunsignedchar invert3[] = {0, 4, 2, 6, 1, 5, 3, 7};
/* start with a table of all zeros: reject all */
memset(multicast_table, 0, sizeof(multicast_table));
netdev_for_each_mc_addr(ha, dev) { int position;
/* only use the low order bits */
position = crc32_le(~0, ha->addr, 6) & 0x3f;
/* do some messy swapping to put the bit in the right spot */
multicast_table[invert3[position&7]] |=
(1<<invert3[(position>>3)&7]);
}
/* be sure I get rid of flags I might have set */
lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
/* now, the table can be loaded into the chipset */
update_multicast = 1;
} else {
DBG(2, dev, "~(RCR_PRMS|RCR_ALMUL)\n");
lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
/* * since I'm disabling all multicast entirely, I need to * clear the multicast list
*/
memset(multicast_table, 0, sizeof(multicast_table));
update_multicast = 1;
}
/* * Open and Initialize the board * * Set up everything, reset the card, etc..
*/ staticint
smc_open(struct net_device *dev)
{ struct smc_local *lp = netdev_priv(dev);
/* * If we are not using a MII interface, we need to * monitor our own carrier signal to detect faults.
*/ if (lp->phy_type == 0)
lp->tcr_cur_mode |= TCR_MON_CSN;
/* reset the hardware */
smc_reset(dev);
smc_enable(dev);
/* Configure the PHY, initialize the link state */ if (lp->phy_type != 0)
smc_phy_configure(&lp->phy_configure); else {
spin_lock_irq(&lp->lock);
smc_10bt_check_media(dev, 1);
spin_unlock_irq(&lp->lock);
}
netif_start_queue(dev); return 0;
}
/* * smc_close * * this makes the board clean up everything that it can * and not talk to the outside world. Caused by * an 'ifconfig ethX down'
*/ staticint smc_close(struct net_device *dev)
{ struct smc_local *lp = netdev_priv(dev);
spin_lock_irq(&lp->lock); /* load word into GP register */
SMC_SELECT_BANK(lp, 1);
SMC_SET_GP(lp, word); /* set the address to put the data in EEPROM */
SMC_SELECT_BANK(lp, 2);
SMC_SET_PTR(lp, addr); /* tell it to write */
SMC_SELECT_BANK(lp, 1);
ctl = SMC_GET_CTL(lp);
SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE)); /* wait for it to finish */ do {
udelay(1);
} while (SMC_GET_CTL(lp) & CTL_STORE); /* clean up */
SMC_SET_CTL(lp, ctl);
SMC_SELECT_BANK(lp, 2);
spin_unlock_irq(&lp->lock); return 0;
}
spin_lock_irq(&lp->lock); /* set the EEPROM address to get the data from */
SMC_SELECT_BANK(lp, 2);
SMC_SET_PTR(lp, addr | PTR_READ); /* tell it to load */
SMC_SELECT_BANK(lp, 1);
SMC_SET_GP(lp, 0xffff); /* init to known */
ctl = SMC_GET_CTL(lp);
SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD)); /* wait for it to finish */ do {
udelay(1);
} while (SMC_GET_CTL(lp) & CTL_RELOAD); /* read word from GP register */
*word = SMC_GET_GP(lp); /* clean up */
SMC_SET_CTL(lp, ctl);
SMC_SELECT_BANK(lp, 2);
spin_unlock_irq(&lp->lock); return 0;
}
/* * smc_findirq * * This routine has a simple purpose -- make the SMC chip generate an * interrupt, so an auto-detect routine can detect it, and find the IRQ,
*/ /* * does this still work? * * I just deleted auto_irq.c, since it was never built... * --jgarzik
*/ staticint smc_findirq(struct smc_local *lp)
{ void __iomem *ioaddr = lp->base; int timeout = 20; unsignedlong cookie;
DBG(2, lp->dev, "%s: %s\n", CARDNAME, __func__);
cookie = probe_irq_on();
/* * What I try to do here is trigger an ALLOC_INT. This is done * by allocating a small chunk of memory, which will give an interrupt * when done.
*/ /* enable ALLOCation interrupts ONLY */
SMC_SELECT_BANK(lp, 2);
SMC_SET_INT_MASK(lp, IM_ALLOC_INT);
/* * Allocate 512 bytes of memory. Note that the chip was just * reset so all the memory is available
*/
SMC_SET_MMU_CMD(lp, MC_ALLOC | 1);
/* * Wait until positive that the interrupt has been generated
*/ do { int int_status;
udelay(10);
int_status = SMC_GET_INT(lp); if (int_status & IM_ALLOC_INT) break; /* got the interrupt */
} while (--timeout);
/* * there is really nothing that I can do here if timeout fails, * as autoirq_report will return a 0 anyway, which is what I * want in this case. Plus, the clean up is needed in both * cases.
*/
/* and disable all interrupts again */
SMC_SET_INT_MASK(lp, 0);
/* and return what I found */ return probe_irq_off(cookie);
}
/* * Function: smc_probe(unsigned long ioaddr) * * Purpose: * Tests to see if a given ioaddr points to an SMC91x chip. * Returns a 0 on success * * Algorithm: * (1) see if the high byte of BANK_SELECT is 0x33 * (2) compare the ioaddr with the base register's address * (3) see if I recognize the chip ID in the appropriate register * * Here I do typical initialization tasks. * * o Initialize the structure if needed * o print out my vanity message if not done so already * o print out what type of hardware is detected * o print out the ethernet address * o find the IRQ * o set up my private data * o configure the dev structure with my subroutines * o actually GRAB the irq. * o GRAB the region
*/ staticint smc_probe(struct net_device *dev, void __iomem *ioaddr, unsignedlong irq_flags)
{ struct smc_local *lp = netdev_priv(dev); int retval; unsignedint val, revision_register; constchar *version_string;
u8 addr[ETH_ALEN];
DBG(2, dev, "%s: %s\n", CARDNAME, __func__);
/* First, see if the high byte is 0x33 */
val = SMC_CURRENT_BANK(lp);
DBG(2, dev, "%s: bank signature probe returned 0x%04x\n",
CARDNAME, val); if ((val & 0xFF00) != 0x3300) { if ((val & 0xFF) == 0x33) {
netdev_warn(dev, "%s: Detected possible byte-swapped interface at IOADDR %p\n",
CARDNAME, ioaddr);
}
retval = -ENODEV; goto err_out;
}
/* * The above MIGHT indicate a device, but I need to write to * further test this.
*/
SMC_SELECT_BANK(lp, 0);
val = SMC_CURRENT_BANK(lp); if ((val & 0xFF00) != 0x3300) {
retval = -ENODEV; goto err_out;
}
/* * well, we've already written once, so hopefully another * time won't hurt. This time, I need to switch the bank * register to bank 1, so I can access the base address * register
*/
SMC_SELECT_BANK(lp, 1);
val = SMC_GET_BASE(lp);
val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT; if (((unsignedlong)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) {
netdev_warn(dev, "%s: IOADDR %p doesn't match configuration (%x).\n",
CARDNAME, ioaddr, val);
}
/* * check if the revision register is something that I * recognize. These might need to be added to later, * as future revisions could be added.
*/
SMC_SELECT_BANK(lp, 3);
revision_register = SMC_GET_REV(lp);
DBG(2, dev, "%s: revision = 0x%04x\n", CARDNAME, revision_register);
version_string = chip_ids[ (revision_register >> 4) & 0xF]; if (!version_string || (revision_register & 0xff00) != 0x3300) { /* I don't recognize this chip, so... */
netdev_warn(dev, "%s: IO %p: Unrecognized revision register 0x%04x, Contact author.\n",
CARDNAME, ioaddr, revision_register);
retval = -ENODEV; goto err_out;
}
/* At this point I'll assume that the chip is an SMC91x. */
pr_info_once("%s\n", version);
/* fill in some of the fields */
dev->base_addr = (unsignedlong)ioaddr;
lp->base = ioaddr;
lp->version = revision_register & 0xff;
spin_lock_init(&lp->lock);
/* Get the MAC address */
SMC_SELECT_BANK(lp, 1);
SMC_GET_MAC_ADDR(lp, addr);
eth_hw_addr_set(dev, addr);
/* now, reset the chip, and put it into a known state */
smc_reset(dev);
/* * If dev->irq is 0, then the device has to be banged on to see * what the IRQ is. * * This banging doesn't always detect the IRQ, for unknown reasons. * a workaround is to reset the chip and try again. * * Interestingly, the DOS packet driver *SETS* the IRQ on the card to * be what is requested on the command line. I don't do that, mostly * because the card that I have uses a non-standard method of accessing * the IRQs, and because this _should_ work in most configurations. * * Specifying an IRQ is done with the assumption that the user knows * what (s)he is doing. No checking is done!!!!
*/ if (dev->irq < 1) { int trials;
trials = 3; while (trials--) {
dev->irq = smc_findirq(lp); if (dev->irq) break; /* kick the card and try again */
smc_reset(dev);
}
} if (dev->irq == 0) {
netdev_warn(dev, "Couldn't autodetect your IRQ. Use irq=xx.\n");
retval = -ENODEV; goto err_out;
}
dev->irq = irq_canonicalize(dev->irq);
retval = register_netdev(dev); if (retval == 0) { /* now, print out the card info, in a short format.. */
netdev_info(dev, "%s (rev %d) at %p IRQ %d",
version_string, revision_register & 0x0f,
lp->base, dev->irq);
if (lp->dma_chan)
pr_cont(" DMA %p", lp->dma_chan);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib"); if (!res) return 0;
/* * Map the attribute space. This is overkill, but clean.
*/
addr = ioremap(res->start, ATTRIB_SIZE); if (!addr) return -ENOMEM;
/* * Reset the device. We must disable IRQs around this * since a reset causes the IRQ line become active.
*/
local_irq_save(flags);
ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
readb(addr + (ECOR << SMC_IO_SHIFT));
/* * Wait 100us for the chip to reset.
*/
udelay(100);
/* * The device will ignore all writes to the enable bit while * reset is asserted, even if the reset bit is cleared in the * same write. Must clear reset first, then enable the device.
*/
writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
/* * Set the appropriate byte/word mode.
*/
ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; if (!SMC_16BIT(lp))
ecsr |= ECSR_IOIS8;
writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
local_irq_restore(flags);
iounmap(addr);
/* * Wait for the chip to wake up. We could poll the control * register in the main register space, but that isn't mapped * yet. We know this is going to take 750us.
*/
msleep(1);
/** * try_toggle_control_gpio - configure a gpio if it exists * @dev: net device * @desc: where to store the GPIO descriptor, if it exists * @name: name of the GPIO in DT * @index: index of the GPIO in DT * @value: set the GPIO to this value * @nsdelay: delay before setting the GPIO
*/ staticint try_toggle_control_gpio(struct device *dev, struct gpio_desc **desc, constchar *name, int index, int value, unsignedint nsdelay)
{ struct gpio_desc *gpio; enum gpiod_flags flags = value ? GPIOD_OUT_LOW : GPIOD_OUT_HIGH;
gpio = devm_gpiod_get_index_optional(dev, name, index, flags); if (IS_ERR(gpio)) return PTR_ERR(gpio);
if (gpio) { if (nsdelay)
usleep_range(nsdelay, 2 * nsdelay);
gpiod_set_value_cansleep(gpio, value);
}
*desc = gpio;
return 0;
} #endif
/* * smc_init(void) * Input parameters: * dev->base_addr == 0, try to find all possible locations * dev->base_addr > 0x1ff, this is the address to check * dev->base_addr == <anything else>, return failure code * * Output: * 0 --> there is a device * anything else, error
*/ staticint smc_drv_probe(struct platform_device *pdev)
{ struct smc91x_platdata *pd = dev_get_platdata(&pdev->dev); conststruct of_device_id *match = NULL; struct smc_local *lp; struct net_device *ndev; struct resource *res; unsignedint __iomem *addr; unsignedlong irq_flags = SMC_IRQ_FLAGS; unsignedlong irq_resflags; int ret;
ndev = alloc_etherdev(sizeof(struct smc_local)); if (!ndev) {
ret = -ENOMEM; goto out;
}
SET_NETDEV_DEV(ndev, &pdev->dev);
/* get configuration from platform data, only allow use of * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set.
*/
lp = netdev_priv(ndev);
lp->cfg.flags = 0;
if (pd) {
memcpy(&lp->cfg, pd, sizeof(lp->cfg));
lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags);
if (!SMC_8BIT(lp) && !SMC_16BIT(lp)) {
dev_err(&pdev->dev, "at least one of 8-bit or 16-bit access support is required.\n");
ret = -ENXIO; goto out_free_netdev;
}
}
#if IS_BUILTIN(CONFIG_OF)
match = of_match_device(of_match_ptr(smc91x_match), &pdev->dev); if (match) {
u32 val;
/* Optional pwrdwn GPIO configured? */
ret = try_toggle_control_gpio(&pdev->dev, &lp->power_gpio, "power", 0, 0, 100); if (ret) goto out_free_netdev;
/* * Optional reset GPIO configured? Minimum 100 ns reset needed * according to LAN91C96 datasheet page 14.
*/
ret = try_toggle_control_gpio(&pdev->dev, &lp->reset_gpio, "reset", 0, 0, 100); if (ret) goto out_free_netdev;
/* * Need to wait for optional EEPROM to load, max 750 us according * to LAN91C96 datasheet page 55.
*/ if (lp->reset_gpio)
usleep_range(750, 1000);
/* Combination of IO widths supported, default to 16-bit */ if (!device_property_read_u32(&pdev->dev, "reg-io-width",
&val)) { if (val & 1)
lp->cfg.flags |= SMC91X_USE_8BIT; if ((val == 0) || (val & 2))
lp->cfg.flags |= SMC91X_USE_16BIT; if (val & 4)
lp->cfg.flags |= SMC91X_USE_32BIT;
} else {
lp->cfg.flags |= SMC91X_USE_16BIT;
} if (!device_property_read_u32(&pdev->dev, "reg-shift",
&val))
lp->io_shift = val;
lp->cfg.pxa_u16_align4 =
device_property_read_bool(&pdev->dev, "pxa-u16-align4");
} #endif
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); if (!res)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) {
ret = -ENODEV; goto out_free_netdev;
}
if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) {
ret = -EBUSY; goto out_free_netdev;
}
ndev->irq = platform_get_irq(pdev, 0); if (ndev->irq < 0) {
ret = ndev->irq; goto out_release_io;
} /* * If this platform does not specify any special irqflags, or if * the resource supplies a trigger, override the irqflags with * the trigger flags from the resource.
*/
irq_resflags = irq_get_trigger_type(ndev->irq); if (irq_flags == -1 || irq_resflags & IRQF_TRIGGER_MASK)
irq_flags = irq_resflags & IRQF_TRIGGER_MASK;
ret = smc_request_attrib(pdev, ndev); if (ret) goto out_release_io; #ifdefined(CONFIG_ASSABET_NEPONSET) if (machine_is_assabet() && machine_has_neponset())
neponset_ncr_set(NCR_ENET_OSC_EN); #endif
platform_set_drvdata(pdev, ndev);
ret = smc_enable_device(pdev); if (ret) goto out_release_attrib;
addr = ioremap(res->start, SMC_IO_EXTENT); if (!addr) {
ret = -ENOMEM; goto out_release_attrib;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs"); if (!res)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(res->start, SMC_IO_EXTENT);
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