/************************************************************************ * regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC * Copyright(c) 2002-2010 Exar Corp. * This software may be used and distributed according to the terms of * the GNU General Public License (GPL), incorporated herein by reference. * Drivers based on or derived from this code fall under the GPL and must * retain the authorship, copyright and license notice. This file is not * a complete program and may only be used when the entire operating * system is licensed under the GPL. * See the file COPYING in this distribution for more information. #ifndef _REGS_H#define _REGS_H#define TBD 0 struct XENA_dev_config {/* Convention: mHAL_XXX is mask, vHAL_XXX is value */ /* General Control-Status Registers */ #define GEN_INTR_TXPIC s2BIT(0 )#define GEN_INTR_TXDMA s2BIT(1 )#define GEN_INTR_TXMAC s2BIT(2 )#define GEN_INTR_TXXGXS s2BIT(3 )#define GEN_INTR_TXTRAFFIC s2BIT(8 )#define GEN_INTR_RXPIC s2BIT(32 )#define GEN_INTR_RXDMA s2BIT(33 )#define GEN_INTR_RXMAC s2BIT(34 )#define GEN_INTR_MC s2BIT(35 )#define GEN_INTR_RXXGXS s2BIT(36 )#define GEN_INTR_RXTRAFFIC s2BIT(40 )#define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \0 x100 - 0 x10];/* XGXS must be removed from reset only once. */ #define SW_RESET_XENA vBIT(0 xA5,0 ,8 )#define SW_RESET_FLASH vBIT(0 xA5,8 ,8 )#define SW_RESET_EOI vBIT(0 xA5,16 ,8 )#define SW_RESET_ALL (SW_RESET_XENA | \/* The SW_RESET register must read this value after a successful reset. */ #define SW_RESET_RAW_VAL 0 xA5000000#define ADAPTER_STATUS_TDMA_READY s2BIT(0 )#define ADAPTER_STATUS_RDMA_READY s2BIT(1 )#define ADAPTER_STATUS_PFC_READY s2BIT(2 )#define ADAPTER_STATUS_TMAC_BUF_EMPTY s2BIT(3 )#define ADAPTER_STATUS_PIC_QUIESCENT s2BIT(5 )#define ADAPTER_STATUS_RMAC_REMOTE_FAULT s2BIT(6 )#define ADAPTER_STATUS_RMAC_LOCAL_FAULT s2BIT(7 )#define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0 xFF,8 ,8 )#define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0 x0F,8 ,8 )#define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0 xFF,16 ,8 )#define ADAPTER_STATUS_MC_DRAM_READY s2BIT(24 )#define ADAPTER_STATUS_MC_QUEUES_READY s2BIT(25 )#define ADAPTER_STATUS_RIC_RUNNING s2BIT(26 )#define ADAPTER_STATUS_M_PLL_LOCK s2BIT(30 )#define ADAPTER_STATUS_P_PLL_LOCK s2BIT(31 )#define ADAPTER_CNTL_EN s2BIT(7 )#define ADAPTER_EOI_TX_ON s2BIT(15 )#define ADAPTER_LED_ON s2BIT(23 )#define ADAPTER_UDPI(val) vBIT(val,36 ,4 )#define ADAPTER_WAIT_INT s2BIT(48 )#define ADAPTER_ECC_EN s2BIT(55 )#define SERR_SOURCE_PIC s2BIT(0 )#define SERR_SOURCE_TXDMA s2BIT(1 )#define SERR_SOURCE_RXDMA s2BIT(2 )#define SERR_SOURCE_MAC s2BIT(3 )#define SERR_SOURCE_MC s2BIT(4 )#define SERR_SOURCE_XGXS s2BIT(5 )#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \#define GET_PCI_MODE(val) ((val & vBIT(0 xF, 0 , 4 )) >> 60 )#define PCI_MODE_PCI_33 0 #define PCI_MODE_PCI_66 0 x1#define PCI_MODE_PCIX_M1_66 0 x2#define PCI_MODE_PCIX_M1_100 0 x3#define PCI_MODE_PCIX_M1_133 0 x4#define PCI_MODE_PCIX_M2_66 0 x5#define PCI_MODE_PCIX_M2_100 0 x6#define PCI_MODE_PCIX_M2_133 0 x7#define PCI_MODE_UNSUPPORTED s2BIT(0 )#define PCI_MODE_32_BITS s2BIT(8 )#define PCI_MODE_UNKNOWN_MODE s2BIT(9 )0 x800 - 0 x128];/* PCI-X Controller registers */ #define PIC_INT_TX s2BIT(0 )#define PIC_INT_FLSH s2BIT(1 )#define PIC_INT_MDIO s2BIT(2 )#define PIC_INT_IIC s2BIT(3 )#define PIC_INT_GPIO s2BIT(4 )#define PIC_INT_RX s2BIT(32 )#define PCIX_INT_REG_ECC_SG_ERR s2BIT(0 )#define PCIX_INT_REG_ECC_DB_ERR s2BIT(1 )#define PCIX_INT_REG_FLASHR_R_FSM_ERR s2BIT(8 )#define PCIX_INT_REG_FLASHR_W_FSM_ERR s2BIT(9 )#define PCIX_INT_REG_INI_TX_FSM_SERR s2BIT(10 )#define PCIX_INT_REG_INI_TXO_FSM_ERR s2BIT(11 )#define PCIX_INT_REG_TRT_FSM_SERR s2BIT(13 )#define PCIX_INT_REG_SRT_FSM_SERR s2BIT(14 )#define PCIX_INT_REG_PIFR_FSM_SERR s2BIT(15 )#define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR s2BIT(21 )#define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR s2BIT(23 )#define PCIX_INT_REG_INI_RX_FSM_SERR s2BIT(48 )#define PCIX_INT_REG_RA_RX_FSM_SERR s2BIT(50 )/*#define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR s2BIT(52) #define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR s2BIT(54) #define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR s2BIT(58) #define PIC_FLSH_INT_REG_CYCLE_FSM_ERR s2BIT(63 )#define PIC_FLSH_INT_REG_ERR s2BIT(62 )#define MDIO_INT_REG_MDIO_BUS_ERR s2BIT(0 )#define MDIO_INT_REG_DTX_BUS_ERR s2BIT(8 )#define MDIO_INT_REG_LASI s2BIT(39 )#define IIC_INT_REG_BUS_FSM_ERR s2BIT(4 )#define IIC_INT_REG_BIT_FSM_ERR s2BIT(5 )#define IIC_INT_REG_CYCLE_FSM_ERR s2BIT(6 )#define IIC_INT_REG_REQ_FSM_ERR s2BIT(7 )#define IIC_INT_REG_ACK_ERR s2BIT(8 )0 x08];#define GPIO_INT_REG_DP_ERR_INT s2BIT(0 )#define GPIO_INT_REG_LINK_DOWN s2BIT(1 )#define GPIO_INT_REG_LINK_UP s2BIT(2 )#define GPIO_INT_MASK_LINK_DOWN s2BIT(1 )#define GPIO_INT_MASK_LINK_UP s2BIT(2 )0 x38];#define TX_TRAFFIC_INT_n(n) s2BIT(n)#define RX_TRAFFIC_INT_n(n) s2BIT(n)/* PIC Control registers */ #define PIC_CNTL_RX_ALARM_MAP_1 s2BIT(0 )#define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11 ,5 )#define SWAPPER_CTRL_PIF_R_FE s2BIT(0 )#define SWAPPER_CTRL_PIF_R_SE s2BIT(1 )#define SWAPPER_CTRL_PIF_W_FE s2BIT(8 )#define SWAPPER_CTRL_PIF_W_SE s2BIT(9 )#define SWAPPER_CTRL_TXP_FE s2BIT(16 )#define SWAPPER_CTRL_TXP_SE s2BIT(17 )#define SWAPPER_CTRL_TXD_R_FE s2BIT(18 )#define SWAPPER_CTRL_TXD_R_SE s2BIT(19 )#define SWAPPER_CTRL_TXD_W_FE s2BIT(20 )#define SWAPPER_CTRL_TXD_W_SE s2BIT(21 )#define SWAPPER_CTRL_TXF_R_FE s2BIT(22 )#define SWAPPER_CTRL_TXF_R_SE s2BIT(23 )#define SWAPPER_CTRL_RXD_R_FE s2BIT(32 )#define SWAPPER_CTRL_RXD_R_SE s2BIT(33 )#define SWAPPER_CTRL_RXD_W_FE s2BIT(34 )#define SWAPPER_CTRL_RXD_W_SE s2BIT(35 )#define SWAPPER_CTRL_RXF_W_FE s2BIT(36 )#define SWAPPER_CTRL_RXF_W_SE s2BIT(37 )#define SWAPPER_CTRL_XMSI_FE s2BIT(40 )#define SWAPPER_CTRL_XMSI_SE s2BIT(41 )#define SWAPPER_CTRL_STATS_FE s2BIT(48 )#define SWAPPER_CTRL_STATS_SE s2BIT(49 )#define IF_RD_SWAPPER_FB 0 x0123456789ABCDEF#define SCHED_INT_CTRL_TIMER_EN s2BIT(0 )#define SCHED_INT_CTRL_ONE_SHOT s2BIT(1 )#define SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10 ,6 )#define SCHED_INT_PERIOD TBD#define TXREQTO_VAL(val) vBIT(val,0 ,32 )#define TXREQTO_EN s2BIT(63 )#define STATREQTO_VAL(n) TBD#define STATREQTO_EN s2BIT(63 )#define RX_MAT_SET(ring, msi) vBIT(msi, (8 * ring), 8 )0 x8];0 x8];#define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8 )#define STAT_BC(n) vBIT(n,4 ,12 )/* Automated statistics collection */ #define STAT_CFG_STAT_EN s2BIT(0 )#define STAT_CFG_ONE_SHOT_EN s2BIT(1 )#define STAT_CFG_STAT_NS_EN s2BIT(8 )#define STAT_CFG_STAT_RO s2BIT(9 )#define STAT_TRSF_PER(n) TBD#define PER_SEC 0 x208d5#define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32 ,32 )#define SET_UPDT_CLICKS(val) vBIT(val, 32 , 32 )/* General Configuration */ #define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0 , 16 )#define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19 , 5 )#define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27 , 5 )#define MDIO_CTRL_START_TRANS(val) vBIT(val, 56 , 4 )#define MDIO_OP(val) vBIT(val, 60 , 2 )#define MDIO_OP_ADDR_TRANS 0 x0#define MDIO_OP_WRITE_TRANS 0 x1#define MDIO_OP_READ_POST_INC_TRANS 0 x2#define MDIO_OP_READ_TRANS 0 x3#define MDIO_MDIO_DATA(val) vBIT(val, 32 , 16 )#define I2C_CONTROL_DEV_ID(id) vBIT(id,1 ,3 )#define I2C_CONTROL_ADDR(addr) vBIT(addr,5 ,11 )#define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22 ,2 )#define I2C_CONTROL_READ s2BIT(24 )#define I2C_CONTROL_NACK s2BIT(25 )#define I2C_CONTROL_CNTL_START vBIT(0 xE,28 ,4 )#define I2C_CONTROL_CNTL_END(val) (val & vBIT(0 x1,28 ,4 ))#define I2C_CONTROL_GET_DATA(val) (u32)(val & 0 xFFFFFFFF)#define I2C_CONTROL_SET_DATA(val) vBIT(val,32 ,32 )#define GPIO_CTRL_GPIO_0 s2BIT(8 )#define FAULT_BEHAVIOUR s2BIT(0 )#define EXT_REQ_EN s2BIT(1 )#define MISC_LINK_STABILITY_PRD(val) vBIT(val,29 ,3 )0 x230 - 0 x208];#define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52 , 12 )0 x800 - 0 x248];/* TxDMA registers */ #define TXDMA_PFC_INT s2BIT(0 )#define TXDMA_TDA_INT s2BIT(1 )#define TXDMA_PCC_INT s2BIT(2 )#define TXDMA_TTI_INT s2BIT(3 )#define TXDMA_LSO_INT s2BIT(4 )#define TXDMA_TPA_INT s2BIT(5 )#define TXDMA_SM_INT s2BIT(6 )#define PFC_ECC_SG_ERR s2BIT(7 )#define PFC_ECC_DB_ERR s2BIT(15 )#define PFC_SM_ERR_ALARM s2BIT(23 )#define PFC_MISC_0_ERR s2BIT(31 )#define PFC_MISC_1_ERR s2BIT(32 )#define PFC_PCIX_ERR s2BIT(39 )#define TDA_Fn_ECC_SG_ERR vBIT(0 xff,0 ,8 )#define TDA_Fn_ECC_DB_ERR vBIT(0 xff,8 ,8 )#define TDA_SM0_ERR_ALARM s2BIT(22 )#define TDA_SM1_ERR_ALARM s2BIT(23 )#define TDA_PCIX_ERR s2BIT(39 )#define PCC_FB_ECC_SG_ERR vBIT(0 xFF,0 ,8 )#define PCC_TXB_ECC_SG_ERR vBIT(0 xFF,8 ,8 )#define PCC_FB_ECC_DB_ERR vBIT(0 xFF,16 , 8 )#define PCC_TXB_ECC_DB_ERR vBIT(0 xff,24 ,8 )#define PCC_SM_ERR_ALARM vBIT(0 xff,32 ,8 )#define PCC_WR_ERR_ALARM vBIT(0 xff,40 ,8 )#define PCC_N_SERR vBIT(0 xff,48 ,8 )#define PCC_6_COF_OV_ERR s2BIT(56 )#define PCC_7_COF_OV_ERR s2BIT(57 )#define PCC_6_LSO_OV_ERR s2BIT(58 )#define PCC_7_LSO_OV_ERR s2BIT(59 )#define PCC_ENABLE_FOUR vBIT(0 x0F,0 ,8 )#define TTI_ECC_SG_ERR s2BIT(7 )#define TTI_ECC_DB_ERR s2BIT(15 )#define TTI_SM_ERR_ALARM s2BIT(23 )#define LSO6_SEND_OFLOW s2BIT(12 )#define LSO7_SEND_OFLOW s2BIT(13 )#define LSO6_ABORT s2BIT(14 )#define LSO7_ABORT s2BIT(15 )#define LSO6_SM_ERR_ALARM s2BIT(22 )#define LSO7_SM_ERR_ALARM s2BIT(23 )#define TPA_TX_FRM_DROP s2BIT(7 )#define TPA_SM_ERR_ALARM s2BIT(23 )#define SM_SM_ERR_ALARM s2BIT(15 )0 x100 - 0 xB8];/* TxDMA arbiter */ /* Tx FIFO controller */ #define X_MAX_FIFOS 8 #define X_FIFO_MAX_LEN 0 x1FFF /*8191 */ #define TX_FIFO_PARTITION_EN s2BIT(0 )#define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5 ,3 )#define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19 ,13 )#define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37 ,3 )#define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51 ,13 )#define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5 ,3 )#define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19 ,13 )#define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37 ,3 )#define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51 ,13 )#define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5 ,3 )#define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19 ,13 )#define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37 ,3 )#define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51 ,13 )#define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5 ,3 )#define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19 ,13 )#define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37 ,3 )#define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51 ,13 )#define TX_FIFO_PARTITION_PRI_0 0 /* highest */ #define TX_FIFO_PARTITION_PRI_1 1 #define TX_FIFO_PARTITION_PRI_2 2 #define TX_FIFO_PARTITION_PRI_3 3 #define TX_FIFO_PARTITION_PRI_4 4 #define TX_FIFO_PARTITION_PRI_5 5 #define TX_FIFO_PARTITION_PRI_6 6 #define TX_FIFO_PARTITION_PRI_7 7 /* lowest */ #define TTI_CMD_MEM_WE s2BIT(7 )#define TTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15 )#define TTI_CMD_MEM_STROBE_BEING_EXECUTED s2BIT(15 )#define TTI_CMD_MEM_OFFSET(n) vBIT(n,26 ,6 )#define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6 ,26 )#define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38 ,2 )#define TTI_DATA1_MEM_TX_TIMER_AC_EN s2BIT(38 )#define TTI_DATA1_MEM_TX_TIMER_CI_EN s2BIT(39 )#define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41 ,7 )#define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49 ,7 )#define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57 ,7 )#define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0 ,16 )#define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16 ,16 )#define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32 ,16 )#define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48 ,16 )/* Tx Protocol assist */ #define TX_PA_CFG_IGNORE_FRM_ERR s2BIT(1 )#define TX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2 )#define TX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3 )#define TX_PA_CFG_IGNORE_L2_ERR s2BIT(6 )#define RX_PA_CFG_STRIP_VLAN_TAG s2BIT(15 )/* Recent add, used only debug purposes. */ 0 x700 - 0 x178];0 x1800 - 0 x1708];/* RxDMA Registers */ #define RXDMA_INT_RC_INT_M s2BIT(0 )#define RXDMA_INT_RPA_INT_M s2BIT(1 )#define RXDMA_INT_RDA_INT_M s2BIT(2 )#define RXDMA_INT_RTI_INT_M s2BIT(3 )#define RDA_RXDn_ECC_SG_ERR vBIT(0 xFF,0 ,8 )#define RDA_RXDn_ECC_DB_ERR vBIT(0 xFF,8 ,8 )#define RDA_FRM_ECC_SG_ERR s2BIT(23 )#define RDA_FRM_ECC_DB_N_AERR s2BIT(31 )#define RDA_SM1_ERR_ALARM s2BIT(38 )#define RDA_SM0_ERR_ALARM s2BIT(39 )#define RDA_MISC_ERR s2BIT(47 )#define RDA_PCIX_ERR s2BIT(55 )#define RDA_RXD_ECC_DB_SERR s2BIT(63 )#define RC_PRCn_ECC_SG_ERR vBIT(0 xFF,0 ,8 )#define RC_PRCn_ECC_DB_ERR vBIT(0 xFF,8 ,8 )#define RC_FTC_ECC_SG_ERR s2BIT(23 )#define RC_FTC_ECC_DB_ERR s2BIT(31 )#define RC_PRCn_SM_ERR_ALARM vBIT(0 xFF,32 ,8 )#define RC_FTC_SM_ERR_ALARM s2BIT(47 )#define RC_RDA_FAIL_WR_Rn vBIT(0 xFF,48 ,8 )#define PRC_PCI_AB_RD_Rn vBIT(0 xFF,0 ,8 )#define PRC_PCI_DP_RD_Rn vBIT(0 xFF,8 ,8 )#define PRC_PCI_AB_WR_Rn vBIT(0 xFF,16 ,8 )#define PRC_PCI_DP_WR_Rn vBIT(0 xFF,24 ,8 )#define PRC_PCI_AB_F_WR_Rn vBIT(0 xFF,32 ,8 )#define PRC_PCI_DP_F_WR_Rn vBIT(0 xFF,40 ,8 )#define RPA_ECC_SG_ERR s2BIT(7 )#define RPA_ECC_DB_ERR s2BIT(15 )#define RPA_FLUSH_REQUEST s2BIT(22 )#define RPA_SM_ERR_ALARM s2BIT(23 )#define RPA_CREDIT_ERR s2BIT(31 )#define RTI_ECC_SG_ERR s2BIT(7 )#define RTI_ECC_DB_ERR s2BIT(15 )#define RTI_SM_ERR_ALARM s2BIT(23 )0 x100 - 0 x88];/* DMA arbiter */ #define RX_QUEUE_0_PRIORITY(val) vBIT(val,5 ,3 )#define RX_QUEUE_1_PRIORITY(val) vBIT(val,13 ,3 )#define RX_QUEUE_2_PRIORITY(val) vBIT(val,21 ,3 )#define RX_QUEUE_3_PRIORITY(val) vBIT(val,29 ,3 )#define RX_QUEUE_4_PRIORITY(val) vBIT(val,37 ,3 )#define RX_QUEUE_5_PRIORITY(val) vBIT(val,45 ,3 )#define RX_QUEUE_6_PRIORITY(val) vBIT(val,53 ,3 )#define RX_QUEUE_7_PRIORITY(val) vBIT(val,61 ,3 )#define RX_QUEUE_PRI_0 0 /* highest */ #define RX_QUEUE_PRI_1 1 #define RX_QUEUE_PRI_2 2 #define RX_QUEUE_PRI_3 3 #define RX_QUEUE_PRI_4 4 #define RX_QUEUE_PRI_5 5 #define RX_QUEUE_PRI_6 6 #define RX_QUEUE_PRI_7 7 /* lowest */ /* Per-ring controller regs */ #define RX_MAX_RINGS 8 #if 0 #define RX_MAX_RINGS_SZ 0 xFFFF /* 65536 */ #define RX_MIN_RINGS_SZ 0 x3F /* 63 */ #endif #define PRC_CTRL_RC_ENABLED s2BIT(7 )#define PRC_CTRL_RING_MODE (s2BIT(14 )|s2BIT(15 ))#define PRC_CTRL_RING_MODE_1 vBIT(0 ,14 ,2 )#define PRC_CTRL_RING_MODE_3 vBIT(1 ,14 ,2 )#define PRC_CTRL_RING_MODE_5 vBIT(2 ,14 ,2 )#define PRC_CTRL_RING_MODE_x vBIT(3 ,14 ,2 )#define PRC_CTRL_NO_SNOOP (s2BIT(22 )|s2BIT(23 ))#define PRC_CTRL_NO_SNOOP_DESC s2BIT(22 )#define PRC_CTRL_NO_SNOOP_BUFF s2BIT(23 )#define PRC_CTRL_BIMODAL_INTERRUPT s2BIT(37 )#define PRC_CTRL_GROUP_READS s2BIT(38 )#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40 ,24 )#define PRC_ALARM_ACTION_RR_R0_STOP s2BIT(3 )#define PRC_ALARM_ACTION_RW_R0_STOP s2BIT(7 )#define PRC_ALARM_ACTION_RR_R1_STOP s2BIT(11 )#define PRC_ALARM_ACTION_RW_R1_STOP s2BIT(15 )#define PRC_ALARM_ACTION_RR_R2_STOP s2BIT(19 )#define PRC_ALARM_ACTION_RW_R2_STOP s2BIT(23 )#define PRC_ALARM_ACTION_RR_R3_STOP s2BIT(27 )#define PRC_ALARM_ACTION_RW_R3_STOP s2BIT(31 )#define PRC_ALARM_ACTION_RR_R4_STOP s2BIT(35 )#define PRC_ALARM_ACTION_RW_R4_STOP s2BIT(39 )#define PRC_ALARM_ACTION_RR_R5_STOP s2BIT(43 )#define PRC_ALARM_ACTION_RW_R5_STOP s2BIT(47 )#define PRC_ALARM_ACTION_RR_R6_STOP s2BIT(51 )#define PRC_ALARM_ACTION_RW_R6_STOP s2BIT(55 )#define PRC_ALARM_ACTION_RR_R7_STOP s2BIT(59 )#define PRC_ALARM_ACTION_RW_R7_STOP s2BIT(63 )/* Receive traffic interrupts */ #define RTI_CMD_MEM_WE s2BIT(7 )#define RTI_CMD_MEM_STROBE s2BIT(15 )#define RTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15 )#define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED s2BIT(15 )#define RTI_CMD_MEM_OFFSET(n) vBIT(n,29 ,3 )#define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3 ,29 )#define RTI_DATA1_MEM_RX_TIMER_AC_EN s2BIT(38 )#define RTI_DATA1_MEM_RX_TIMER_CI_EN s2BIT(39 )#define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41 ,7 )#define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49 ,7 )#define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57 ,7 )#define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0 ,16 )#define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16 ,16 )#define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32 ,16 )#define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48 ,16 )#define RX_PA_CFG_IGNORE_FRM_ERR s2BIT(1 )#define RX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2 )#define RX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3 )#define RX_PA_CFG_IGNORE_L2_ERR s2BIT(6 )0 x700 - 0 x1F0];0 x2000 - 0 x1f08];/* Media Access Controller Register */ #define MAC_INT_STATUS_TMAC_INT s2BIT(0 )#define MAC_INT_STATUS_RMAC_INT s2BIT(1 )#define TMAC_ECC_SG_ERR s2BIT(7 )#define TMAC_ECC_DB_ERR s2BIT(15 )#define TMAC_TX_BUF_OVRN s2BIT(23 )#define TMAC_TX_CRI_ERR s2BIT(31 )#define TMAC_TX_SM_ERR s2BIT(39 )#define TMAC_DESC_ECC_SG_ERR s2BIT(47 )#define TMAC_DESC_ECC_DB_ERR s2BIT(55 )#define RMAC_RX_BUFF_OVRN s2BIT(0 )#define RMAC_FRM_RCVD_INT s2BIT(1 )#define RMAC_UNUSED_INT s2BIT(2 )#define RMAC_RTS_PNUM_ECC_SG_ERR s2BIT(5 )#define RMAC_RTS_DS_ECC_SG_ERR s2BIT(6 )#define RMAC_RD_BUF_ECC_SG_ERR s2BIT(7 )#define RMAC_RTH_MAP_ECC_SG_ERR s2BIT(8 )#define RMAC_RTH_SPDM_ECC_SG_ERR s2BIT(9 )#define RMAC_RTS_VID_ECC_SG_ERR s2BIT(10 )#define RMAC_DA_SHADOW_ECC_SG_ERR s2BIT(11 )#define RMAC_RTS_PNUM_ECC_DB_ERR s2BIT(13 )#define RMAC_RTS_DS_ECC_DB_ERR s2BIT(14 )#define RMAC_RD_BUF_ECC_DB_ERR s2BIT(15 )#define RMAC_RTH_MAP_ECC_DB_ERR s2BIT(16 )#define RMAC_RTH_SPDM_ECC_DB_ERR s2BIT(17 )#define RMAC_RTS_VID_ECC_DB_ERR s2BIT(18 )#define RMAC_DA_SHADOW_ECC_DB_ERR s2BIT(19 )#define RMAC_LINK_STATE_CHANGE_INT s2BIT(31 )#define RMAC_RX_SM_ERR s2BIT(39 )#define RMAC_SINGLE_ECC_ERR (s2BIT(5 ) | s2BIT(6 ) | s2BIT(7 ) |\8 ) | s2BIT(9 ) | s2BIT(10 )|\11 ))#define RMAC_DOUBLE_ECC_ERR (s2BIT(13 ) | s2BIT(14 ) | s2BIT(15 ) |\16 ) | s2BIT(17 ) | s2BIT(18 )|\19 ))0 x100 - 0 x40];#define MAC_CFG_TMAC_ENABLE s2BIT(0 )#define MAC_CFG_RMAC_ENABLE s2BIT(1 )#define MAC_CFG_LAN_NOT_WAN s2BIT(2 )#define MAC_CFG_TMAC_LOOPBACK s2BIT(3 )#define MAC_CFG_TMAC_APPEND_PAD s2BIT(4 )#define MAC_CFG_RMAC_STRIP_FCS s2BIT(5 )#define MAC_CFG_RMAC_STRIP_PAD s2BIT(6 )#define MAC_CFG_RMAC_PROM_ENABLE s2BIT(7 )#define MAC_RMAC_DISCARD_PFRM s2BIT(8 )#define MAC_RMAC_BCAST_ENABLE s2BIT(9 )#define MAC_RMAC_ALL_ADDR_ENABLE s2BIT(10 )#define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16 ,8 )#define TMAC_AVG_IPG(val) vBIT(val,0 ,8 )#define RMAC_MAX_PYLD_LEN(val) vBIT(val,2 ,14 )#define RMAC_MAX_PYLD_LEN_DEF vBIT(1500 ,2 ,14 )#define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600 ,2 ,14 )#define RMAC_ERR_FCS s2BIT(0 )#define RMAC_ERR_FCS_ACCEPT s2BIT(1 )#define RMAC_ERR_TOO_LONG s2BIT(1 )#define RMAC_ERR_TOO_LONG_ACCEPT s2BIT(1 )#define RMAC_ERR_RUNT s2BIT(2 )#define RMAC_ERR_RUNT_ACCEPT s2BIT(2 )#define RMAC_ERR_LEN_MISMATCH s2BIT(3 )#define RMAC_ERR_LEN_MISMATCH_ACCEPT s2BIT(3 )#define RMAC_CFG_KEY(val) vBIT(val,0 ,16 )#define S2IO_MAC_ADDR_START_OFFSET 0 #define S2IO_XENA_MAX_MC_ADDRESSES 64 /* multicast addresses */ #define S2IO_HERC_MAX_MC_ADDRESSES 256 #define S2IO_XENA_MAX_MAC_ADDRESSES 16 #define S2IO_HERC_MAX_MAC_ADDRESSES 64 #define S2IO_XENA_MC_ADDR_START_OFFSET 16 #define S2IO_HERC_MC_ADDR_START_OFFSET 64 #define RMAC_ADDR_CMD_MEM_WE s2BIT(7 )#define RMAC_ADDR_CMD_MEM_RD 0 #define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD s2BIT(15 )#define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING s2BIT(15 )#define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26 ,6 )#define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0 ,48 )#define RMAC_ADDR_DATA0_MEM_USER s2BIT(48 )#define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0 ,48 )0 x8];/* u64 rmac_addr_cfg; #define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n) #define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n) #define RMAC_ADDR_BCAST_EN vBIT(0)_48 #define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49 #define RMAC_PAUSE_GEN s2BIT(0 )#define RMAC_PAUSE_GEN_ENABLE s2BIT(0 )#define RMAC_PAUSE_RX s2BIT(1 )#define RMAC_PAUSE_RX_ENABLE s2BIT(1 )#define RMAC_PAUSE_HG_PTIME_DEF vBIT(0 xFFFF,16 ,16 )#define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16 ,16 )#define MAC_TX_LINK_UTIL vBIT(0 xFE,1 ,7 )#define MAC_TX_LINK_UTIL_DISABLE vBIT(0 xF, 8 ,4 )#define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8 ,4 )#define MAC_RX_LINK_UTIL vBIT(0 xFE,33 ,7 )#define MAC_RX_LINK_UTIL_DISABLE vBIT(0 xF,40 ,4 )#define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40 ,4 )#define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \/* rx traffic steering */ #define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2 ,14 )8 ];#define MAX_DIX_MAP 4 #define RTS_DIX_MAP_ETYPE(val) vBIT(val,0 ,16 )#define RTS_DIX_MAP_SCW(val) s2BIT(val,21 )#define RTS_CTRL_IGNORE_SNAP_OUI s2BIT(2 )#define RTS_CTRL_IGNORE_LLC_CTRL s2BIT(3 )#define RTS_PN_CAM_CTRL_WE s2BIT(7 )#define RTS_PN_CAM_CTRL_STROBE_NEW_CMD s2BIT(15 )#define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED s2BIT(15 )#define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24 ,8 )#define RTS_PN_CAM_DATA_TCP_SELECT s2BIT(7 )#define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8 ,16 )#define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24 ,8 )#define RTS_DS_MEM_CTRL_WE s2BIT(7 )#define RTS_DS_MEM_CTRL_STROBE_NEW_CMD s2BIT(15 )#define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED s2BIT(15 )#define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26 ,6 )#define RTS_DS_MEM_DATA(n) vBIT(n,0 ,8 )0 x700 - 0 x220];#define MAC_DBG_ACTIVITY_VALUE 0 x411040400000000ULL0 x2800 - 0 x2708];/* memory controller registers */ #define MC_INT_STATUS_MC_INT s2BIT(0 )#define MC_INT_MASK_MC_INT s2BIT(0 )#define MC_ERR_REG_ECC_DB_ERR_L s2BIT(14 )#define MC_ERR_REG_ECC_DB_ERR_U s2BIT(15 )#define MC_ERR_REG_MIRI_ECC_DB_ERR_0 s2BIT(18 )#define MC_ERR_REG_MIRI_ECC_DB_ERR_1 s2BIT(20 )#define MC_ERR_REG_MIRI_CRI_ERR_0 s2BIT(22 )#define MC_ERR_REG_MIRI_CRI_ERR_1 s2BIT(23 )#define MC_ERR_REG_SM_ERR s2BIT(31 )#define MC_ERR_REG_ECC_ALL_SNG (s2BIT(2 ) | s2BIT(3 ) | s2BIT(4 ) | s2BIT(5 ) |\17 ) | s2BIT(19 ))#define MC_ERR_REG_ECC_ALL_DBL (s2BIT(10 ) | s2BIT(11 ) | s2BIT(12 ) |\13 ) | s2BIT(18 ) | s2BIT(20 ))#define PLL_LOCK_N s2BIT(39 )0 x100 - 0 x28];/* MC configuration */ #define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0 ,8 )#define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8 ,8 )#define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16 ,8 )#define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24 ,8 )#define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32 ,8 )#define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40 ,8 )#define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48 ,8 )#define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56 ,8 )#define MC_RLDRAM_QUEUE_SIZE_ENABLE s2BIT(39 )#define MC_RLDRAM_MRS_ENABLE s2BIT(47 )8 ];0 x200 - 0 x168];0 x220 - 0 x208];#define MC_RLDRAM_TEST_MODE s2BIT(47 )#define MC_RLDRAM_TEST_WRITE s2BIT(7 )#define MC_RLDRAM_TEST_GO s2BIT(15 )#define MC_RLDRAM_TEST_DONE s2BIT(23 )#define MC_RLDRAM_TEST_PASS s2BIT(31 )0 x240 - 0 x228];0 x260 - 0 x248];0 x280 - 0 x268];0 x300 - 0 x288];0 x360 - 0 x308];#define MC_RLDRAM_ENABLE_ODT s2BIT(7 )0 x640 - 0 x368];#define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0 , 16 )0 x660 - 0 x648];0 x700 - 0 x668];0 x3000 - 0 x2f08];/* XGXG */ /* XGXS control registers */ #define XGXS_INT_STATUS_TXGXS s2BIT(0 )#define XGXS_INT_STATUS_RXGXS s2BIT(1 )#define XGXS_INT_MASK_TXGXS s2BIT(0 )#define XGXS_INT_MASK_RXGXS s2BIT(1 )#define TXGXS_ECC_SG_ERR s2BIT(7 )#define TXGXS_ECC_DB_ERR s2BIT(15 )#define TXGXS_ESTORE_UFLOW s2BIT(31 )#define TXGXS_TX_SM_ERR s2BIT(39 )#define RXGXS_ESTORE_OFLOW s2BIT(7 )#define RXGXS_RX_SM_ERR s2BIT(39 )0 x100 - 0 x40];/* CHANGED */ /* CHANGED */ /* CHANGED */ #define SPI_CONTROL_KEY(key) vBIT(key,0 ,4 )#define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29 ,3 )#define SPI_CONTROL_CMD(cmd) vBIT(cmd,32 ,8 )#define SPI_CONTROL_ADDR(addr) vBIT(addr,40 ,24 )#define SPI_CONTROL_SEL1 s2BIT(4 )#define SPI_CONTROL_REQ s2BIT(7 )#define SPI_CONTROL_NACK s2BIT(5 )#define SPI_CONTROL_DONE s2BIT(6 )#define SPI_DATA_WRITE(data,len) vBIT(data,0 ,len)#define XENA_REG_SPACE sizeof (struct XENA_dev_config)#define XENA_EEPROM_SPACE (0 x01 << 11 )#endif /* _REGS_H */
Messung V0.5 in Prozent C=94 H=92 G=92
¤ Dauer der Verarbeitung: 0.4 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
