/** * i40e_vc_vf_broadcast * @pf: pointer to the PF structure * @v_opcode: operation code * @v_retval: return value * @msg: pointer to the msg buffer * @msglen: msg length * * send a message to all VFs on a given PF
**/ staticvoid i40e_vc_vf_broadcast(struct i40e_pf *pf, enum virtchnl_ops v_opcode, int v_retval, u8 *msg,
u16 msglen)
{ struct i40e_hw *hw = &pf->hw; struct i40e_vf *vf = pf->vf; int i;
for (i = 0; i < pf->num_alloc_vfs; i++, vf++) { int abs_vf_id = vf->vf_id + (int)hw->func_caps.vf_base_id; /* Not all vfs are enabled so skip the ones that are not */ if (!test_bit(I40E_VF_STATE_INIT, &vf->vf_states) &&
!test_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states)) continue;
/* Ignore return value on purpose - a given VF may fail, but * we need to keep going and send to all of them
*/
i40e_aq_send_msg_to_vf(hw, abs_vf_id, v_opcode, v_retval,
msg, msglen, NULL);
}
}
/** * i40e_vc_link_speed2mbps * converts i40e_aq_link_speed to integer value of Mbps * @link_speed: the speed to convert * * return the speed as direct value of Mbps.
**/ static u32
i40e_vc_link_speed2mbps(enum i40e_aq_link_speed link_speed)
{ switch (link_speed) { case I40E_LINK_SPEED_100MB: return SPEED_100; case I40E_LINK_SPEED_1GB: return SPEED_1000; case I40E_LINK_SPEED_2_5GB: return SPEED_2500; case I40E_LINK_SPEED_5GB: return SPEED_5000; case I40E_LINK_SPEED_10GB: return SPEED_10000; case I40E_LINK_SPEED_20GB: return SPEED_20000; case I40E_LINK_SPEED_25GB: return SPEED_25000; case I40E_LINK_SPEED_40GB: return SPEED_40000; case I40E_LINK_SPEED_UNKNOWN: return SPEED_UNKNOWN;
} return SPEED_UNKNOWN;
}
/** * i40e_set_vf_link_state * @vf: pointer to the VF structure * @pfe: pointer to PF event structure * @ls: pointer to link status structure * * set a link state on a single vf
**/ staticvoid i40e_set_vf_link_state(struct i40e_vf *vf, struct virtchnl_pf_event *pfe, struct i40e_link_status *ls)
{
u8 link_status = ls->link_info & I40E_AQ_LINK_UP;
/** * i40e_vc_notify_link_state * @pf: pointer to the PF structure * * send a link status message to all VFs on a given PF
**/ void i40e_vc_notify_link_state(struct i40e_pf *pf)
{ int i;
for (i = 0; i < pf->num_alloc_vfs; i++)
i40e_vc_notify_vf_link_state(&pf->vf[i]);
}
/** * i40e_vc_notify_reset * @pf: pointer to the PF structure * * indicate a pending reset to all VFs on a given PF
**/ void i40e_vc_notify_reset(struct i40e_pf *pf)
{ struct virtchnl_pf_event pfe;
/** * i40e_vc_notify_vf_reset * @vf: pointer to the VF structure * * indicate a pending reset to the given VF
**/ void i40e_vc_notify_vf_reset(struct i40e_vf *vf)
{ struct virtchnl_pf_event pfe; int abs_vf_id;
/* validate the request */ if (!vf || vf->vf_id >= vf->pf->num_alloc_vfs) return;
/* verify if the VF is in either init or active before proceeding */ if (!test_bit(I40E_VF_STATE_INIT, &vf->vf_states) &&
!test_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states)) return;
/** * i40e_vc_reset_vf * @vf: pointer to the VF info * @notify_vf: notify vf about reset or not * Reset VF handler.
**/ void i40e_vc_reset_vf(struct i40e_vf *vf, bool notify_vf)
{ struct i40e_pf *pf = vf->pf; int i;
if (notify_vf)
i40e_vc_notify_vf_reset(vf);
/* We want to ensure that an actual reset occurs initiated after this * function was called. However, we do not want to wait forever, so * we'll give a reasonable time and print a message if we failed to * ensure a reset.
*/ for (i = 0; i < 20; i++) { /* If PF is in VFs releasing state reset VF is impossible, * so leave it.
*/ if (test_bit(__I40E_VFS_RELEASING, pf->state)) return; if (i40e_reset_vf(vf, false)) return;
usleep_range(10000, 20000);
}
if (notify_vf)
dev_warn(&vf->pf->pdev->dev, "Failed to initiate reset for VF %d after 200 milliseconds\n",
vf->vf_id); else
dev_dbg(&vf->pf->pdev->dev, "Failed to initiate reset for VF %d after 200 milliseconds\n",
vf->vf_id);
}
/** * i40e_vc_isvalid_vsi_id * @vf: pointer to the VF info * @vsi_id: VF relative VSI id * * check for the valid VSI id
**/ staticinlinebool i40e_vc_isvalid_vsi_id(struct i40e_vf *vf, u16 vsi_id)
{ struct i40e_pf *pf = vf->pf; struct i40e_vsi *vsi = i40e_find_vsi_from_id(pf, vsi_id);
return (vsi && (vsi->vf_id == vf->vf_id));
}
/** * i40e_vc_isvalid_queue_id * @vf: pointer to the VF info * @vsi_id: vsi id * @qid: vsi relative queue id * * check for the valid queue id
**/ staticinlinebool i40e_vc_isvalid_queue_id(struct i40e_vf *vf, u16 vsi_id,
u16 qid)
{ struct i40e_pf *pf = vf->pf; struct i40e_vsi *vsi = i40e_find_vsi_from_id(pf, vsi_id);
return (vsi && (qid < vsi->alloc_queue_pairs));
}
/** * i40e_vc_isvalid_vector_id * @vf: pointer to the VF info * @vector_id: VF relative vector id * * check for the valid vector id
**/ staticinlinebool i40e_vc_isvalid_vector_id(struct i40e_vf *vf, u32 vector_id)
{ struct i40e_pf *pf = vf->pf;
/** * i40e_vc_get_pf_queue_id * @vf: pointer to the VF info * @vsi_id: id of VSI as provided by the FW * @vsi_queue_id: vsi relative queue id * * return PF relative queue id
**/ static u16 i40e_vc_get_pf_queue_id(struct i40e_vf *vf, u16 vsi_id,
u8 vsi_queue_id)
{ struct i40e_pf *pf = vf->pf; struct i40e_vsi *vsi = i40e_find_vsi_from_id(pf, vsi_id);
u16 pf_queue_id = I40E_QUEUE_END_OF_LIST;
/** * i40e_get_real_pf_qid * @vf: pointer to the VF info * @vsi_id: vsi id * @queue_id: queue number * * wrapper function to get pf_queue_id handling ADq code as well
**/ static u16 i40e_get_real_pf_qid(struct i40e_vf *vf, u16 vsi_id, u16 queue_id)
{ int i;
if (vf->adq_enabled) { /* Although VF considers all the queues(can be 1 to 16) as its * own but they may actually belong to different VSIs(up to 4). * We need to find which queues belongs to which VSI.
*/ for (i = 0; i < vf->num_tc; i++) { if (queue_id < vf->ch[i].num_qps) {
vsi_id = vf->ch[i].vsi_id; break;
} /* find right queue id which is relative to a * given VSI.
*/
queue_id -= vf->ch[i].num_qps;
}
}
/* format for the RQCTL & TQCTL regs is same */
reg = (vector_id) |
(qtype << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
(pf_queue_id << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |
FIELD_PREP(I40E_QINT_RQCTL_ITR_INDX_MASK, itr_idx);
wr32(hw, reg_idx, reg);
}
/* if the vf is running in polling mode and using interrupt zero, * need to disable auto-mask on enabling zero interrupt for VFs.
*/ if ((vf->driver_caps & VIRTCHNL_VF_OFFLOAD_RX_POLLING) &&
(vector_id == 0)) {
reg = rd32(hw, I40E_GLINT_CTL); if (!(reg & I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK)) {
reg |= I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
wr32(hw, I40E_GLINT_CTL, reg);
}
}
/** * i40e_config_rdma_qvlist * @vf: pointer to the VF info * @qvlist_info: queue and vector list * * Return 0 on success or < 0 on error
**/ staticint
i40e_config_rdma_qvlist(struct i40e_vf *vf, struct virtchnl_rdma_qvlist_info *qvlist_info)
{ struct i40e_pf *pf = vf->pf; struct i40e_hw *hw = &pf->hw; struct virtchnl_rdma_qv_info *qv_info;
u32 v_idx, i, reg_idx, reg;
u32 next_q_idx, next_q_type;
size_t size;
u32 msix_vf; int ret = 0;
msix_vf = pf->hw.func_caps.num_msix_vectors_vf;
if (qvlist_info->num_vectors > msix_vf) {
dev_warn(&pf->pdev->dev, "Incorrect number of iwarp vectors %u. Maximum %u allowed.\n",
qvlist_info->num_vectors,
msix_vf);
ret = -EINVAL; goto err_out;
}
msix_vf = pf->hw.func_caps.num_msix_vectors_vf; for (i = 0; i < qvlist_info->num_vectors; i++) {
qv_info = &qvlist_info->qv_info[i];
/* Validate vector id belongs to this vf */ if (!i40e_vc_isvalid_vector_id(vf, qv_info->v_idx)) {
ret = -EINVAL; goto err_free;
}
v_idx = qv_info->v_idx;
vf->qvlist_info->qv_info[i] = *qv_info;
reg_idx = ((msix_vf - 1) * vf->vf_id) + (v_idx - 1); /* We might be sharing the interrupt, so get the first queue * index and type, push it down the list by adding the new * queue on top. Also link it with the new queue in CEQCTL.
*/
reg = rd32(hw, I40E_VPINT_LNKLSTN(reg_idx));
next_q_idx = FIELD_GET(I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK,
reg);
next_q_type = FIELD_GET(I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK,
reg);
/** * i40e_config_vsi_tx_queue * @vf: pointer to the VF info * @vsi_id: id of VSI as provided by the FW * @vsi_queue_id: vsi relative queue index * @info: config. info * * configure tx queue
**/ staticint i40e_config_vsi_tx_queue(struct i40e_vf *vf, u16 vsi_id,
u16 vsi_queue_id, struct virtchnl_txq_info *info)
{ struct i40e_pf *pf = vf->pf; struct i40e_hw *hw = &pf->hw; struct i40e_hmc_obj_txq tx_ctx; struct i40e_vsi *vsi;
u16 pf_queue_id;
u32 qtx_ctl; int ret = 0;
if (!i40e_vc_isvalid_vsi_id(vf, info->vsi_id)) {
ret = -ENOENT; goto error_context;
}
pf_queue_id = i40e_vc_get_pf_queue_id(vf, vsi_id, vsi_queue_id);
vsi = i40e_find_vsi_from_id(pf, vsi_id); if (!vsi) {
ret = -ENOENT; goto error_context;
}
/* clear the context structure first */
memset(&tx_ctx, 0, sizeof(struct i40e_hmc_obj_txq));
/* only set the required fields */
tx_ctx.base = info->dma_ring_addr / 128;
/* ring_len has to be multiple of 8 */ if (!IS_ALIGNED(info->ring_len, 8) ||
info->ring_len > I40E_MAX_NUM_DESCRIPTORS_XL710) {
ret = -EINVAL; goto error_context;
}
tx_ctx.qlen = info->ring_len;
tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[0]);
tx_ctx.rdylist_act = 0;
tx_ctx.head_wb_ena = info->headwb_enabled;
tx_ctx.head_wb_addr = info->dma_headwb_addr;
/* clear the context in the HMC */
ret = i40e_clear_lan_tx_queue_context(hw, pf_queue_id); if (ret) {
dev_err(&pf->pdev->dev, "Failed to clear VF LAN Tx queue context %d, error: %d\n",
pf_queue_id, ret);
ret = -ENOENT; goto error_context;
}
/* set the context in the HMC */
ret = i40e_set_lan_tx_queue_context(hw, pf_queue_id, &tx_ctx); if (ret) {
dev_err(&pf->pdev->dev, "Failed to set VF LAN Tx queue context %d error: %d\n",
pf_queue_id, ret);
ret = -ENOENT; goto error_context;
}
/* associate this queue with the PCI VF function */
qtx_ctl = I40E_QTX_CTL_VF_QUEUE;
qtx_ctl |= FIELD_PREP(I40E_QTX_CTL_PF_INDX_MASK, hw->pf_id);
qtx_ctl |= FIELD_PREP(I40E_QTX_CTL_VFVM_INDX_MASK,
vf->vf_id + hw->func_caps.vf_base_id);
wr32(hw, I40E_QTX_CTL(pf_queue_id), qtx_ctl);
i40e_flush(hw);
error_context: return ret;
}
/** * i40e_config_vsi_rx_queue * @vf: pointer to the VF info * @vsi_id: id of VSI as provided by the FW * @vsi_queue_id: vsi relative queue index * @info: config. info * * configure rx queue
**/ staticint i40e_config_vsi_rx_queue(struct i40e_vf *vf, u16 vsi_id,
u16 vsi_queue_id, struct virtchnl_rxq_info *info)
{
u16 pf_queue_id = i40e_vc_get_pf_queue_id(vf, vsi_id, vsi_queue_id); struct i40e_pf *pf = vf->pf; struct i40e_vsi *vsi = pf->vsi[vf->lan_vsi_idx]; struct i40e_hw *hw = &pf->hw; struct i40e_hmc_obj_rxq rx_ctx; int ret = 0;
/* clear the context structure first */
memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
/* only set the required fields */
rx_ctx.base = info->dma_ring_addr / 128;
/* ring_len has to be multiple of 32 */ if (!IS_ALIGNED(info->ring_len, 32) ||
info->ring_len > I40E_MAX_NUM_DESCRIPTORS_XL710) {
ret = -EINVAL; goto error_param;
}
rx_ctx.qlen = info->ring_len;
/* clear the context in the HMC */
ret = i40e_clear_lan_rx_queue_context(hw, pf_queue_id); if (ret) {
dev_err(&pf->pdev->dev, "Failed to clear VF LAN Rx queue context %d, error: %d\n",
pf_queue_id, ret);
ret = -ENOENT; goto error_param;
}
/* set the context in the HMC */
ret = i40e_set_lan_rx_queue_context(hw, pf_queue_id, &rx_ctx); if (ret) {
dev_err(&pf->pdev->dev, "Failed to set VF LAN Rx queue context %d error: %d\n",
pf_queue_id, ret);
ret = -ENOENT; goto error_param;
}
error_param: return ret;
}
/** * i40e_alloc_vsi_res * @vf: pointer to the VF info * @idx: VSI index, applies only for ADq mode, zero otherwise * * alloc VF vsi context & resources
**/ staticint i40e_alloc_vsi_res(struct i40e_vf *vf, u8 idx)
{ struct i40e_mac_filter *f = NULL; struct i40e_vsi *main_vsi, *vsi; struct i40e_pf *pf = vf->pf;
u64 max_tx_rate = 0; int ret = 0;
main_vsi = i40e_pf_get_main_vsi(pf);
vsi = i40e_vsi_setup(pf, I40E_VSI_SRIOV, main_vsi->seid, vf->vf_id);
if (!vsi) {
dev_err(&pf->pdev->dev, "add vsi failed for VF %d, aq_err %d\n",
vf->vf_id, pf->hw.aq.asq_last_status);
ret = -ENOENT; goto error_alloc_vsi_res;
}
if (!idx) {
u64 hashcfg = i40e_pf_get_default_rss_hashcfg(pf);
u8 broadcast[ETH_ALEN];
vf->lan_vsi_idx = vsi->idx;
vf->lan_vsi_id = vsi->id; /* If the port VLAN has been configured and then the * VF driver was removed then the VSI port VLAN * configuration was destroyed. Check if there is * a port VLAN and restore the VSI configuration if * needed.
*/ if (vf->port_vlan_id)
i40e_vsi_add_pvid(vsi, vf->port_vlan_id);
spin_lock_bh(&vsi->mac_filter_hash_lock); if (is_valid_ether_addr(vf->default_lan_addr.addr)) {
f = i40e_add_mac_filter(vsi,
vf->default_lan_addr.addr); if (!f)
dev_info(&pf->pdev->dev, "Could not add MAC filter %pM for VF %d\n",
vf->default_lan_addr.addr, vf->vf_id);
}
eth_broadcast_addr(broadcast);
f = i40e_add_mac_filter(vsi, broadcast); if (!f)
dev_info(&pf->pdev->dev, "Could not allocate VF broadcast filter\n");
spin_unlock_bh(&vsi->mac_filter_hash_lock);
wr32(&pf->hw, I40E_VFQF_HENA1(0, vf->vf_id), (u32)hashcfg);
wr32(&pf->hw, I40E_VFQF_HENA1(1, vf->vf_id),
(u32)(hashcfg >> 32)); /* program mac filter only for VF VSI */
ret = i40e_sync_vsi_filters(vsi); if (ret)
dev_err(&pf->pdev->dev, "Unable to program ucast filters\n");
}
/* storing VSI index and id for ADq and don't apply the mac filter */ if (vf->adq_enabled) {
vf->ch[idx].vsi_idx = vsi->idx;
vf->ch[idx].vsi_id = vsi->id;
}
/* Set VF bandwidth if specified */ if (vf->tx_rate) {
max_tx_rate = vf->tx_rate;
} elseif (vf->ch[idx].max_tx_rate) {
max_tx_rate = vf->ch[idx].max_tx_rate;
}
if (max_tx_rate) {
max_tx_rate = div_u64(max_tx_rate, I40E_BW_CREDIT_DIVISOR);
ret = i40e_aq_config_vsi_bw_limit(&pf->hw, vsi->seid,
max_tx_rate, 0, NULL); if (ret)
dev_err(&pf->pdev->dev, "Unable to set tx rate, VF %d, error code %d.\n",
vf->vf_id, ret);
}
error_alloc_vsi_res: return ret;
}
/** * i40e_map_pf_queues_to_vsi * @vf: pointer to the VF info * * PF maps LQPs to a VF by programming VSILAN_QTABLE & VPLAN_QTABLE. This * function takes care of first part VSILAN_QTABLE, mapping pf queues to VSI.
**/ staticvoid i40e_map_pf_queues_to_vsi(struct i40e_vf *vf)
{ struct i40e_pf *pf = vf->pf; struct i40e_hw *hw = &pf->hw;
u32 reg, num_tc = 1; /* VF has at least one traffic class */
u16 vsi_id, qps; int i, j;
if (vf->adq_enabled)
num_tc = vf->num_tc;
for (i = 0; i < num_tc; i++) { if (vf->adq_enabled) {
qps = vf->ch[i].num_qps;
vsi_id = vf->ch[i].vsi_id;
} else {
qps = pf->vsi[vf->lan_vsi_idx]->alloc_queue_pairs;
vsi_id = vf->lan_vsi_id;
}
/** * i40e_map_pf_to_vf_queues * @vf: pointer to the VF info * * PF maps LQPs to a VF by programming VSILAN_QTABLE & VPLAN_QTABLE. This * function takes care of the second part VPLAN_QTABLE & completes VF mappings.
**/ staticvoid i40e_map_pf_to_vf_queues(struct i40e_vf *vf)
{ struct i40e_pf *pf = vf->pf; struct i40e_hw *hw = &pf->hw;
u32 reg, total_qps = 0;
u32 qps, num_tc = 1; /* VF has at least one traffic class */
u16 vsi_id, qid; int i, j;
if (vf->adq_enabled)
num_tc = vf->num_tc;
for (i = 0; i < num_tc; i++) { if (vf->adq_enabled) {
qps = vf->ch[i].num_qps;
vsi_id = vf->ch[i].vsi_id;
} else {
qps = pf->vsi[vf->lan_vsi_idx]->alloc_queue_pairs;
vsi_id = vf->lan_vsi_id;
}
/* Tell the hardware we're using noncontiguous mapping. HW requires * that VF queues be mapped using this method, even when they are * contiguous in real life
*/
i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vf->lan_vsi_id),
I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
/** * i40e_disable_vf_mappings * @vf: pointer to the VF info * * disable VF mappings
**/ staticvoid i40e_disable_vf_mappings(struct i40e_vf *vf)
{ struct i40e_pf *pf = vf->pf; struct i40e_hw *hw = &pf->hw; int i;
/* disable qp mappings */
wr32(hw, I40E_VPLAN_MAPENA(vf->vf_id), 0); for (i = 0; i < I40E_MAX_VSI_QP; i++)
wr32(hw, I40E_VPLAN_QTABLE(i, vf->vf_id),
I40E_QUEUE_END_OF_LIST);
i40e_flush(hw);
}
/** * i40e_free_vf_res * @vf: pointer to the VF info * * free VF resources
**/ staticvoid i40e_free_vf_res(struct i40e_vf *vf)
{ struct i40e_pf *pf = vf->pf; struct i40e_hw *hw = &pf->hw;
u32 reg_idx, reg; int i, j, msix_vf;
/* Start by disabling VF's configuration API to prevent the OS from * accessing the VF's VSI after it's freed / invalidated.
*/
clear_bit(I40E_VF_STATE_INIT, &vf->vf_states);
/* It's possible the VF had requeuested more queues than the default so * do the accounting here when we're about to free them.
*/ if (vf->num_queue_pairs > I40E_DEFAULT_QUEUES_PER_VF) {
pf->queues_left += vf->num_queue_pairs -
I40E_DEFAULT_QUEUES_PER_VF;
}
/* free vsi & disconnect it from the parent uplink */ if (vf->lan_vsi_idx) {
i40e_vsi_release(pf->vsi[vf->lan_vsi_idx]);
vf->lan_vsi_idx = 0;
vf->lan_vsi_id = 0;
}
/* do the accounting and remove additional ADq VSI's */ if (vf->adq_enabled && vf->ch[0].vsi_idx) { for (j = 0; j < vf->num_tc; j++) { /* At this point VSI0 is already released so don't * release it again and only clear their values in * structure variables
*/ if (j)
i40e_vsi_release(pf->vsi[vf->ch[j].vsi_idx]);
vf->ch[j].vsi_idx = 0;
vf->ch[j].vsi_id = 0;
}
}
msix_vf = pf->hw.func_caps.num_msix_vectors_vf;
/* disable interrupts so the VF starts in a known state */ for (i = 0; i < msix_vf; i++) { /* format is same for both registers */ if (0 == i)
reg_idx = I40E_VFINT_DYN_CTL0(vf->vf_id); else
reg_idx = I40E_VFINT_DYN_CTLN(((msix_vf - 1) *
(vf->vf_id))
+ (i - 1));
wr32(hw, reg_idx, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
i40e_flush(hw);
}
/* clear the irq settings */ for (i = 0; i < msix_vf; i++) { /* format is same for both registers */ if (0 == i)
reg_idx = I40E_VPINT_LNKLST0(vf->vf_id); else
reg_idx = I40E_VPINT_LNKLSTN(((msix_vf - 1) *
(vf->vf_id))
+ (i - 1));
reg = (I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK |
I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
wr32(hw, reg_idx, reg);
i40e_flush(hw);
} /* reset some of the state variables keeping track of the resources */
vf->num_queue_pairs = 0;
clear_bit(I40E_VF_STATE_MC_PROMISC, &vf->vf_states);
clear_bit(I40E_VF_STATE_UC_PROMISC, &vf->vf_states);
}
/** * i40e_alloc_vf_res * @vf: pointer to the VF info * * allocate VF resources
**/ staticint i40e_alloc_vf_res(struct i40e_vf *vf)
{ struct i40e_pf *pf = vf->pf; int total_queue_pairs = 0; int ret, idx;
/* allocate hw vsi context & associated resources */
ret = i40e_alloc_vsi_res(vf, 0); if (ret) goto error_alloc;
total_queue_pairs += pf->vsi[vf->lan_vsi_idx]->alloc_queue_pairs;
/* allocate additional VSIs based on tc information for ADq */ if (vf->adq_enabled) { if (pf->queues_left >=
(I40E_MAX_VF_QUEUES - I40E_DEFAULT_QUEUES_PER_VF)) { /* TC 0 always belongs to VF VSI */ for (idx = 1; idx < vf->num_tc; idx++) {
ret = i40e_alloc_vsi_res(vf, idx); if (ret) goto error_alloc;
} /* send correct number of queues */
total_queue_pairs = I40E_MAX_VF_QUEUES;
} else {
dev_info(&pf->pdev->dev, "VF %d: Not enough queues to allocate, disabling ADq\n",
vf->vf_id);
vf->adq_enabled = false;
}
}
/* We account for each VF to get a default number of queue pairs. If * the VF has now requested more, we need to account for that to make * certain we never request more queues than we actually have left in * HW.
*/ if (total_queue_pairs > I40E_DEFAULT_QUEUES_PER_VF)
pf->queues_left -=
total_queue_pairs - I40E_DEFAULT_QUEUES_PER_VF;
if (vf->trusted)
set_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps); else
clear_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps);
/* store the total qps number for the runtime * VF req validation
*/
vf->num_queue_pairs = total_queue_pairs;
/* VF is now completely initialized */
set_bit(I40E_VF_STATE_INIT, &vf->vf_states);
error_alloc: if (ret)
i40e_free_vf_res(vf);
return ret;
}
#define VF_DEVICE_STATUS 0xAA #define VF_TRANS_PENDING_MASK 0x20 /** * i40e_quiesce_vf_pci * @vf: pointer to the VF structure * * Wait for VF PCI transactions to be cleared after reset. Returns -EIO * if the transactions never clear.
**/ staticint i40e_quiesce_vf_pci(struct i40e_vf *vf)
{ struct i40e_pf *pf = vf->pf; struct i40e_hw *hw = &pf->hw; int vf_abs_id, i;
u32 reg;
vf_abs_id = vf->vf_id + hw->func_caps.vf_base_id;
wr32(hw, I40E_PF_PCI_CIAA,
VF_DEVICE_STATUS | (vf_abs_id << I40E_PF_PCI_CIAA_VF_NUM_SHIFT)); for (i = 0; i < 100; i++) {
reg = rd32(hw, I40E_PF_PCI_CIAD); if ((reg & VF_TRANS_PENDING_MASK) == 0) return 0;
udelay(1);
} return -EIO;
}
/** * __i40e_getnum_vf_vsi_vlan_filters * @vsi: pointer to the vsi * * called to get the number of VLANs offloaded on this VF
**/ staticint __i40e_getnum_vf_vsi_vlan_filters(struct i40e_vsi *vsi)
{ struct i40e_mac_filter *f;
u16 num_vlans = 0, bkt;
/** * i40e_getnum_vf_vsi_vlan_filters * @vsi: pointer to the vsi * * wrapper for __i40e_getnum_vf_vsi_vlan_filters() with spinlock held
**/ staticint i40e_getnum_vf_vsi_vlan_filters(struct i40e_vsi *vsi)
{ int num_vlans;
/** * i40e_get_vlan_list_sync * @vsi: pointer to the VSI * @num_vlans: number of VLANs in mac_filter_hash, returned to caller * @vlan_list: list of VLANs present in mac_filter_hash, returned to caller. * This array is allocated here, but has to be freed in caller. * * Called to get number of VLANs and VLAN list present in mac_filter_hash.
**/ staticvoid i40e_get_vlan_list_sync(struct i40e_vsi *vsi, u16 *num_vlans,
s16 **vlan_list)
{ struct i40e_mac_filter *f; int i = 0; int bkt;
/** * i40e_set_vsi_promisc * @vf: pointer to the VF struct * @seid: VSI number * @multi_enable: set MAC L2 layer multicast promiscuous enable/disable * for a given VLAN * @unicast_enable: set MAC L2 layer unicast promiscuous enable/disable * for a given VLAN * @vl: List of VLANs - apply filter for given VLANs * @num_vlans: Number of elements in @vl
**/ staticint
i40e_set_vsi_promisc(struct i40e_vf *vf, u16 seid, bool multi_enable, bool unicast_enable, s16 *vl, u16 num_vlans)
{ struct i40e_pf *pf = vf->pf; struct i40e_hw *hw = &pf->hw; int aq_ret, aq_tmp = 0; int i;
/* No VLAN to set promisc on, set on VSI */ if (!num_vlans || !vl) {
aq_ret = i40e_aq_set_vsi_multicast_promiscuous(hw, seid,
multi_enable,
NULL); if (aq_ret) { int aq_err = pf->hw.aq.asq_last_status;
dev_err(&pf->pdev->dev, "VF %d failed to set multicast promiscuous mode err %pe aq_err %s\n",
vf->vf_id, ERR_PTR(aq_ret),
libie_aq_str(aq_err));
if (aq_ret) { int aq_err = pf->hw.aq.asq_last_status;
dev_err(&pf->pdev->dev, "VF %d failed to set unicast promiscuous mode err %pe aq_err %s\n",
vf->vf_id, ERR_PTR(aq_ret),
libie_aq_str(aq_err));
}
return aq_ret;
}
for (i = 0; i < num_vlans; i++) {
aq_ret = i40e_aq_set_vsi_mc_promisc_on_vlan(hw, seid,
multi_enable,
vl[i], NULL); if (aq_ret) { int aq_err = pf->hw.aq.asq_last_status;
dev_err(&pf->pdev->dev, "VF %d failed to set multicast promiscuous mode err %pe aq_err %s\n",
vf->vf_id, ERR_PTR(aq_ret),
libie_aq_str(aq_err));
if (!aq_tmp)
aq_tmp = aq_ret;
}
aq_ret = i40e_aq_set_vsi_uc_promisc_on_vlan(hw, seid,
unicast_enable,
vl[i], NULL); if (aq_ret) { int aq_err = pf->hw.aq.asq_last_status;
dev_err(&pf->pdev->dev, "VF %d failed to set unicast promiscuous mode err %pe aq_err %s\n",
vf->vf_id, ERR_PTR(aq_ret),
libie_aq_str(aq_err));
if (!aq_tmp)
aq_tmp = aq_ret;
}
}
if (aq_tmp)
aq_ret = aq_tmp;
return aq_ret;
}
/** * i40e_config_vf_promiscuous_mode * @vf: pointer to the VF info * @vsi_id: VSI id * @allmulti: set MAC L2 layer multicast promiscuous enable/disable * @alluni: set MAC L2 layer unicast promiscuous enable/disable * * Called from the VF to configure the promiscuous mode of * VF vsis and from the VF reset path to reset promiscuous mode.
**/ staticint i40e_config_vf_promiscuous_mode(struct i40e_vf *vf,
u16 vsi_id, bool allmulti, bool alluni)
{ struct i40e_pf *pf = vf->pf; struct i40e_vsi *vsi; int aq_ret = 0;
u16 num_vlans;
s16 *vl;
vsi = i40e_find_vsi_from_id(pf, vsi_id); if (!i40e_vc_isvalid_vsi_id(vf, vsi_id) || !vsi) return -EINVAL;
/* no VLANs to set on, set on VSI */
aq_ret = i40e_set_vsi_promisc(vf, vsi->seid, allmulti, alluni,
NULL, 0); return aq_ret;
}
/** * i40e_sync_vfr_reset * @hw: pointer to hw struct * @vf_id: VF identifier * * Before trigger hardware reset, we need to know if no other process has * reserved the hardware for any reset operations. This check is done by * examining the status of the RSTAT1 register used to signal the reset.
**/ staticint i40e_sync_vfr_reset(struct i40e_hw *hw, int vf_id)
{
u32 reg; int i;
for (i = 0; i < I40E_VFR_WAIT_COUNT; i++) {
reg = rd32(hw, I40E_VFINT_ICR0_ENA(vf_id)) &
I40E_VFINT_ICR0_ADMINQ_MASK; if (reg) return 0;
usleep_range(100, 200);
}
return -EAGAIN;
}
/** * i40e_trigger_vf_reset * @vf: pointer to the VF structure * @flr: VFLR was issued or not * * Trigger hardware to start a reset for a particular VF. Expects the caller * to wait the proper amount of time to allow hardware to reset the VF before * it cleans up and restores VF functionality.
**/ staticvoid i40e_trigger_vf_reset(struct i40e_vf *vf, bool flr)
{ struct i40e_pf *pf = vf->pf; struct i40e_hw *hw = &pf->hw;
u32 reg, reg_idx, bit_idx; bool vf_active;
u32 radq;
/* warn the VF */
vf_active = test_and_clear_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states);
/* Disable VF's configuration API during reset. The flag is re-enabled * in i40e_alloc_vf_res(), when it's safe again to access VF's VSI. * It's normally disabled in i40e_free_vf_res(), but it's safer * to do it earlier to give some time to finish to any VF config * functions that may still be running at this point.
*/
clear_bit(I40E_VF_STATE_INIT, &vf->vf_states);
clear_bit(I40E_VF_STATE_RESOURCES_LOADED, &vf->vf_states);
/* In the case of a VFLR, the HW has already reset the VF and we * just need to clean up, so don't hit the VFRTRIG register.
*/ if (!flr) { /* Sync VFR reset before trigger next one */
radq = rd32(hw, I40E_VFINT_ICR0_ENA(vf->vf_id)) &
I40E_VFINT_ICR0_ADMINQ_MASK; if (vf_active && !radq) /* waiting for finish reset by virtual driver */ if (i40e_sync_vfr_reset(hw, vf->vf_id))
dev_info(&pf->pdev->dev, "Reset VF %d never finished\n",
vf->vf_id);
/* Reset VF using VPGEN_VFRTRIG reg. It is also setting * in progress state in rstat1 register.
*/
reg = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id));
reg |= I40E_VPGEN_VFRTRIG_VFSWR_MASK;
wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id), reg);
i40e_flush(hw);
} /* clear the VFLR bit in GLGEN_VFLRSTAT */
reg_idx = (hw->func_caps.vf_base_id + vf->vf_id) / 32;
bit_idx = (hw->func_caps.vf_base_id + vf->vf_id) % 32;
wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));
i40e_flush(hw);
if (i40e_quiesce_vf_pci(vf))
dev_err(&pf->pdev->dev, "VF %d PCI transactions stuck\n",
vf->vf_id);
}
/** * i40e_cleanup_reset_vf * @vf: pointer to the VF structure * * Cleanup a VF after the hardware reset is finished. Expects the caller to * have verified whether the reset is finished properly, and ensure the * minimum amount of wait time has passed.
**/ staticvoid i40e_cleanup_reset_vf(struct i40e_vf *vf)
{ struct i40e_pf *pf = vf->pf; struct i40e_hw *hw = &pf->hw;
u32 reg;
/* disable promisc modes in case they were enabled */
i40e_config_vf_promiscuous_mode(vf, vf->lan_vsi_id, false, false);
/* free VF resources to begin resetting the VSI state */
i40e_free_vf_res(vf);
/* Enable hardware by clearing the reset bit in the VPGEN_VFRTRIG reg. * By doing this we allow HW to access VF memory at any point. If we * did it any sooner, HW could access memory while it was being freed * in i40e_free_vf_res(), causing an IOMMU fault. * * On the other hand, this needs to be done ASAP, because the VF driver * is waiting for this to happen and may report a timeout. It's * harmless, but it gets logged into Guest OS kernel log, so best avoid * it.
*/
reg = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id));
reg &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK;
wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id), reg);
/* reallocate VF resources to finish resetting the VSI state */ if (!i40e_alloc_vf_res(vf)) { int abs_vf_id = vf->vf_id + hw->func_caps.vf_base_id;
i40e_enable_vf_mappings(vf);
set_bit(I40E_VF_STATE_ACTIVE, &vf->vf_states);
clear_bit(I40E_VF_STATE_DISABLED, &vf->vf_states); /* Do not notify the client during VF init */ if (!test_and_clear_bit(I40E_VF_STATE_PRE_ENABLE,
&vf->vf_states))
i40e_notify_client_of_vf_reset(pf, abs_vf_id);
vf->num_vlan = 0;
}
/* Tell the VF driver the reset is done. This needs to be done only * after VF has been fully initialized, because the VF driver may * request resources immediately after setting this flag.
*/
wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_id), VIRTCHNL_VFR_VFACTIVE);
}
/** * i40e_reset_vf * @vf: pointer to the VF structure * @flr: VFLR was issued or not * * Return: True if reset was performed successfully or if resets are disabled. * False if reset is already in progress.
**/ bool i40e_reset_vf(struct i40e_vf *vf, bool flr)
{ struct i40e_pf *pf = vf->pf; struct i40e_hw *hw = &pf->hw; bool rsd = false;
u32 reg; int i;
if (test_bit(__I40E_VF_RESETS_DISABLED, pf->state)) returntrue;
/* Bail out if VFs are disabled. */ if (test_bit(__I40E_VF_DISABLE, pf->state)) returntrue;
/* If VF is being reset already we don't need to continue. */ if (test_and_set_bit(I40E_VF_STATE_RESETTING, &vf->vf_states)) returnfalse;
i40e_trigger_vf_reset(vf, flr);
/* poll VPGEN_VFRSTAT reg to make sure * that reset is complete
*/ for (i = 0; i < 10; i++) { /* VF reset requires driver to first reset the VF and then * poll the status register to make sure that the reset * completed successfully. Due to internal HW FIFO flushes, * we must wait 10ms before the register will be valid.
*/
usleep_range(10000, 20000);
reg = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_id)); if (reg & I40E_VPGEN_VFRSTAT_VFRD_MASK) {
rsd = true; break;
}
}
if (flr)
usleep_range(10000, 20000);
if (!rsd)
dev_err(&pf->pdev->dev, "VF reset check timeout on VF %d\n",
vf->vf_id);
usleep_range(10000, 20000);
/* On initial reset, we don't have any queues to disable */ if (vf->lan_vsi_idx != 0)
i40e_vsi_stop_rings(pf->vsi[vf->lan_vsi_idx]);
/** * i40e_reset_all_vfs * @pf: pointer to the PF structure * @flr: VFLR was issued or not * * Reset all allocated VFs in one go. First, tell the hardware to reset each * VF, then do all the waiting in one chunk, and finally finish restoring each * VF after the wait. This is useful during PF routines which need to reset * all VFs, as otherwise it must perform these resets in a serialized fashion. * * Returns true if any VFs were reset, and false otherwise.
**/ bool i40e_reset_all_vfs(struct i40e_pf *pf, bool flr)
{ struct i40e_hw *hw = &pf->hw; struct i40e_vf *vf;
u32 reg; int i;
/* If we don't have any VFs, then there is nothing to reset */ if (!pf->num_alloc_vfs) returnfalse;
/* If VFs have been disabled, there is no need to reset */ if (test_and_set_bit(__I40E_VF_DISABLE, pf->state)) returnfalse;
/* Begin reset on all VFs at once */ for (vf = &pf->vf[0]; vf < &pf->vf[pf->num_alloc_vfs]; ++vf) { /* If VF is being reset no need to trigger reset again */ if (!test_bit(I40E_VF_STATE_RESETTING, &vf->vf_states))
i40e_trigger_vf_reset(vf, flr);
}
/* HW requires some time to make sure it can flush the FIFO for a VF * when it resets it. Poll the VPGEN_VFRSTAT register for each VF in * sequence to make sure that it has completed. We'll keep track of * the VFs using a simple iterator that increments once that VF has * finished resetting.
*/ for (i = 0, vf = &pf->vf[0]; i < 10 && vf < &pf->vf[pf->num_alloc_vfs]; ++i) {
usleep_range(10000, 20000);
/* Check each VF in sequence, beginning with the VF to fail * the previous check.
*/ while (vf < &pf->vf[pf->num_alloc_vfs]) { if (!test_bit(I40E_VF_STATE_RESETTING, &vf->vf_states)) {
reg = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_id)); if (!(reg & I40E_VPGEN_VFRSTAT_VFRD_MASK)) break;
}
/* If the current VF has finished resetting, move on * to the next VF in sequence.
*/
++vf;
}
}
if (flr)
usleep_range(10000, 20000);
/* Display a warning if at least one VF didn't manage to reset in * time, but continue on with the operation.
*/ if (vf < &pf->vf[pf->num_alloc_vfs])
dev_err(&pf->pdev->dev, "VF reset check timeout on VF %d\n",
vf->vf_id);
usleep_range(10000, 20000);
/* Begin disabling all the rings associated with VFs, but do not wait * between each VF.
*/ for (vf = &pf->vf[0]; vf < &pf->vf[pf->num_alloc_vfs]; ++vf) { /* On initial reset, we don't have any queues to disable */ if (vf->lan_vsi_idx == 0) continue;
/* If VF is reset in another thread just continue */ if (test_bit(I40E_VF_STATE_RESETTING, &vf->vf_states)) continue;
/* Now that we've notified HW to disable all of the VF rings, wait * until they finish.
*/ for (vf = &pf->vf[0]; vf < &pf->vf[pf->num_alloc_vfs]; ++vf) { /* On initial reset, we don't have any queues to disable */ if (vf->lan_vsi_idx == 0) continue;
/* If VF is reset in another thread just continue */ if (test_bit(I40E_VF_STATE_RESETTING, &vf->vf_states)) continue;
/* Hw may need up to 50ms to finish disabling the RX queues. We * minimize the wait by delaying only once for all VFs.
*/
mdelay(50);
/* Finish the reset on each VF */ for (vf = &pf->vf[0]; vf < &pf->vf[pf->num_alloc_vfs]; ++vf) { /* If VF is reset in another thread just continue */ if (test_bit(I40E_VF_STATE_RESETTING, &vf->vf_states)) continue;
/** * i40e_free_vfs * @pf: pointer to the PF structure * * free VF resources
**/ void i40e_free_vfs(struct i40e_pf *pf)
{ struct i40e_hw *hw = &pf->hw;
u32 reg_idx, bit_idx; int i, tmp, vf_id;
if (!pf->vf) return;
set_bit(__I40E_VFS_RELEASING, pf->state); while (test_and_set_bit(__I40E_VF_DISABLE, pf->state))
usleep_range(1000, 2000);
i40e_notify_client_of_vf_enable(pf, 0);
/* Disable IOV before freeing resources. This lets any VF drivers * running in the host get themselves cleaned up before we yank * the carpet out from underneath their feet.
*/ if (!pci_vfs_assigned(pf->pdev))
pci_disable_sriov(pf->pdev); else
dev_warn(&pf->pdev->dev, "VFs are assigned - not disabling SR-IOV\n");
/* Amortize wait time by stopping all VFs at the same time */ for (i = 0; i < pf->num_alloc_vfs; i++) { if (test_bit(I40E_VF_STATE_INIT, &pf->vf[i].vf_states)) continue;
/* free up VF resources */
tmp = pf->num_alloc_vfs;
pf->num_alloc_vfs = 0; for (i = 0; i < tmp; i++) { if (test_bit(I40E_VF_STATE_INIT, &pf->vf[i].vf_states))
i40e_free_vf_res(&pf->vf[i]); /* disable qp mappings */
i40e_disable_vf_mappings(&pf->vf[i]);
}
kfree(pf->vf);
pf->vf = NULL;
/* This check is for when the driver is unloaded while VFs are * assigned. Setting the number of VFs to 0 through sysfs is caught * before this function ever gets called.
*/ if (!pci_vfs_assigned(pf->pdev)) { /* Acknowledge VFLR for all VFS. Without this, VFs will fail to * work correctly when SR-IOV gets re-enabled.
*/ for (vf_id = 0; vf_id < tmp; vf_id++) {
reg_idx = (hw->func_caps.vf_base_id + vf_id) / 32;
bit_idx = (hw->func_caps.vf_base_id + vf_id) % 32;
wr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));
}
}
clear_bit(__I40E_VF_DISABLE, pf->state);
clear_bit(__I40E_VFS_RELEASING, pf->state);
}
#ifdef CONFIG_PCI_IOV /** * i40e_alloc_vfs * @pf: pointer to the PF structure * @num_alloc_vfs: number of VFs to allocate * * allocate VF resources
**/ int i40e_alloc_vfs(struct i40e_pf *pf, u16 num_alloc_vfs)
{ struct i40e_vf *vfs; int i, ret = 0;
/* Disable interrupt 0 so we don't try to handle the VFLR. */
i40e_irq_dynamic_disable_icr0(pf);
/* Check to see if we're just allocating resources for extant VFs */ if (pci_num_vf(pf->pdev) != num_alloc_vfs) {
ret = pci_enable_sriov(pf->pdev, num_alloc_vfs); if (ret) {
clear_bit(I40E_FLAG_VEB_MODE_ENA, pf->flags);
pf->num_alloc_vfs = 0; goto err_iov;
}
} /* allocate memory */
vfs = kcalloc(num_alloc_vfs, sizeof(struct i40e_vf), GFP_KERNEL); if (!vfs) {
ret = -ENOMEM; goto err_alloc;
}
pf->vf = vfs;
/* apply default profile */ for (i = 0; i < num_alloc_vfs; i++) {
vfs[i].pf = pf;
vfs[i].parent_type = I40E_SWITCH_ELEMENT_TYPE_VEB;
vfs[i].vf_id = i;
#endif /** * i40e_pci_sriov_enable * @pdev: pointer to a pci_dev structure * @num_vfs: number of VFs to allocate * * Enable or change the number of VFs
**/ staticint i40e_pci_sriov_enable(struct pci_dev *pdev, int num_vfs)
{ #ifdef CONFIG_PCI_IOV struct i40e_pf *pf = pci_get_drvdata(pdev); int pre_existing_vfs = pci_num_vf(pdev); int err = 0;
if (test_bit(__I40E_TESTING, pf->state)) {
dev_warn(&pdev->dev, "Cannot enable SR-IOV virtual functions while the device is undergoing diagnostic testing\n");
err = -EPERM; goto err_out;
}
/** * i40e_pci_sriov_configure * @pdev: pointer to a pci_dev structure * @num_vfs: number of VFs to allocate * * Enable or change the number of VFs. Called when the user updates the number * of VFs in sysfs.
**/ int i40e_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
{ struct i40e_pf *pf = pci_get_drvdata(pdev); int ret = 0;
if (test_and_set_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state)) {
dev_warn(&pdev->dev, "Unable to configure VFs, other operation is pending.\n"); return -EAGAIN;
}
if (num_vfs) { if (!test_bit(I40E_FLAG_VEB_MODE_ENA, pf->flags)) {
set_bit(I40E_FLAG_VEB_MODE_ENA, pf->flags);
i40e_do_reset_safe(pf, I40E_PF_RESET_AND_REBUILD_FLAG);
}
ret = i40e_pci_sriov_enable(pdev, num_vfs); goto sriov_configure_out;
}
if (!pci_vfs_assigned(pf->pdev)) {
i40e_free_vfs(pf);
clear_bit(I40E_FLAG_VEB_MODE_ENA, pf->flags);
i40e_do_reset_safe(pf, I40E_PF_RESET_AND_REBUILD_FLAG);
} else {
dev_warn(&pdev->dev, "Unable to free VFs because some are assigned to VMs.\n");
ret = -EINVAL; goto sriov_configure_out;
}
sriov_configure_out:
clear_bit(__I40E_VIRTCHNL_OP_PENDING, pf->state); return ret;
}
aq_ret = i40e_aq_send_msg_to_vf(hw, abs_vf_id, v_opcode, v_retval,
msg, msglen, NULL); if (aq_ret) {
dev_info(&pf->pdev->dev, "Unable to send the message to VF %d aq_err %d\n",
vf->vf_id, pf->hw.aq.asq_last_status); return -EIO;
}
return 0;
}
/** * i40e_vc_send_resp_to_vf * @vf: pointer to the VF info * @opcode: operation code * @retval: return value * * send resp msg to VF
**/ staticint i40e_vc_send_resp_to_vf(struct i40e_vf *vf, enum virtchnl_ops opcode, int retval)
{ return i40e_vc_send_msg_to_vf(vf, opcode, retval, NULL, 0);
}
/** * i40e_sync_vf_state * @vf: pointer to the VF info * @state: VF state * * Called from a VF message to synchronize the service with a potential * VF reset state
**/ staticbool i40e_sync_vf_state(struct i40e_vf *vf, enum i40e_vf_states state)
{ int i;
/* When handling some messages, it needs VF state to be set. * It is possible that this flag is cleared during VF reset, * so there is a need to wait until the end of the reset to * handle the request message correctly.
*/ for (i = 0; i < I40E_VF_STATE_WAIT_COUNT; i++) { if (test_bit(state, &vf->vf_states)) returntrue;
usleep_range(10000, 20000);
}
return test_bit(state, &vf->vf_states);
}
/** * i40e_vc_get_version_msg * @vf: pointer to the VF info * @msg: pointer to the msg buffer * * called from the VF to request the API version used by the PF
**/ staticint i40e_vc_get_version_msg(struct i40e_vf *vf, u8 *msg)
{ struct virtchnl_version_info info = {
VIRTCHNL_VERSION_MAJOR, VIRTCHNL_VERSION_MINOR
};
vf->vf_ver = *(struct virtchnl_version_info *)msg; /* VFs running the 1.0 API expect to get 1.0 back or they will cry. */ if (VF_IS_V10(&vf->vf_ver))
info.minor = VIRTCHNL_VERSION_MINOR_NO_VF_CAPS; return i40e_vc_send_msg_to_vf(vf, VIRTCHNL_OP_VERSION,
0, (u8 *)&info, sizeof(struct virtchnl_version_info));
}
/** * i40e_del_qch - delete all the additional VSIs created as a part of ADq * @vf: pointer to VF structure
**/ staticvoid i40e_del_qch(struct i40e_vf *vf)
{ struct i40e_pf *pf = vf->pf; int i;
/* first element in the array belongs to primary VF VSI and we shouldn't * delete it. We should however delete the rest of the VSIs created
*/ for (i = 1; i < vf->num_tc; i++) { if (vf->ch[i].vsi_idx) {
i40e_vsi_release(pf->vsi[vf->ch[i].vsi_idx]);
vf->ch[i].vsi_idx = 0;
vf->ch[i].vsi_id = 0;
}
}
}
/** * i40e_vc_get_max_frame_size * @vf: pointer to the VF * * Max frame size is determined based on the current port's max frame size and * whether a port VLAN is configured on this VF. The VF is not aware whether * it's in a port VLAN so the PF needs to account for this in max frame size * checks and sending the max frame size to the VF.
**/ static u16 i40e_vc_get_max_frame_size(struct i40e_vf *vf)
{
u16 max_frame_size = vf->pf->hw.phy.link_info.max_frame_size;
if (vf->port_vlan_id)
max_frame_size -= VLAN_HLEN;
return max_frame_size;
}
/** * i40e_vc_get_vf_resources_msg * @vf: pointer to the VF info * @msg: pointer to the msg buffer * * called from the VF to request its resources
**/ staticint i40e_vc_get_vf_resources_msg(struct i40e_vf *vf, u8 *msg)
{ struct virtchnl_vf_resource *vfres = NULL; struct i40e_pf *pf = vf->pf; struct i40e_vsi *vsi; int num_vsis = 1; int aq_ret = 0;
size_t len = 0; int ret;
if (test_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE, pf->hw.caps)) { if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2)
vfres->vf_cap_flags |=
VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2;
}
if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_ENCAP)
vfres->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_ENCAP;
if (test_bit(I40E_HW_CAP_OUTER_UDP_CSUM, pf->hw.caps) &&
(vf->driver_caps & VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM))
vfres->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM;
if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_RX_POLLING) { if (test_bit(I40E_FLAG_MFP_ENA, pf->flags)) {
dev_err(&pf->pdev->dev, "VF %d requested polling mode: this feature is supported only when the device is running in single function per port (SFP) mode\n",
vf->vf_id);
aq_ret = -EINVAL; goto err;
}
vfres->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_RX_POLLING;
}
if (test_bit(I40E_HW_CAP_WB_ON_ITR, pf->hw.caps)) { if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_WB_ON_ITR)
vfres->vf_cap_flags |=
VIRTCHNL_VF_OFFLOAD_WB_ON_ITR;
}
if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_REQ_QUEUES)
vfres->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_REQ_QUEUES;
if (vf->driver_caps & VIRTCHNL_VF_OFFLOAD_ADQ)
vfres->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_ADQ;
/* For ADq there can be up to 4 VSIs with max 4 queues each. * VF does not know about these additional VSIs and all * it cares is about its own queues. PF configures these queues * to its appropriate VSIs based on TC mapping
*/ if (vf->adq_enabled) { if (idx >= vf->num_tc) {
aq_ret = -ENODEV; goto error_param;
} if (j == (vf->ch[idx].num_qps - 1)) {
idx++;
j = 0; /* resetting the queue count */
vsi_queue_id = 0;
} else {
j++;
vsi_queue_id++;
}
}
} /* set vsi num_queue_pairs in use to num configured by VF */ if (!vf->adq_enabled) {
pf->vsi[vf->lan_vsi_idx]->num_queue_pairs =
qci->num_queue_pairs;
} else { for (i = 0; i < vf->num_tc; i++) {
vsi = pf->vsi[vf->ch[i].vsi_idx];
vsi->num_queue_pairs = vf->ch[i].num_qps;
--> --------------------
--> maximum size reached
--> --------------------
Messung V0.5
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(vorverarbeitet)
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