/* Broadcom NetXtreme-C/E network driver. * * Copyright (c) 2014-2016 Broadcom Corporation * Copyright (c) 2016-2018 Broadcom Limited * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation. #ifndef BNXT_H#define BNXT_H#define DRV_MODULE_NAME "bnxt_en" /* DO NOT CHANGE DRV_VER_* defines * FIXME: Delete them #define DRV_VER_MAJ 1#define DRV_VER_MIN 10#define DRV_VER_UPD 3#include <linux/ethtool.h>#include <linux/interrupt.h>#include <linux/rhashtable.h>#include <linux/crash_dump.h>#include <linux/auxiliary_bus.h>#include <net/devlink.h>#include <net/dst_metadata.h>#include <net/xdp.h>#include <linux/dim.h>#include <linux/io-64-nonatomic-lo-hi.h>#ifdef CONFIG_TEE_BNXT_FW#include <linux/firmware/broadcom/tee_bnxt_fw.h>#endif #define BNXT_DEFAULT_RX_COPYBREAK 256#define BNXT_MAX_RX_COPYBREAK 1024extern struct list_head bnxt_block_cb_list;struct page_pool;struct tx_bd {#define TX_BD_TYPE (0x3f << 0)#define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)#define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)#define TX_BD_FLAGS_PACKET_END (1 << 6)#define TX_BD_FLAGS_NO_CMPL (1 << 7)#define TX_BD_FLAGS_BD_CNT (0x1f << 8)#define TX_BD_FLAGS_BD_CNT_SHIFT 8#define TX_BD_FLAGS_LHINT (3 << 13)#define TX_BD_FLAGS_LHINT_SHIFT 13#define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)#define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)#define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)#define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)#define TX_BD_FLAGS_COAL_NOW (1 << 15)#define TX_BD_LEN (0xffff << 16)#define TX_BD_LEN_SHIFT 16#define TX_OPAQUE_IDX_MASK 0x0000ffff#define TX_OPAQUE_BDS_MASK 0x00ff0000#define TX_OPAQUE_BDS_SHIFT 16#define TX_OPAQUE_RING_MASK 0xff000000#define TX_OPAQUE_RING_SHIFT 24#define SET_TX_OPAQUE(bp, txr, idx, bds) \#define TX_OPAQUE_IDX(opq) ((opq) & TX_OPAQUE_IDX_MASK)#define TX_OPAQUE_RING(opq) (((opq) & TX_OPAQUE_RING_MASK) >> \#define TX_OPAQUE_BDS(opq) (((opq) & TX_OPAQUE_BDS_MASK) >> \#define TX_OPAQUE_PROD(bp, opq) ((TX_OPAQUE_IDX(opq) + TX_OPAQUE_BDS(opq)) &\#define TX_BD_CNT(n) (((n) << TX_BD_FLAGS_BD_CNT_SHIFT) & TX_BD_FLAGS_BD_CNT)#define TX_MAX_BD_CNT 32#define TX_MAX_FRAGS (TX_MAX_BD_CNT - 2)struct tx_bd_ext {#define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)#define TX_BD_FLAGS_IP_CKSUM (1 << 1)#define TX_BD_FLAGS_NO_CRC (1 << 2)#define TX_BD_FLAGS_STAMP (1 << 3)#define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)#define TX_BD_FLAGS_LSO (1 << 5)#define TX_BD_FLAGS_IPID_FMT (1 << 6)#define TX_BD_FLAGS_T_IPID (1 << 7)#define TX_BD_HSIZE (0xff << 16)#define TX_BD_HSIZE_SHIFT 16#define TX_BD_CFA_ACTION (0xffff << 16)#define TX_BD_CFA_ACTION_SHIFT 16#define TX_BD_CFA_META_MASK 0xfffffff#define TX_BD_CFA_META_VID_MASK 0xfff#define TX_BD_CFA_META_PRI_MASK (0xf << 12)#define TX_BD_CFA_META_PRI_SHIFT 12#define TX_BD_CFA_META_TPID_MASK (3 << 16)#define TX_BD_CFA_META_TPID_SHIFT 16#define TX_BD_CFA_META_KEY (0xf << 28)#define TX_BD_CFA_META_KEY_SHIFT 28#define TX_BD_CFA_META_KEY_VLAN (1 << 28)#define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))struct rx_bd {#define RX_BD_TYPE (0x3f << 0)#define RX_BD_TYPE_RX_PACKET_BD 0x4#define RX_BD_TYPE_RX_BUFFER_BD 0x5#define RX_BD_TYPE_RX_AGG_BD 0x6#define RX_BD_TYPE_16B_BD_SIZE (0 << 4)#define RX_BD_TYPE_32B_BD_SIZE (1 << 4)#define RX_BD_TYPE_48B_BD_SIZE (2 << 4)#define RX_BD_TYPE_64B_BD_SIZE (3 << 4)#define RX_BD_FLAGS_SOP (1 << 6)#define RX_BD_FLAGS_EOP (1 << 7)#define RX_BD_FLAGS_BUFFERS (3 << 8)#define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)#define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)#define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)#define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)#define RX_BD_LEN (0xffff << 16)#define RX_BD_LEN_SHIFT 16struct tx_cmp {#define CMP_TYPE (0x3f << 0)#define CMP_TYPE_TX_L2_CMP 0#define CMP_TYPE_TX_L2_COAL_CMP 2#define CMP_TYPE_TX_L2_PKT_TS_CMP 4#define CMP_TYPE_RX_L2_CMP 17#define CMP_TYPE_RX_AGG_CMP 18#define CMP_TYPE_RX_L2_TPA_START_CMP 19#define CMP_TYPE_RX_L2_TPA_END_CMP 21#define CMP_TYPE_RX_TPA_AGG_CMP 22#define CMP_TYPE_RX_L2_V3_CMP 23#define CMP_TYPE_RX_L2_TPA_START_V3_CMP 25#define CMP_TYPE_STATUS_CMP 32#define CMP_TYPE_REMOTE_DRIVER_REQ 34#define CMP_TYPE_REMOTE_DRIVER_RESP 36#define CMP_TYPE_ERROR_STATUS 48#define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL#define CMPL_BASE_TYPE_HWRM_DONE 0x20UL#define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL#define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL#define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL#define TX_CMP_FLAGS_ERROR (1 << 6)#define TX_CMP_FLAGS_PUSH (1 << 7)#define TX_CMP_V (1 << 0)#define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)#define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0#define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2#define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4#define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5#define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)#define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)#define TX_CMP_ERRORS_DMA_ERROR (1 << 6)#define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)#define TX_CMP_SQ_CONS_IDX_MASK 0x00ffffff#define TX_CMP_SQ_CONS_IDX(txcmp) \struct tx_ts_cmp {#define TX_TS_CMP_FLAGS_ERROR (1 << 6)#define TX_TS_CMP_FLAGS_TS_TYPE (1 << 7)#define TX_TS_CMP_FLAGS_TS_TYPE_PM (0 << 7)#define TX_TS_CMP_FLAGS_TS_TYPE_PA (1 << 7)#define TX_TS_CMP_FLAGS_TS_FALLBACK (1 << 8)#define TX_TS_CMP_TS_SUB_NS (0xf << 12)#define TX_TS_CMP_TS_NS_MID (0xffff << 16)#define TX_TS_CMP_TS_NS_MID_SFT 16#define TX_TS_CMP_V (1 << 0)#define TX_TS_CMP_TS_INVALID_ERR (1 << 10)#define BNXT_GET_TX_TS_48B_NS(tscmp) \#define BNXT_TX_TS_ERR(tscmp) \struct rx_cmp {#define RX_CMP_CMP_TYPE (0x3f << 0)#define RX_CMP_FLAGS_ERROR (1 << 6)#define RX_CMP_FLAGS_PLACEMENT (7 << 7)#define RX_CMP_FLAGS_RSS_VALID (1 << 10)#define RX_CMP_FLAGS_PKT_METADATA_PRESENT (1 << 11)#define RX_CMP_FLAGS_ITYPES_SHIFT 12#define RX_CMP_FLAGS_ITYPES_MASK 0xf000#define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)#define RX_CMP_FLAGS_ITYPE_IP (1 << 12)#define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)#define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)#define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)#define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)#define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)#define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)#define RX_CMP_LEN (0xffff << 16)#define RX_CMP_LEN_SHIFT 16#define RX_CMP_V1 (1 << 0)#define RX_CMP_AGG_BUFS (0x1f << 1)#define RX_CMP_AGG_BUFS_SHIFT 1#define RX_CMP_RSS_HASH_TYPE (0x7f << 9)#define RX_CMP_RSS_HASH_TYPE_SHIFT 9#define RX_CMP_V3_RSS_EXT_OP_LEGACY (0xf << 12)#define RX_CMP_V3_RSS_EXT_OP_LEGACY_SHIFT 12#define RX_CMP_V3_RSS_EXT_OP_NEW (0xf << 8)#define RX_CMP_V3_RSS_EXT_OP_NEW_SHIFT 8#define RX_CMP_PAYLOAD_OFFSET (0xff << 16)#define RX_CMP_PAYLOAD_OFFSET_SHIFT 16#define RX_CMP_SUB_NS_TS (0xf << 16)#define RX_CMP_SUB_NS_TS_SHIFT 16#define RX_CMP_METADATA1 (0xf << 28)#define RX_CMP_METADATA1_SHIFT 28#define RX_CMP_METADATA1_TPID_SEL (0x7 << 28)#define RX_CMP_METADATA1_TPID_8021Q (0x1 << 28)#define RX_CMP_METADATA1_TPID_8021AD (0x0 << 28)#define RX_CMP_METADATA1_VALID (0x8 << 28)#define BNXT_PTP_RX_TS_VALID(flags) \#define BNXT_ALL_RX_TS_VALID(flags) \#define RX_CMP_HASH_VALID(rxcmp) \#define RSS_PROFILE_ID_MASK 0x1f#define RX_CMP_HASH_TYPE(rxcmp) \#define RX_CMP_ITYPES(rxcmp) \#define RX_CMP_V3_HASH_TYPE_LEGACY(rxcmp) \#define RX_CMP_V3_HASH_TYPE_NEW(rxcmp) \#define RX_CMP_V3_HASH_TYPE(bp, rxcmp) \#define EXT_OP_INNER_4 0x0#define EXT_OP_OUTER_4 0x2#define EXT_OP_INNFL_3 0x8#define EXT_OP_OUTFL_3 0xa#define RX_CMP_VLAN_VALID(rxcmp) \#define RX_CMP_VLAN_TPID_SEL(rxcmp) \struct rx_cmp_ext {#define RX_CMP_FLAGS2_IP_CS_CALC 0x1#define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)#define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)#define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)#define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)#define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff#define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff#define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000#define RX_CMP_FLAGS2_METADATA_TPID_SFT 16#define RX_CMP_V (1 << 0)#define RX_CMPL_ERRORS_MASK (0x7fff << 1)#define RX_CMPL_ERRORS_SFT 1#define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)#define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)#define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)#define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)#define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)#define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)#define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)#define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)#define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)#define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)#define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)#define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)#define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)#define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)#define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)#define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)#define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)#define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)#define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)#define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)#define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)#define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)#define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)#define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)#define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)#define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)#define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)#define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)#define RX_CMPL_CFA_CODE_MASK (0xffff << 16)#define RX_CMPL_CFA_CODE_SFT 16#define RX_CMPL_METADATA0_TCI_MASK (0xffff << 16)#define RX_CMPL_METADATA0_VID_MASK (0x0fff << 16)#define RX_CMPL_METADATA0_SFT 16#define RX_CMP_L2_ERRORS \#define RX_CMP_L4_CS_BITS \#define RX_CMP_L4_CS_ERR_BITS \#define RX_CMP_L4_CS_OK(rxcmp1) \#define RX_CMP_ENCAP(rxcmp1) \#define RX_CMP_CFA_CODE(rxcmpl1) \#define RX_CMP_METADATA0_TCI(rxcmp1) \struct rx_agg_cmp {#define RX_AGG_CMP_TYPE (0x3f << 0)#define RX_AGG_CMP_LEN (0xffff << 16)#define RX_AGG_CMP_LEN_SHIFT 16#define RX_AGG_CMP_V (1 << 0)#define RX_AGG_CMP_AGG_ID (0x0fff << 16)#define RX_AGG_CMP_AGG_ID_SHIFT 16#define TPA_AGG_AGG_ID(rx_agg) \struct rx_tpa_start_cmp {#define RX_TPA_START_CMP_TYPE (0x3f << 0)#define RX_TPA_START_CMP_FLAGS (0x3ff << 6)#define RX_TPA_START_CMP_FLAGS_SHIFT 6#define RX_TPA_START_CMP_FLAGS_ERROR (0x1 << 6)#define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)#define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7#define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)#define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)#define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)#define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)#define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)#define RX_TPA_START_CMP_FLAGS_TIMESTAMP (0x1 << 11)#define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)#define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12#define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)#define RX_TPA_START_CMP_LEN (0xffff << 16)#define RX_TPA_START_CMP_LEN_SHIFT 16#define RX_TPA_START_CMP_V1 (0x1 << 0)#define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)#define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9#define RX_TPA_START_CMP_V3_RSS_HASH_TYPE (0x1ff << 7)#define RX_TPA_START_CMP_V3_RSS_HASH_TYPE_SHIFT 7#define RX_TPA_START_CMP_AGG_ID (0x7f << 25)#define RX_TPA_START_CMP_AGG_ID_SHIFT 25#define RX_TPA_START_CMP_AGG_ID_P5 (0x0fff << 16)#define RX_TPA_START_CMP_AGG_ID_SHIFT_P5 16#define RX_TPA_START_CMP_METADATA1 (0xf << 28)#define RX_TPA_START_CMP_METADATA1_SHIFT 28#define RX_TPA_START_METADATA1_TPID_SEL (0x7 << 28)#define RX_TPA_START_METADATA1_TPID_8021Q (0x1 << 28)#define RX_TPA_START_METADATA1_TPID_8021AD (0x0 << 28)#define RX_TPA_START_METADATA1_VALID (0x8 << 28)#define TPA_START_HASH_VALID(rx_tpa_start) \#define TPA_START_HASH_TYPE(rx_tpa_start) \#define TPA_START_V3_HASH_TYPE(rx_tpa_start) \#define TPA_START_AGG_ID(rx_tpa_start) \#define TPA_START_AGG_ID_P5(rx_tpa_start) \#define TPA_START_ERROR(rx_tpa_start) \#define TPA_START_VLAN_VALID(rx_tpa_start) \#define TPA_START_VLAN_TPID_SEL(rx_tpa_start) \struct rx_tpa_start_cmp_ext {#define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)#define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)#define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)#define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)#define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID (0x1 << 9)#define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT (0x3 << 10)#define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT 10#define RX_TPA_START_CMP_V3_FLAGS2_T_IP_TYPE (0x1 << 10)#define RX_TPA_START_CMP_V3_FLAGS2_AGG_GRO (0x1 << 11)#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL (0xffff << 16)#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT 16#define RX_TPA_START_CMP_V2 (0x1 << 0)#define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)#define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT 1#define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)#define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)#define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)#define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)#define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16#define RX_TPA_START_CMP_METADATA0_TCI_MASK (0xffff << 16)#define RX_TPA_START_CMP_METADATA0_VID_MASK (0x0fff << 16)#define RX_TPA_START_CMP_METADATA0_SFT 16#define TPA_START_CFA_CODE(rx_tpa_start) \#define TPA_START_IS_IPV6(rx_tpa_start) \#define TPA_START_ERROR_CODE(rx_tpa_start) \#define TPA_START_METADATA0_TCI(rx_tpa_start) \struct rx_tpa_end_cmp {#define RX_TPA_END_CMP_TYPE (0x3f << 0)#define RX_TPA_END_CMP_FLAGS (0x3ff << 6)#define RX_TPA_END_CMP_FLAGS_SHIFT 6#define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)#define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7#define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)#define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)#define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)#define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)#define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)#define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)#define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12#define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)#define RX_TPA_END_CMP_LEN (0xffff << 16)#define RX_TPA_END_CMP_LEN_SHIFT 16#define RX_TPA_END_CMP_V1 (0x1 << 0)#define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)#define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1#define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)#define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8#define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)#define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16#define RX_TPA_END_CMP_AGG_ID (0x7f << 25)#define RX_TPA_END_CMP_AGG_ID_SHIFT 25#define RX_TPA_END_CMP_AGG_ID_P5 (0x0fff << 16)#define RX_TPA_END_CMP_AGG_ID_SHIFT_P5 16#define RX_TPA_END_GRO_TS (0x1 << 31)#define TPA_END_AGG_ID(rx_tpa_end) \#define TPA_END_AGG_ID_P5(rx_tpa_end) \#define TPA_END_PAYLOAD_OFF(rx_tpa_end) \#define TPA_END_AGG_BUFS(rx_tpa_end) \#define TPA_END_TPA_SEGS(rx_tpa_end) \#define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \#define TPA_END_GRO(rx_tpa_end) \#define TPA_END_GRO_TS(rx_tpa_end) \struct rx_tpa_end_cmp_ext {#define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)#define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5 (0xff << 16)#define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5 16#define RX_TPA_END_CMP_AGG_BUFS_P5 (0xff << 24)#define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5 24#define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)#define RX_TPA_END_CMP_V2 (0x1 << 0)#define RX_TPA_END_CMP_ERRORS (0x3 << 1)#define RX_TPA_END_CMP_ERRORS_P5 (0x7 << 1)#define RX_TPA_END_CMPL_ERRORS_SHIFT 1#define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)#define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)#define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)#define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR (0x4 << 1)#define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH (0x5 << 1)#define TPA_END_ERRORS(rx_tpa_end_ext) \#define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext) \#define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext) \#define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \#define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \#define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \#define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \#define EVENT_DATA1_RECOVERY_ENABLED(data1) \#define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \#define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \struct nqe_cn {#define NQ_CN_TYPE_MASK 0x3fUL#define NQ_CN_TYPE_SFT 0#define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL#define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION#define NQ_CN_TOGGLE_MASK 0xc0UL#define NQ_CN_TOGGLE_SFT 6#define NQ_CN_V 0x1UL#define BNXT_NQ_HDL_IDX_MASK 0x00ffffff#define BNXT_NQ_HDL_TYPE_MASK 0xff000000#define BNXT_NQ_HDL_TYPE_SHIFT 24#define BNXT_NQ_HDL_TYPE_RX 0x00#define BNXT_NQ_HDL_TYPE_TX 0x01#define BNXT_NQ_HDL_IDX(hdl) ((hdl) & BNXT_NQ_HDL_IDX_MASK)#define BNXT_NQ_HDL_TYPE(hdl) (((hdl) & BNXT_NQ_HDL_TYPE_MASK) >> \#define BNXT_SET_NQ_HDL(cpr) \#define NQE_CN_TYPE(type) ((type) & NQ_CN_TYPE_MASK)#define NQE_CN_TOGGLE(type) (((type) & NQ_CN_TOGGLE_MASK) >> \#define DB_IDX_MASK 0xffffff#define DB_IDX_VALID (0x1 << 26)#define DB_IRQ_DIS (0x1 << 27)#define DB_KEY_TX (0x0 << 28)#define DB_KEY_RX (0x1 << 28)#define DB_KEY_CP (0x2 << 28)#define DB_KEY_ST (0x3 << 28)#define DB_KEY_TX_PUSH (0x4 << 28)#define DB_LONG_TX_PUSH (0x2 << 24)#define BNXT_MIN_ROCE_CP_RINGS 2#define BNXT_MIN_ROCE_STAT_CTXS 1/* 64-bit doorbell */ #define DBR_INDEX_MASK 0x0000000000ffffffULL#define DBR_EPOCH_MASK 0x01000000UL#define DBR_EPOCH_SFT 24#define DBR_TOGGLE_MASK 0x06000000UL#define DBR_TOGGLE_SFT 25#define DBR_XID_MASK 0x000fffff00000000ULL#define DBR_XID_SFT 32#define DBR_PATH_L2 (0x1ULL << 56)#define DBR_VALID (0x1ULL << 58)#define DBR_TYPE_SQ (0x0ULL << 60)#define DBR_TYPE_RQ (0x1ULL << 60)#define DBR_TYPE_SRQ (0x2ULL << 60)#define DBR_TYPE_SRQ_ARM (0x3ULL << 60)#define DBR_TYPE_CQ (0x4ULL << 60)#define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)#define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)#define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)#define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)#define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)#define DBR_TYPE_NQ (0xaULL << 60)#define DBR_TYPE_NQ_ARM (0xbULL << 60)#define DBR_TYPE_NQ_MASK (0xeULL << 60)#define DBR_TYPE_NULL (0xfULL << 60)#define DB_PF_OFFSET_P5 0x10000#define DB_VF_OFFSET_P5 0x4000#define INVALID_HW_RING_ID ((u16)-1)/* The hardware supports certain page sizes. Use the supported page sizes * to allocate the rings. #if (PAGE_SHIFT < 12)#define BNXT_PAGE_SHIFT 12#elif (PAGE_SHIFT <= 13)#define BNXT_PAGE_SHIFT PAGE_SHIFT#elif (PAGE_SHIFT < 16)#define BNXT_PAGE_SHIFT 13#else #define BNXT_PAGE_SHIFT 16#endif #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)/* The RXBD length is 16-bit so we can only support page sizes < 64K */ #if (PAGE_SHIFT > 15)#define BNXT_RX_PAGE_SHIFT 15#else #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT#endif #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)#define BNXT_MAX_MTU 9500/* First RX buffer page in XDP multi-buf mode * * +-------------------------------------------------------------------------+ * | XDP_PACKET_HEADROOM | bp->rx_buf_use_size | skb_shared_info| * | (bp->rx_dma_offset) | | | * +-------------------------------------------------------------------------+ #define BNXT_MAX_PAGE_MODE_MTU_SBUF \unsigned int )PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \#define BNXT_MAX_PAGE_MODE_MTU \unsigned int )sizeof (struct skb_shared_info)))#define BNXT_MIN_PKT_SIZE 52#define BNXT_DEFAULT_RX_RING_SIZE 511#define BNXT_DEFAULT_TX_RING_SIZE 511#define MAX_TPA 64#define MAX_TPA_P5 256#define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)#define MAX_TPA_SEGS_P5 0x3f#if (BNXT_PAGE_SHIFT == 16)#define MAX_RX_PAGES_AGG_ENA 1#define MAX_RX_PAGES 4#define MAX_RX_AGG_PAGES 4#define MAX_TX_PAGES 1#define MAX_CP_PAGES 16#else #define MAX_RX_PAGES_AGG_ENA 8#define MAX_RX_PAGES 32#define MAX_RX_AGG_PAGES 32#define MAX_TX_PAGES 8#define MAX_CP_PAGES 128#endif #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof (struct rx_bd))#define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof (struct tx_bd))#define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof (struct tx_cmp))#define SW_RXBD_RING_SIZE (sizeof (struct bnxt_sw_rx_bd) * RX_DESC_CNT)#define HW_RXBD_RING_SIZE (sizeof (struct rx_bd) * RX_DESC_CNT)#define SW_RXBD_AGG_RING_SIZE (sizeof (struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)#define SW_TXBD_RING_SIZE (sizeof (struct bnxt_sw_tx_bd) * TX_DESC_CNT)#define HW_TXBD_RING_SIZE (sizeof (struct tx_bd) * TX_DESC_CNT)#define HW_CMPD_RING_SIZE (sizeof (struct tx_cmp) * CP_DESC_CNT)#define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)#define BNXT_MAX_RX_DESC_CNT_JUM_ENA (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)#define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)#define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)/* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1. We need one extra * BD because the first TX BD is always a long BD. #define BNXT_MIN_TX_DESC_CNT (MAX_SKB_FRAGS + 2)#define RX_RING(bp, x) (((x) & (bp)->rx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))#define RX_AGG_RING(bp, x) (((x) & (bp)->rx_agg_ring_mask) >> \#define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))#define TX_RING(bp, x) (((x) & (bp)->tx_ring_mask) >> (BNXT_PAGE_SHIFT - 4))#define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))#define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))#define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))#define TX_CMP_VALID(txcmp, raw_cons) \#define RX_CMP_VALID(rxcmp1, raw_cons) \#define RX_AGG_CMP_VALID(agg, raw_cons) \#define NQ_CMP_VALID(nqcmp, raw_cons) \#define TX_CMP_TYPE(txcmp) \#define RX_CMP_TYPE(rxcmp) \#define RING_RX(bp, idx) ((idx) & (bp)->rx_ring_mask)#define NEXT_RX(idx) ((idx) + 1)#define RING_RX_AGG(bp, idx) ((idx) & (bp)->rx_agg_ring_mask)#define NEXT_RX_AGG(idx) ((idx) + 1)#define RING_TX(bp, idx) ((idx) & (bp)->tx_ring_mask)#define NEXT_TX(idx) ((idx) + 1)#define ADV_RAW_CMP(idx, n) ((idx) + (n))#define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)#define RING_CMP(idx) ((idx) & bp->cp_ring_mask)#define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))#define DFLT_HWRM_CMD_TIMEOUT 500#define BNXT_RX_EVENT 1#define BNXT_AGG_EVENT 2#define BNXT_TX_EVENT 4#define BNXT_REDIRECT_EVENT 8#define BNXT_TX_CMP_EVENT 0x10struct bnxt_sw_tx_bd {union {struct sk_buff *skb;struct xdp_frame *xdpf;struct page *page;unsigned short nr_frags;union {struct bnxt_sw_rx_bd {void *data;struct bnxt_sw_rx_agg_bd {unsigned int offset;struct bnxt_ring_mem_info {int nr_pages;int page_size;#define BNXT_RMEM_VALID_PTE_FLAG 1#define BNXT_RMEM_RING_PTE_FLAG 2#define BNXT_RMEM_USE_FULL_PAGE_FLAG 4struct bnxt_ctx_mem_type *ctx_mem;void **pg_arr;int vmem_size;void **vmem;struct bnxt_ring_struct {struct bnxt_ring_mem_info ring_mem;/* Ring id filled by Chimp FW */ union {/* Used by cmpl rings */ struct tx_push_bd {struct tx_bd_ext txbd2;struct tx_push_buffer {struct tx_push_bd push_bd;struct bnxt_db_info {void __iomem *doorbell;union {#define DB_EPOCH(db, idx) (((idx) & (db)->db_epoch_mask) << \#define DB_TOGGLE(tgl) ((tgl) << DBR_TOGGLE_SFT)#define DB_RING_IDX(db, idx) (((idx) & (db)->db_ring_mask) | \struct bnxt_tx_ring_info {struct bnxt_napi *bnapi;struct bnxt_cp_ring_info *tx_cpr;struct bnxt_db_info tx_db;struct tx_bd *tx_desc_ring[MAX_TX_PAGES];struct bnxt_sw_tx_bd *tx_buf_ring;struct tx_push_buffer *tx_push;#define BNXT_DEV_STATE_CLOSING 0x1struct bnxt_ring_struct tx_ring_struct;/* Synchronize simultaneous xdp_xmit on same ring */ #define BNXT_LEGACY_COAL_CMPL_PARAMS \#define BNXT_COAL_CMPL_ENABLES \#define BNXT_COAL_CMPL_MIN_TMR_ENABLE \#define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \struct bnxt_coal_cap {struct bnxt_coal {/* RING_IDLE enabled when coal ticks < idle_thresh */ struct bnxt_tpa_info {void *data;unsigned short gso_type;enum pkt_hash_types hash_type;#define BNXT_TPA_L4_SIZE(hdr_info) \#define BNXT_TPA_INNER_L3_OFF(hdr_info) \#define BNXT_TPA_INNER_L2_OFF(hdr_info) \#define BNXT_TPA_OUTER_L3_OFF(hdr_info) \/* cfa_code in TPA start compl */ struct rx_agg_cmp *agg_arr;#define BNXT_AGG_IDX_BMAP_SIZE (MAX_TPA_P5 / BITS_PER_LONG)struct bnxt_tpa_idx_map {unsigned long agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];struct bnxt_rx_ring_info {struct bnxt_napi *bnapi;struct bnxt_cp_ring_info *rx_cpr;struct bnxt_db_info rx_db;struct bnxt_db_info rx_agg_db;struct bpf_prog *xdp_prog;struct rx_bd *rx_desc_ring[MAX_RX_PAGES];struct bnxt_sw_rx_bd *rx_buf_ring;struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];struct bnxt_sw_rx_agg_bd *rx_agg_ring;unsigned long *rx_agg_bmap;bool need_head_pool;struct bnxt_tpa_info *rx_tpa;struct bnxt_tpa_idx_map *rx_tpa_idx_map;struct bnxt_ring_struct rx_ring_struct;struct bnxt_ring_struct rx_agg_ring_struct;struct xdp_rxq_info xdp_rxq;struct page_pool *page_pool;struct page_pool *head_pool;struct bnxt_rx_sw_stats {struct bnxt_tx_sw_stats {struct bnxt_cmn_sw_stats {struct bnxt_sw_stats {struct bnxt_rx_sw_stats rx;struct bnxt_tx_sw_stats tx;struct bnxt_cmn_sw_stats cmn;struct bnxt_total_ring_err_stats {struct bnxt_stats_mem {void *hw_stats;int len;struct bnxt_cp_ring_info {struct bnxt_napi *bnapi;struct bnxt_db_info cp_db;struct bnxt_coal rx_ring_coal;struct dim dim;union {struct tx_cmp **cp_desc_ring;struct nqe_cn **nq_desc_ring;struct bnxt_stats_mem stats;struct bnxt_sw_stats *sw_stats;struct bnxt_ring_struct cp_ring_struct;int cp_ring_count;struct bnxt_cp_ring_info *cp_ring_arr;#define BNXT_MAX_QUEUE 8#define BNXT_MAX_TXR_PER_NAPI BNXT_MAX_QUEUE#define bnxt_for_each_napi_tx(iter, bnapi, txr) \for (iter = 0, txr = (bnapi)->tx_ring[0]; txr; \struct bnxt_napi {struct napi_struct napi;struct bnxt *bp;int index;struct bnxt_cp_ring_info cp_ring;struct bnxt_rx_ring_info *rx_ring;struct bnxt_tx_ring_info *tx_ring[BNXT_MAX_TXR_PER_NAPI];void (*tx_int)(struct bnxt *, struct bnxt_napi *,int budget);#define BNXT_NAPI_FLAG_XDP 0x1bool in_reset;/* "TxRx", 2 hypens, plus maximum integer */ #define BNXT_IRQ_NAME_EXTRA 17struct bnxt_irq {unsigned int vector;char name[IFNAMSIZ + BNXT_IRQ_NAME_EXTRA];struct bnxt *bp;int msix_nr;int ring_nr;struct irq_affinity_notify affinity_notify;#define HWRM_RING_ALLOC_TX 0x1#define HWRM_RING_ALLOC_RX 0x2#define HWRM_RING_ALLOC_AGG 0x4#define HWRM_RING_ALLOC_CMPL 0x8#define HWRM_RING_ALLOC_NQ 0x10#define INVALID_STATS_CTX_ID -1struct bnxt_ring_grp_info {#define BNXT_VNIC_DEFAULT 0#define BNXT_VNIC_NTUPLE 1struct bnxt_vnic_info {/* returned by Chimp during alloc */ #define BNXT_MAX_CTX_PER_VNIC 8#define BNXT_MAX_UC_ADDRS 4struct bnxt_l2_filter *l2_filters[BNXT_MAX_UC_ADDRS];/* index 0 always dev_addr */ int rss_table_size;#define BNXT_RSS_TABLE_ENTRIES_P5 64#define BNXT_RSS_TABLE_SIZE_P5 (BNXT_RSS_TABLE_ENTRIES_P5 * 4)#define BNXT_RSS_TABLE_MAX_TBL_P5 8#define BNXT_MAX_RSS_TABLE_SIZE_P5 \#define BNXT_MAX_RSS_TABLE_ENTRIES_P5 \int mc_list_size;int mc_list_count;#define BNXT_MAX_MC_ADDRS 16#define BNXT_VNIC_RSS_FLAG 1#define BNXT_VNIC_RFS_FLAG 2#define BNXT_VNIC_MCAST_FLAG 4#define BNXT_VNIC_UCAST_FLAG 8#define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10#define BNXT_VNIC_NTUPLE_FLAG 0x20#define BNXT_VNIC_RSSCTX_FLAG 0x40struct ethtool_rxfh_context *rss_ctx;struct bnxt_rss_ctx {struct bnxt_vnic_info vnic;#define BNXT_MAX_ETH_RSS_CTX 32#define BNXT_VNIC_ID_INVALID 0xffffffffstruct bnxt_hw_rings {int tx;int rx;int grp;int cp;int cp_p5;int stat;int vnic;int rss_ctx;struct bnxt_hw_resc {#if defined (CONFIG_BNXT_SRIOV)struct bnxt_vf_info {/* PF assigned MAC Address */ /* VF assigned MAC address, only * stored by PF. #define BNXT_VF_SPOOFCHK 0x2#define BNXT_VF_LINK_FORCED 0x4#define BNXT_VF_LINK_UP 0x8#define BNXT_VF_TRUST 0x10void *hwrm_cmd_req_addr;#endif struct bnxt_pf_info {#define BNXT_FIRST_PF_FID 1#define BNXT_FIRST_VF_FID 128unsigned long *vf_event_bmap;#define BNXT_VF_RESV_STRATEGY_MAXIMAL 0#define BNXT_VF_RESV_STRATEGY_MINIMAL 1#define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2void *hwrm_cmd_req_addr[4];struct bnxt_vf_info *vf;struct bnxt_filter_base {struct hlist_node hash;struct list_head list;#define BNXT_FLTR_TYPE_NTUPLE 1#define BNXT_FLTR_TYPE_L2 2#define BNXT_ACT_DROP 1#define BNXT_ACT_RING_DST 2#define BNXT_ACT_FUNC_DST 4#define BNXT_ACT_NO_AGING 8#define BNXT_ACT_RSS_CTX 0x10unsigned long state;#define BNXT_FLTR_VALID 0#define BNXT_FLTR_INSERTED 1#define BNXT_FLTR_FW_DELETED 2struct rcu_head rcu;struct bnxt_flow_masks {struct flow_dissector_key_ports ports;struct flow_dissector_key_addrs addrs;extern const struct bnxt_flow_masks BNXT_FLOW_MASK_NONE;extern const struct bnxt_flow_masks BNXT_FLOW_IPV6_MASK_ALL;extern const struct bnxt_flow_masks BNXT_FLOW_IPV4_MASK_ALL;struct bnxt_ntuple_filter {/* base filter must be the first member */ struct bnxt_filter_base base;struct flow_keys fkeys;struct bnxt_flow_masks fmasks;struct bnxt_l2_filter *l2_fltr;struct bnxt_l2_key {union {struct {struct bnxt_ipv4_tuple {struct flow_dissector_key_ipv4_addrs v4addrs;struct flow_dissector_key_ports ports;struct bnxt_ipv6_tuple {struct flow_dissector_key_ipv6_addrs v6addrs;struct flow_dissector_key_ports ports;#define BNXT_L2_KEY_SIZE (sizeof (struct bnxt_l2_key) / 4)struct bnxt_l2_filter {/* base filter must be the first member */ struct bnxt_filter_base base;struct bnxt_l2_key l2_key;/* Compat version of hwrm_port_phy_qcfg_output capped at 96 bytes. The * first 95 bytes are identical to hwrm_port_phy_qcfg_output in bnxt_hsi.h. * The last valid byte in the compat version is different. struct hwrm_port_phy_qcfg_output_compat {char phy_vendor_name[16];char phy_vendor_partnumber[16];struct bnxt_link_info {#define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK#define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL#define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK#define BNXT_PHY_STATE_ENABLED 0#define BNXT_PHY_STATE_DISABLED 1#define BNXT_LINK_STATE_UNKNOWN 0#define BNXT_LINK_STATE_DOWN 1#define BNXT_LINK_STATE_UP 2#define BNXT_LINK_IS_UP(bp) ((bp)->link_info.link_state == BNXT_LINK_STATE_UP)#define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF#define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL#define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX#define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX#define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \#define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \#define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE#define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS#define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED#define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW#define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK#define PHY_VER_LEN 3#define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB#define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB#define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB#define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB#define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB#define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB#define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB#define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB#define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB#define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB#define BNXT_LINK_SPEED_200GB PORT_PHY_QCFG_RESP_LINK_SPEED_200GB#define BNXT_LINK_SPEED_400GB PORT_PHY_QCFG_RESP_LINK_SPEED_400GB/* fw adv setting */ #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB#define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB#define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB#define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB#define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB#define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB#define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB#define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB#define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB#define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB#define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G#define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G#define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G#define BNXT_LINK_SPEEDS2_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB#define BNXT_LINK_SPEEDS2_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB#define BNXT_LINK_SPEEDS2_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB#define BNXT_LINK_SPEEDS2_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB#define BNXT_LINK_SPEEDS2_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB#define BNXT_LINK_SPEEDS2_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB#define BNXT_LINK_SPEEDS2_MSK_50GB_PAM4 \#define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4 \#define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4 \#define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4 \#define BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112 \#define BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112 \#define BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112 \#define BNXT_LINK_SPEED_50GB_PAM4 \#define BNXT_LINK_SPEED_100GB_PAM4 \#define BNXT_LINK_SPEED_200GB_PAM4 \#define BNXT_LINK_SPEED_400GB_PAM4 \#define BNXT_LINK_SPEED_100GB_PAM4_112 \#define BNXT_LINK_SPEED_200GB_PAM4_112 \#define BNXT_LINK_SPEED_400GB_PAM4_112 \#define BNXT_FEC_NONE PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED#define BNXT_FEC_AUTONEG_CAP PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED#define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED#define BNXT_FEC_ENC_BASE_R_CAP \#define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED#define BNXT_FEC_ENC_RS_CAP \#define BNXT_FEC_ENC_LLRS_CAP \#define BNXT_FEC_ENC_RS \#define BNXT_FEC_ENC_LLRS \/* copy of requested setting from ethtool cmd */ #define BNXT_AUTONEG_SPEED 1#define BNXT_AUTONEG_FLOW_CTRL 2#define BNXT_SIG_MODE_NRZ PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ#define BNXT_SIG_MODE_PAM4 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4#define BNXT_SIG_MODE_PAM4_112 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112#define BNXT_SIG_MODE_MAX (PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST + 1)/* user adv setting */ bool force_link_chng;bool phy_retry;unsigned long phy_retry_expires;/* a copy of phy_qcfg output used to report link * info to VF struct hwrm_port_phy_qcfg_output phy_qcfg_resp;#define BNXT_FEC_RS544_ON \#define BNXT_FEC_RS544_OFF \#define BNXT_FEC_RS272_ON \#define BNXT_FEC_RS272_OFF \#define BNXT_PAM4_SUPPORTED(link_info) \#define BNXT_FEC_RS_ON(link_info) \#define BNXT_FEC_LLRS_ON \#define BNXT_FEC_RS_OFF(link_info) \#define BNXT_FEC_BASE_R_ON(link_info) \#define BNXT_FEC_ALL_OFF(link_info) \struct bnxt_queue_info {#define BNXT_MAX_LED 4struct bnxt_led_info {#define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \#define BNXT_MAX_TEST 8struct bnxt_test_info {char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];#define CHIMP_REG_VIEW_ADDR \#define BNXT_GRCPF_REG_CHIMP_COMM 0x0#define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100#define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400#define BNXT_GRC_REG_STATUS_P5 0x520#define BNXT_GRCPF_REG_KONG_COMM 0xA00#define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00#define BNXT_GRC_REG_CHIP_NUM 0x48#define BNXT_GRC_REG_BASE 0x260000#define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c#define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810#define BNXT_GRC_BASE_MASK 0xfffff000#define BNXT_GRC_OFFSET_MASK 0x00000ffcstruct bnxt_tc_flow_stats {#ifdef CONFIG_BNXT_FLOWER_OFFLOADstruct bnxt_flower_indr_block_cb_priv {struct net_device *tunnel_netdev;struct bnxt *bp;struct list_head list;#endif struct bnxt_tc_info {bool enabled;/* hash table to store TC offloaded flows */ struct rhashtable flow_table;struct rhashtable_params flow_ht_params;/* hash table to store L2 keys of TC flows */ struct rhashtable l2_table;struct rhashtable_params l2_ht_params;/* hash table to store L2 keys for TC tunnel decap */ struct rhashtable decap_l2_table;struct rhashtable_params decap_l2_ht_params;/* hash table to store tunnel decap entries */ struct rhashtable decap_table;struct rhashtable_params decap_ht_params;/* hash table to store tunnel encap entries */ struct rhashtable encap_table;struct rhashtable_params encap_ht_params;/* lock to atomically add/del an l2 node when a flow is * added or deleted. struct mutex lock;/* Fields used for batching stats query */ struct rhashtable_iter iter;#define BNXT_FLOW_STATS_BATCH_MAX 10struct bnxt_tc_stats_batch {void *flow_node;struct bnxt_tc_flow_stats hw_stats;/* Stat counter mask (width) */ struct bnxt_vf_rep_stats {struct bnxt_vf_rep {struct bnxt *bp;struct net_device *dev;struct metadata_dst *dst;struct bnxt_vf_rep_stats rx_stats;struct bnxt_vf_rep_stats tx_stats;#define PTU_PTE_VALID 0x1UL#define PTU_PTE_LAST 0x2UL#define PTU_PTE_NEXT_TO_LAST 0x4UL#define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)#define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)#define MAX_CTX_BYTES ((size_t)MAX_CTX_TOTAL_PAGES * BNXT_PAGE_SIZE)#define MAX_CTX_BYTES_MASK (MAX_CTX_BYTES - 1)struct bnxt_ctx_pg_info {void *ctx_pg_arr[MAX_CTX_PAGES];struct bnxt_ring_mem_info ring_mem;struct bnxt_ctx_pg_info **ctx_pg_tbl;#define BNXT_MAX_TQM_SP_RINGS 1#define BNXT_MAX_TQM_FP_RINGS 8#define BNXT_MAX_TQM_RINGS \#define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256#define BNXT_SET_CTX_PAGE_ATTR(attr) \do { \if (BNXT_PAGE_SIZE == 0x2000) \else if (BNXT_PAGE_SIZE == 0x10000) \else \while (0)struct bnxt_ctx_mem_type {#define BNXT_CTX_MEM_TYPE_VALID FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID#define BNXT_CTX_MEM_FW_TRACE \#define BNXT_CTX_MEM_FW_BIN_TRACE \#define BNXT_CTX_MEM_PERSIST \#define BNXT_CTX_INIT_INVALID_OFFSET 0xffff#define BNXT_MAX_SPLIT_ENTRY 4union {struct {struct {struct bnxt_ctx_pg_info *pg_info;#define BNXT_CTX_MRAV_AV_SPLIT_ENTRY 0#define BNXT_CTX_QP FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP#define BNXT_CTX_SRQ FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ#define BNXT_CTX_CQ FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ#define BNXT_CTX_VNIC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC#define BNXT_CTX_STAT FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT#define BNXT_CTX_STQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING#define BNXT_CTX_FTQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING#define BNXT_CTX_MRAV FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV#define BNXT_CTX_TIM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM#define BNXT_CTX_TCK FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK#define BNXT_CTX_RCK FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK#define BNXT_CTX_MTQM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING#define BNXT_CTX_SQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW#define BNXT_CTX_RQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW#define BNXT_CTX_SRQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW#define BNXT_CTX_CQDBS FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW#define BNXT_CTX_TBLSC FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE#define BNXT_CTX_XPAR FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION#define BNXT_CTX_SRT FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE#define BNXT_CTX_SRT2 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE#define BNXT_CTX_CRT FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE#define BNXT_CTX_CRT2 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE#define BNXT_CTX_RIGP0 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE#define BNXT_CTX_L2HWRM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE#define BNXT_CTX_REHWRM FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE#define BNXT_CTX_CA0 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA0_TRACE#define BNXT_CTX_CA1 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA1_TRACE#define BNXT_CTX_CA2 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA2_TRACE#define BNXT_CTX_RIGP1 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP1_TRACE#define BNXT_CTX_KONG FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE#define BNXT_CTX_MAX (BNXT_CTX_TIM + 1)#define BNXT_CTX_L2_MAX (BNXT_CTX_FTQM + 1)#define BNXT_CTX_V2_MAX (BNXT_CTX_KONG + 1)#define BNXT_CTX_INV ((u16)-1)struct bnxt_ctx_mem_info {#define BNXT_CTX_FLAG_INITED 0x01struct bnxt_ctx_mem_type ctx_arr[BNXT_CTX_V2_MAX];enum bnxt_health_severity {enum bnxt_health_remedy {struct bnxt_fw_health {#define BNXT_FW_HEALTH_REG 0#define BNXT_FW_HEARTBEAT_REG 1#define BNXT_FW_RESET_CNT_REG 2#define BNXT_FW_RESET_INPROG_REG 3struct devlink_health_reporter *fw_reporter;/* Protects severity and remedy */ struct mutex lock;enum bnxt_health_severity severity;enum bnxt_health_remedy remedy;#define BNXT_FW_HEALTH_REG_TYPE_MASK 3#define BNXT_FW_HEALTH_REG_TYPE_CFG 0#define BNXT_FW_HEALTH_REG_TYPE_GRC 1#define BNXT_FW_HEALTH_REG_TYPE_BAR0 2#define BNXT_FW_HEALTH_REG_TYPE_BAR1 3#define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)#define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)#define BNXT_FW_HEALTH_WIN_BASE 0x3000#define BNXT_FW_HEALTH_WIN_MAP_OFF 8#define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \#define BNXT_FW_STATUS_HEALTH_MSK 0xffff#define BNXT_FW_STATUS_HEALTHY 0x8000#define BNXT_FW_STATUS_SHUTDOWN 0x100000#define BNXT_FW_STATUS_RECOVERING 0x400000#define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\#define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \#define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \#define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \#define BNXT_FW_RETRY 5#define BNXT_FW_IF_RETRY 10#define BNXT_FW_SLOT_RESET_RETRY 4struct bnxt_aux_priv {struct auxiliary_device aux_dev;struct bnxt_en_dev *edev;
Messung V0.5 C=98 H=97 G=97
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