/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2010 ASIX Electronics Corporation * Copyright (c) 2020 Samsung Electronics * * ASIX AX88796C SPI Fast Ethernet Linux driver #ifndef _AX88796C_MAIN_H#define _AX88796C_MAIN_H#include <linux/netdevice.h>#include <linux/mii.h>#include "ax88796c_spi.h" /* These identify the driver base version and may not be removed. */ #define DRV_NAME "ax88796c" #define ADP_NAME "ASIX AX88796C SPI Ethernet Adapter" #define TX_QUEUE_HIGH_WATER 45 /* Tx queue high water mark */ #define TX_QUEUE_LOW_WATER 20 /* Tx queue low water mark */ #define AX88796C_REGDUMP_LEN 256 #define AX88796C_PHY_REGDUMP_LEN 14 #define AX88796C_PHY_ID 0 x10#define TX_OVERHEAD sizeof_field(struct tx_pkt_info, tx_overhead)#define TX_EOP_SIZE 4 #define AX_MCAST_FILTER_SIZE 8 #define AX_MAX_MCAST 64 #define AX_MAX_CLK 80000000 #define TX_HDR_SOP_DICF 0 x8000#define TX_HDR_SOP_CPHI 0 x4000#define TX_HDR_SOP_INT 0 x2000#define TX_HDR_SOP_MDEQ 0 x1000#define TX_HDR_SOP_PKTLEN 0 x07FF#define TX_HDR_SOP_SEQNUM 0 xF800#define TX_HDR_SOP_PKTLENBAR 0 x07FF#define TX_HDR_SEG_FS 0 x8000#define TX_HDR_SEG_LS 0 x4000#define TX_HDR_SEG_SEGNUM 0 x3800#define TX_HDR_SEG_SEGLEN 0 x0700#define TX_HDR_SEG_EOFST 0 xC000#define TX_HDR_SEG_SOFST 0 x3800#define TX_HDR_SEG_SEGLENBAR 0 x07FF#define TX_HDR_EOP_SEQNUM 0 xF800#define TX_HDR_EOP_PKTLEN 0 x07FF#define TX_HDR_EOP_SEQNUMBAR 0 xF800#define TX_HDR_EOP_PKTLENBAR 0 x07FF/* Rx header fields mask */ #define RX_HDR1_MCBC 0 x8000#define RX_HDR1_STUFF_PKT 0 x4000#define RX_HDR1_MII_ERR 0 x2000#define RX_HDR1_CRC_ERR 0 x1000#define RX_HDR1_PKT_LEN 0 x07FF#define RX_HDR2_SEQ_NUM 0 xF800#define RX_HDR2_PKT_LEN_BAR 0 x7FFF#define RX_HDR3_PE 0 x8000#define RX_HDR3_L3_TYPE_IPV4V6 0 x6000#define RX_HDR3_L3_TYPE_IP 0 x4000#define RX_HDR3_L3_TYPE_IPV6 0 x2000#define RX_HDR3_L4_TYPE_ICMPV6 0 x1400#define RX_HDR3_L4_TYPE_TCP 0 x1000#define RX_HDR3_L4_TYPE_IGMP 0 x0c00#define RX_HDR3_L4_TYPE_ICMP 0 x0800#define RX_HDR3_L4_TYPE_UDP 0 x0400#define RX_HDR3_L3_ERR 0 x0200#define RX_HDR3_L4_ERR 0 x0100#define RX_HDR3_PRIORITY(x) ((x) << 4 )#define RX_HDR3_STRIP 0 x0008#define RX_HDR3_VLAN_ID 0 x0007struct ax88796c_pcpu_stats {struct u64_stats_sync syncp;struct ax88796c_device {struct spi_device *spi;struct net_device *ndev;struct ax88796c_pcpu_stats __percpu *stats;struct work_struct ax_work;struct mutex spi_lock; /* device access */ struct sk_buff_head tx_wait_q;struct axspi_data ax_spi;struct mii_bus *mdiobus;struct phy_device *phydev;int msg_enable;int link;int speed;int duplex;int pause;int asym_pause;int flowctrl;#define AX_FC_NONE 0 #define AX_FC_RX BIT(0 )#define AX_FC_TX BIT(1 )#define AX_FC_ANEG BIT(2 )#define AX_CAP_COMP BIT(0 )#define AX_PRIV_FLAGS_MASK (AX_CAP_COMP)unsigned long flags;#define EVENT_INTR 0 #define EVENT_TX 1 #define EVENT_SET_MULTI 2 #define to_ax88796c_device(ndev) ((struct ax88796c_device *)netdev_priv(ndev))enum skb_state {0 ,struct skb_data {enum skb_state state;/* A88796C register definition */ /* Definition of PAGE0 */ #define P0_PSR (0 x00)#define PSR_DEV_READY BIT(7 )#define PSR_RESET (0 << 15 )#define PSR_RESET_CLR BIT(15 )#define P0_BOR (0 x02)#define P0_FER (0 x04)#define FER_IPALM BIT(0 )#define FER_DCRC BIT(1 )#define FER_RH3M BIT(2 )#define FER_HEADERSWAP BIT(7 )#define FER_WSWAP BIT(8 )#define FER_BSWAP BIT(9 )#define FER_INTHI BIT(10 )#define FER_INTLO (0 << 10 )#define FER_IRQ_PULL BIT(11 )#define FER_RXEN BIT(14 )#define FER_TXEN BIT(15 )#define P0_ISR (0 x06)#define ISR_RXPKT BIT(0 )#define ISR_MDQ BIT(4 )#define ISR_TXT BIT(5 )#define ISR_TXPAGES BIT(6 )#define ISR_TXERR BIT(8 )#define ISR_LINK BIT(9 )#define P0_IMR (0 x08)#define IMR_RXPKT BIT(0 )#define IMR_MDQ BIT(4 )#define IMR_TXT BIT(5 )#define IMR_TXPAGES BIT(6 )#define IMR_TXERR BIT(8 )#define IMR_LINK BIT(9 )#define IMR_MASKALL (0 xFFFF)#define IMR_DEFAULT (IMR_TXERR)#define P0_WFCR (0 x0A)#define WFCR_PMEIND BIT(0 ) /* PME indication */ #define WFCR_PMETYPE BIT(1 ) /* PME I/O type */ #define WFCR_PMEPOL BIT(2 ) /* PME polarity */ #define WFCR_PMERST BIT(3 ) /* Reset PME */ #define WFCR_SLEEP BIT(4 ) /* Enable sleep mode */ #define WFCR_WAKEUP BIT(5 ) /* Enable wakeup mode */ #define WFCR_WAITEVENT BIT(6 ) /* Reserved */ #define WFCR_CLRWAKE BIT(7 ) /* Clear wakeup */ #define WFCR_LINKCH BIT(8 ) /* Enable link change */ #define WFCR_MAGICP BIT(9 ) /* Enable magic packet */ #define WFCR_WAKEF BIT(10 ) /* Enable wakeup frame */ #define WFCR_PMEEN BIT(11 ) /* Enable PME pin */ #define WFCR_LINKCHS BIT(12 ) /* Link change status */ #define WFCR_MAGICPS BIT(13 ) /* Magic packet status */ #define WFCR_WAKEFS BIT(14 ) /* Wakeup frame status */ #define WFCR_PMES BIT(15 ) /* PME pin status */ #define P0_PSCR (0 x0C)#define PSCR_PS_MASK (0 xFFF0)#define PSCR_PS_D0 (0 )#define PSCR_PS_D1 BIT(0 )#define PSCR_PS_D2 BIT(1 )#define PSCR_FPS BIT(3 ) /* Enable fiber mode PS */ #define PSCR_SWPS BIT(4 ) /* Enable software */ /* PS control */ #define PSCR_WOLPS BIT(5 ) /* Enable WOL PS */ #define PSCR_SWWOL BIT(6 ) /* Enable software select */ /* WOL PS */ #define PSCR_PHYOSC BIT(7 ) /* Internal PHY OSC control */ #define PSCR_FOFEF BIT(8 ) /* Force PHY generate FEF */ #define PSCR_FOF BIT(9 ) /* Force PHY in fiber mode */ #define PSCR_PHYPD BIT(10 ) /* PHY power down. */ /* Active high */ #define PSCR_PHYRST BIT(11 ) /* PHY reset signal. */ /* Active low */ #define PSCR_PHYCSIL BIT(12 ) /* PHY cable energy detect */ #define PSCR_PHYCOFF BIT(13 ) /* PHY cable off */ #define PSCR_PHYLINK BIT(14 ) /* PHY link status */ #define PSCR_EEPOK BIT(15 ) /* EEPROM load complete */ #define P0_MACCR (0 x0E)#define MACCR_RXEN BIT(0 ) /* Enable RX */ #define MACCR_DUPLEX_FULL BIT(1 ) /* 1: Full, 0: Half */ #define MACCR_SPEED_100 BIT(2 ) /* 1: 100Mbps, 0: 10Mbps */ #define MACCR_RXFC_ENABLE BIT(3 )#define MACCR_RXFC_MASK 0 xFFF7#define MACCR_TXFC_ENABLE BIT(4 )#define MACCR_TXFC_MASK 0 xFFEF#define MACCR_PSI BIT(6 ) /* Software Cable-Off */ /* Power Saving Interrupt */ #define MACCR_PF BIT(7 )#define MACCR_PMM_BITS 8 #define MACCR_PMM_MASK (0 x1F00)#define MACCR_PMM_RESET BIT(8 )#define MACCR_PMM_WAIT (2 << 8 )#define MACCR_PMM_READY (3 << 8 )#define MACCR_PMM_D1 (4 << 8 )#define MACCR_PMM_D2 (5 << 8 )#define MACCR_PMM_WAKE (7 << 8 )#define MACCR_PMM_D1_WAKE (8 << 8 )#define MACCR_PMM_D2_WAKE (9 << 8 )#define MACCR_PMM_SLEEP (10 << 8 )#define MACCR_PMM_PHY_RESET (11 << 8 )#define MACCR_PMM_SOFT_D1 (16 << 8 )#define MACCR_PMM_SOFT_D2 (17 << 8 )#define P0_TFBFCR (0 x10)#define TFBFCR_SCHE_FREE_PAGE 0 xE07F#define TFBFCR_FREE_PAGE_BITS 0 x07#define TFBFCR_FREE_PAGE_LATCH BIT(6 )#define TFBFCR_SET_FREE_PAGE(x) (((x) & 0 x3F) << TFBFCR_FREE_PAGE_BITS)#define TFBFCR_TX_PAGE_SET BIT(13 )#define TFBFCR_MANU_ENTX BIT(15 )#define TX_FREEBUF_MASK 0 x003F#define TX_DPTSTART 0 x4000#define P0_TSNR (0 x12)#define TXNR_TXB_ERR BIT(5 )#define TXNR_TXB_IDLE BIT(6 )#define TSNR_PKT_CNT(x) (((x) & 0 x3F) << 8 )#define TXNR_TXB_REINIT BIT(14 )#define TSNR_TXB_START BIT(15 )#define P0_RTDPR (0 x14)#define P0_RXBCR1 (0 x16)#define RXBCR1_RXB_DISCARD BIT(14 )#define RXBCR1_RXB_START BIT(15 )#define P0_RXBCR2 (0 x18)#define RXBCR2_PKT_MASK (0 xFF)#define RXBCR2_RXPC_MASK (0 x7F)#define RXBCR2_RXB_READY BIT(13 )#define RXBCR2_RXB_IDLE BIT(14 )#define RXBCR2_RXB_REINIT BIT(15 )#define P0_RTWCR (0 x1A)#define RTWCR_RXWC_MASK (0 x3FFF)#define RTWCR_RX_LATCH BIT(15 )#define P0_RCPHR (0 x1C)/* Definition of PAGE1 */ #define P1_RPPER (0 x22)#define RPPER_RXEN BIT(0 )#define P1_MRCR (0 x28)#define P1_MDR (0 x2A)#define P1_RMPR (0 x2C)#define P1_TMPR (0 x2E)#define P1_RXBSPCR (0 x30)#define RXBSPCR_STUF_WORD_CNT(x) (((x) & 0 x7000) >> 12 )#define RXBSPCR_STUF_ENABLE BIT(15 )#define P1_MCR (0 x32)#define MCR_SBP BIT(8 )#define MCR_SM BIT(9 )#define MCR_CRCENLAN BIT(11 )#define MCR_STP BIT(12 )/* Definition of PAGE2 */ #define P2_CIR (0 x42)#define P2_PCR (0 x44)#define PCR_POLL_EN BIT(0 )#define PCR_POLL_FLOWCTRL BIT(1 )#define PCR_POLL_BMCR BIT(2 )#define PCR_PHYID(x) ((x) << 8 )#define P2_PHYSR (0 x46)#define P2_MDIODR (0 x48)#define P2_MDIOCR (0 x4A)#define MDIOCR_RADDR(x) ((x) & 0 x1F)#define MDIOCR_FADDR(x) (((x) & 0 x1F) << 8 )#define MDIOCR_VALID BIT(13 )#define MDIOCR_READ BIT(14 )#define MDIOCR_WRITE BIT(15 )#define P2_LCR0 (0 x4C)#define LCR_LED0_EN BIT(0 )#define LCR_LED0_100MODE BIT(1 )#define LCR_LED0_DUPLEX BIT(2 )#define LCR_LED0_LINK BIT(3 )#define LCR_LED0_ACT BIT(4 )#define LCR_LED0_COL BIT(5 )#define LCR_LED0_10MODE BIT(6 )#define LCR_LED0_DUPCOL BIT(7 )#define LCR_LED1_EN BIT(8 )#define LCR_LED1_100MODE BIT(9 )#define LCR_LED1_DUPLEX BIT(10 )#define LCR_LED1_LINK BIT(11 )#define LCR_LED1_ACT BIT(12 )#define LCR_LED1_COL BIT(13 )#define LCR_LED1_10MODE BIT(14 )#define LCR_LED1_DUPCOL BIT(15 )#define P2_LCR1 (0 x4E)#define LCR_LED2_MASK (0 xFF00)#define LCR_LED2_EN BIT(0 )#define LCR_LED2_100MODE BIT(1 )#define LCR_LED2_DUPLEX BIT(2 )#define LCR_LED2_LINK BIT(3 )#define LCR_LED2_ACT BIT(4 )#define LCR_LED2_COL BIT(5 )#define LCR_LED2_10MODE BIT(6 )#define LCR_LED2_DUPCOL BIT(7 )#define P2_IPGCR (0 x50)#define P2_CRIR (0 x52)#define P2_FLHWCR (0 x54)#define P2_RXCR (0 x56)#define RXCR_PRO BIT(0 )#define RXCR_AMALL BIT(1 )#define RXCR_SEP BIT(2 )#define RXCR_AB BIT(3 )#define RXCR_AM BIT(4 )#define RXCR_AP BIT(5 )#define RXCR_ARP BIT(6 )#define P2_JLCR (0 x58)#define P2_MPLR (0 x5C)/* Definition of PAGE3 */ #define P3_MACASR0 (0 x62)#define P3_MACASR(x) (P3_MACASR0 + 2 * (x))#define MACASR_LOWBYTE_MASK 0 x00FF#define MACASR_HIGH_BITS 0 x08#define P3_MACASR1 (0 x64)#define P3_MACASR2 (0 x66)#define P3_MFAR01 (0 x68)#define P3_MFAR_BASE (0 x68)#define P3_MFAR(x) (P3_MFAR_BASE + 2 * (x))#define P3_MFAR23 (0 x6A)#define P3_MFAR45 (0 x6C)#define P3_MFAR67 (0 x6E)#define P3_VID0FR (0 x70)#define P3_VID1FR (0 x72)#define P3_EECSR (0 x74)#define P3_EEDR (0 x76)#define P3_EECR (0 x78)#define EECR_ADDR_MASK (0 x00FF)#define EECR_READ_ACT BIT(8 )#define EECR_WRITE_ACT BIT(9 )#define EECR_WRITE_DISABLE BIT(10 )#define EECR_WRITE_ENABLE BIT(11 )#define EECR_EE_READY BIT(13 )#define EECR_RELOAD BIT(14 )#define EECR_RESET BIT(15 )#define P3_TPCR (0 x7A)#define TPCR_PATT_MASK (0 xFF)#define TPCR_RAND_PKT_EN BIT(14 )#define TPCR_FIXED_PKT_EN BIT(15 )#define P3_TPLR (0 x7C)/* Definition of PAGE4 */ #define P4_SPICR (0 x8A)#define SPICR_RCEN BIT(0 )#define SPICR_QCEN BIT(1 )#define SPICR_RBRE BIT(3 )#define SPICR_PMM BIT(4 )#define SPICR_LOOPBACK BIT(8 )#define SPICR_CORE_RES_CLR BIT(10 )#define SPICR_SPI_RES_CLR BIT(11 )#define P4_SPIISMR (0 x8C)#define P4_COERCR0 (0 x92)#define COERCR0_RXIPCE BIT(0 )#define COERCR0_RXIPVE BIT(1 )#define COERCR0_RXV6PE BIT(2 )#define COERCR0_RXTCPE BIT(3 )#define COERCR0_RXUDPE BIT(4 )#define COERCR0_RXICMP BIT(5 )#define COERCR0_RXIGMP BIT(6 )#define COERCR0_RXICV6 BIT(7 )#define COERCR0_RXTCPV6 BIT(8 )#define COERCR0_RXUDPV6 BIT(9 )#define COERCR0_RXICMV6 BIT(10 )#define COERCR0_RXIGMV6 BIT(11 )#define COERCR0_RXICV6V6 BIT(12 )#define COERCR0_DEFAULT (COERCR0_RXIPCE | COERCR0_RXV6PE | \#define P4_COERCR1 (0 x94)#define COERCR1_IPCEDP BIT(0 )#define COERCR1_IPVEDP BIT(1 )#define COERCR1_V6VEDP BIT(2 )#define COERCR1_TCPEDP BIT(3 )#define COERCR1_UDPEDP BIT(4 )#define COERCR1_ICMPDP BIT(5 )#define COERCR1_IGMPDP BIT(6 )#define COERCR1_ICV6DP BIT(7 )#define COERCR1_RX64TE BIT(8 )#define COERCR1_RXPPPE BIT(9 )#define COERCR1_TCP6DP BIT(10 )#define COERCR1_UDP6DP BIT(11 )#define COERCR1_IC6DP BIT(12 )#define COERCR1_IG6DP BIT(13 )#define COERCR1_ICV66DP BIT(14 )#define COERCR1_RPCE BIT(15 )#define COERCR1_DEFAULT (COERCR1_RXPPPE)#define P4_COETCR0 (0 x96)#define COETCR0_TXIP BIT(0 )#define COETCR0_TXTCP BIT(1 )#define COETCR0_TXUDP BIT(2 )#define COETCR0_TXICMP BIT(3 )#define COETCR0_TXIGMP BIT(4 )#define COETCR0_TXICV6 BIT(5 )#define COETCR0_TXTCPV6 BIT(8 )#define COETCR0_TXUDPV6 BIT(9 )#define COETCR0_TXICMV6 BIT(10 )#define COETCR0_TXIGMV6 BIT(11 )#define COETCR0_TXICV6V6 BIT(12 )#define COETCR0_DEFAULT (COETCR0_TXIP | COETCR0_TXTCP | \#define P4_COETCR1 (0 x98)#define COETCR1_TX64TE BIT(0 )#define COETCR1_TXPPPE BIT(1 )#define P4_COECEDR (0 x9A)#define P4_L2CECR (0 x9C)/* Definition of PAGE5 */ #define P5_WFTR (0 xA2)#define WFTR_2MS (0 x01)#define WFTR_4MS (0 x02)#define WFTR_8MS (0 x03)#define WFTR_16MS (0 x04)#define WFTR_32MS (0 x05)#define WFTR_64MS (0 x06)#define WFTR_128MS (0 x07)#define WFTR_256MS (0 x08)#define WFTR_512MS (0 x09)#define WFTR_1024MS (0 x0A)#define WFTR_2048MS (0 x0B)#define WFTR_4096MS (0 x0C)#define WFTR_8192MS (0 x0D)#define WFTR_16384MS (0 x0E)#define WFTR_32768MS (0 x0F)#define P5_WFCCR (0 xA4)#define P5_WFCR03 (0 xA6)#define WFCR03_F0_EN BIT(0 )#define WFCR03_F1_EN BIT(4 )#define WFCR03_F2_EN BIT(8 )#define WFCR03_F3_EN BIT(12 )#define P5_WFCR47 (0 xA8)#define WFCR47_F4_EN BIT(0 )#define WFCR47_F5_EN BIT(4 )#define WFCR47_F6_EN BIT(8 )#define WFCR47_F7_EN BIT(12 )#define P5_WF0BMR0 (0 xAA)#define P5_WF0BMR1 (0 xAC)#define P5_WF0CR (0 xAE)#define P5_WF0OBR (0 xB0)#define P5_WF1BMR0 (0 xB2)#define P5_WF1BMR1 (0 xB4)#define P5_WF1CR (0 xB6)#define P5_WF1OBR (0 xB8)#define P5_WF2BMR0 (0 xBA)#define P5_WF2BMR1 (0 xBC)/* Definition of PAGE6 */ #define P6_WF2CR (0 xC2)#define P6_WF2OBR (0 xC4)#define P6_WF3BMR0 (0 xC6)#define P6_WF3BMR1 (0 xC8)#define P6_WF3CR (0 xCA)#define P6_WF3OBR (0 xCC)#define P6_WF4BMR0 (0 xCE)#define P6_WF4BMR1 (0 xD0)#define P6_WF4CR (0 xD2)#define P6_WF4OBR (0 xD4)#define P6_WF5BMR0 (0 xD6)#define P6_WF5BMR1 (0 xD8)#define P6_WF5CR (0 xDA)#define P6_WF5OBR (0 xDC)/* Definition of PAGE7 */ #define P7_WF6BMR0 (0 xE2)#define P7_WF6BMR1 (0 xE4)#define P7_WF6CR (0 xE6)#define P7_WF6OBR (0 xE8)#define P7_WF7BMR0 (0 xEA)#define P7_WF7BMR1 (0 xEC)#define P7_WF7CR (0 xEE)#define P7_WF7OBR (0 xF0)#define P7_WFR01 (0 xF2)#define P7_WFR23 (0 xF4)#define P7_WFR45 (0 xF6)#define P7_WFR67 (0 xF8)#define P7_WFPC0 (0 xFA)#define P7_WFPC1 (0 xFC)/* Tx headers structure */ struct tx_sop_header {/* bit 15-11: flags, bit 10-0: packet length */ /* bit 15-11: sequence number, bit 11-0: packet length bar */ struct tx_segment_header {/* bit 15-14: flags, bit 13-11: segment number */ /* bit 10-0: segment length */ /* bit 15-14: end offset, bit 13-11: start offset */ /* bit 10-0: segment length bar */ struct tx_eop_header {/* bit 15-11: sequence number, bit 10-0: packet length */ /* bit 15-11: sequence number bar, bit 10-0: packet length bar */ struct tx_pkt_info {struct tx_sop_header sop;struct tx_segment_header seg;struct tx_eop_header eop;/* Rx headers structure */ struct rx_header {extern unsigned long ax88796c_no_regs_mask[];#endif /* #ifndef _AX88796C_MAIN_H */
Messung V0.5 in Prozent C=95 H=91 G=92
¤ Dauer der Verarbeitung: 0.14 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
