// SPDX-License-Identifier: GPL-2.0 /* * Driver for Renesas R-Car MIPI CSI-2 Receiver * * Copyright (C) 2018 Renesas Electronics Corp. #include <linux/delay.h>#include <linux/interrupt.h>#include <linux/io.h>#include <linux/math64.h>#include <linux/module.h>#include <linux/of.h>#include <linux/of_graph.h>#include <linux/platform_device.h>#include <linux/pm_runtime.h>#include <linux/reset.h>#include <linux/sys_soc.h>#include <linux/units.h>#include <media/mipi-csi2.h>#include <media/v4l2-ctrls.h>#include <media/v4l2-device.h>#include <media/v4l2-fwnode.h>#include <media/v4l2-mc.h>#include <media/v4l2-subdev.h>struct rcar_csi2;/* Register offsets and bits */ /* Control Timing Select */ #define TREF_REG 0 x00#define TREF_TREF BIT(0 )/* Software Reset */ #define SRST_REG 0 x04#define SRST_SRST BIT(0 )/* PHY Operation Control */ #define PHYCNT_REG 0 x08#define PHYCNT_SHUTDOWNZ BIT(17 )#define PHYCNT_RSTZ BIT(16 )#define PHYCNT_ENABLECLK BIT(4 )#define PHYCNT_ENABLE_3 BIT(3 )#define PHYCNT_ENABLE_2 BIT(2 )#define PHYCNT_ENABLE_1 BIT(1 )#define PHYCNT_ENABLE_0 BIT(0 )/* Checksum Control */ #define CHKSUM_REG 0 x0c#define CHKSUM_ECC_EN BIT(1 )#define CHKSUM_CRC_EN BIT(0 )/* * Channel Data Type Select * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3 #define VCDT_REG 0 x10#define VCDT2_REG 0 x14#define VCDT_VCDTN_EN BIT(15 )#define VCDT_SEL_VC(n) (((n) & 0 x3) << 8 )#define VCDT_SEL_DTN_ON BIT(6 )#define VCDT_SEL_DT(n) (((n) & 0 x3f) << 0 )/* Frame Data Type Select */ #define FRDT_REG 0 x18/* Field Detection Control */ #define FLD_REG 0 x1c#define FLD_FLD_NUM(n) (((n) & 0 xff) << 16 )#define FLD_DET_SEL(n) (((n) & 0 x3) << 4 )#define FLD_FLD_EN4 BIT(3 )#define FLD_FLD_EN3 BIT(2 )#define FLD_FLD_EN2 BIT(1 )#define FLD_FLD_EN BIT(0 )/* Automatic Standby Control */ #define ASTBY_REG 0 x20/* Long Data Type Setting 0 */ #define LNGDT0_REG 0 x28/* Long Data Type Setting 1 */ #define LNGDT1_REG 0 x2c/* Interrupt Enable */ #define INTEN_REG 0 x30#define INTEN_INT_AFIFO_OF BIT(27 )#define INTEN_INT_ERRSOTHS BIT(4 )#define INTEN_INT_ERRSOTSYNCHS BIT(3 )/* Interrupt Source Mask */ #define INTCLOSE_REG 0 x34/* Interrupt Status Monitor */ #define INTSTATE_REG 0 x38#define INTSTATE_INT_ULPS_START BIT(7 )#define INTSTATE_INT_ULPS_END BIT(6 )/* Interrupt Error Status Monitor */ #define INTERRSTATE_REG 0 x3c/* Short Packet Data */ #define SHPDAT_REG 0 x40/* Short Packet Count */ #define SHPCNT_REG 0 x44/* LINK Operation Control */ #define LINKCNT_REG 0 x48#define LINKCNT_MONITOR_EN BIT(31 )#define LINKCNT_REG_MONI_PACT_EN BIT(25 )#define LINKCNT_ICLK_NONSTOP BIT(24 )/* Lane Swap */ #define LSWAP_REG 0 x4c#define LSWAP_L3SEL(n) (((n) & 0 x3) << 6 )#define LSWAP_L2SEL(n) (((n) & 0 x3) << 4 )#define LSWAP_L1SEL(n) (((n) & 0 x3) << 2 )#define LSWAP_L0SEL(n) (((n) & 0 x3) << 0 )/* PHY Test Interface Write Register */ #define PHTW_REG 0 x50#define PHTW_DWEN BIT(24 )#define PHTW_TESTDIN_DATA(n) (((n & 0 xff)) << 16 )#define PHTW_CWEN BIT(8 )#define PHTW_TESTDIN_CODE(n) ((n & 0 xff))#define PHYFRX_REG 0 x64#define PHYFRX_FORCERX_MODE_3 BIT(3 )#define PHYFRX_FORCERX_MODE_2 BIT(2 )#define PHYFRX_FORCERX_MODE_1 BIT(1 )#define PHYFRX_FORCERX_MODE_0 BIT(0 )/* V4H BASE registers */ #define V4H_N_LANES_REG 0 x0004#define V4H_CSI2_RESETN_REG 0 x0008#define V4H_PHY_MODE_REG 0 x001c#define V4H_PHY_MODE_DPHY 0 #define V4H_PHY_MODE_CPHY 1 #define V4H_PHY_SHUTDOWNZ_REG 0 x0040#define V4H_DPHY_RSTZ_REG 0 x0044#define V4H_FLDC_REG 0 x0804#define V4H_FLDD_REG 0 x0808#define V4H_IDIC_REG 0 x0810#define V4H_PHY_EN_REG 0 x2000#define V4H_PHY_EN_ENABLE_3 BIT(7 )#define V4H_PHY_EN_ENABLE_2 BIT(6 )#define V4H_PHY_EN_ENABLE_1 BIT(5 )#define V4H_PHY_EN_ENABLE_0 BIT(4 )#define V4H_PHY_EN_ENABLE_CLK BIT(0 )#define V4H_ST_PHYST_REG 0 x2814#define V4H_ST_PHYST_ST_PHY_READY BIT(31 )#define V4H_ST_PHYST_ST_STOPSTATE_3 BIT(3 )#define V4H_ST_PHYST_ST_STOPSTATE_2 BIT(2 )#define V4H_ST_PHYST_ST_STOPSTATE_1 BIT(1 )#define V4H_ST_PHYST_ST_STOPSTATE_0 BIT(0 )/* V4H PPI registers */ #define V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(n) (0 x21800 + ((n) * 2 )) /* n = 0 - 9 */ #define V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG 0 x21822#define V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG 0 x2184c#define V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG 0 x21c02#define V4H_PPI_RW_LPDCOCAL_NREF_REG 0 x21c04#define V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG 0 x21c06#define V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG 0 x21c0a#define V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG 0 x21c0c#define V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG 0 x21c10#define V4H_PPI_RW_DDLCAL_CFG_n_REG(n) (0 x21c40 + ((n) * 2 )) /* n = 0 - 7 */ #define V4H_PPI_RW_COMMON_CFG_REG 0 x21c6c#define V4H_PPI_RW_TERMCAL_CFG_0_REG 0 x21c80#define V4H_PPI_RW_OFFSETCAL_CFG_0_REG 0 x21ca0/* V4H CORE registers */ #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, n) (0 x22040 + ((l) * 0 x400) + ((n) * 2 ))#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_3_REG(l, n) (0 x22060 + ((l) * 0 x400) + ((n) * 2 ))#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_4_REG(l, n) (0 x22080 + ((l) * 0 x400) + ((n) * 2 ))#define V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(n) (0 x23840 + ((n) * 2 )) /* n = 0 - 11 */ #define V4H_CORE_DIG_RW_COMMON_REG(n) (0 x23880 + ((n) * 2 )) /* n = 0 - 15 */ #define V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(n) (0 x239e0 + ((n) * 2 )) /* n = 0 - 3 */ #define V4H_CORE_DIG_COMMON_RW_DESKEW_FINE_MEM_REG 0 x23fe0#define V4H_CORE_DIG_DLANE_l_RW_CFG_n_REG(l, n) (0 x26000 + ((l) * 0 x400) + ((n) * 2 ))#define V4H_CORE_DIG_DLANE_l_RW_LP_n_REG(l, n) (0 x26080 + ((l) * 0 x400) + ((n) * 2 ))#define V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, n) (0 x26100 + ((l) * 0 x400) + ((n) * 2 ))#define V4H_CORE_DIG_DLANE_CLK_RW_LP_n_REG(n) V4H_CORE_DIG_DLANE_l_RW_LP_n_REG(4 , (n))#define V4H_CORE_DIG_DLANE_CLK_RW_HS_RX_n_REG(n) V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(4 , (n))/* V4H C-PHY */ #define V4H_CORE_DIG_RW_TRIO0_REG(n) (0 x22100 + ((n) * 2 )) /* n = 0 - 3 */ #define V4H_CORE_DIG_RW_TRIO1_REG(n) (0 x22500 + ((n) * 2 )) /* n = 0 - 3 */ #define V4H_CORE_DIG_RW_TRIO2_REG(n) (0 x22900 + ((n) * 2 )) /* n = 0 - 3 */ #define V4H_CORE_DIG_CLANE_0_RW_CFG_0_REG 0 x2a000#define V4H_CORE_DIG_CLANE_0_RW_LP_0_REG 0 x2a080#define V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(n) (0 x2a100 + ((n) * 2 )) /* n = 0 - 6 */ #define V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG 0 x2a400#define V4H_CORE_DIG_CLANE_1_RW_LP_0_REG 0 x2a480#define V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(n) (0 x2a500 + ((n) * 2 )) /* n = 0 - 6 */ #define V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG 0 x2a60c#define V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG 0 x2a800#define V4H_CORE_DIG_CLANE_2_RW_LP_0_REG 0 x2a880#define V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(n) (0 x2a900 + ((n) * 2 )) /* n = 0 - 6 */ struct rcsi2_cphy_setting {static const struct rcsi2_cphy_setting cphy_setting_table_r8a779g0[] = {80 , .rx2 = 0 x38, .trio0 = 0 x024a, .trio1 = 0 x0134, .trio2 = 0 x6a, .lane27 = 0 x0000, .lane29 = 0 x0a24 },100 , .rx2 = 0 x38, .trio0 = 0 x024a, .trio1 = 0 x00f5, .trio2 = 0 x55, .lane27 = 0 x0000, .lane29 = 0 x0a24 },200 , .rx2 = 0 x38, .trio0 = 0 x024a, .trio1 = 0 x0077, .trio2 = 0 x2b, .lane27 = 0 x0000, .lane29 = 0 x0a44 },300 , .rx2 = 0 x38, .trio0 = 0 x024a, .trio1 = 0 x004d, .trio2 = 0 x1d, .lane27 = 0 x0000, .lane29 = 0 x0a44 },400 , .rx2 = 0 x38, .trio0 = 0 x024a, .trio1 = 0 x0038, .trio2 = 0 x16, .lane27 = 0 x0000, .lane29 = 0 x0a64 },500 , .rx2 = 0 x38, .trio0 = 0 x024a, .trio1 = 0 x002b, .trio2 = 0 x12, .lane27 = 0 x0000, .lane29 = 0 x0a64 },600 , .rx2 = 0 x38, .trio0 = 0 x024a, .trio1 = 0 x0023, .trio2 = 0 x0f, .lane27 = 0 x0000, .lane29 = 0 x0a64 },700 , .rx2 = 0 x38, .trio0 = 0 x024a, .trio1 = 0 x001d, .trio2 = 0 x0d, .lane27 = 0 x0000, .lane29 = 0 x0a84 },800 , .rx2 = 0 x38, .trio0 = 0 x024a, .trio1 = 0 x0018, .trio2 = 0 x0c, .lane27 = 0 x0000, .lane29 = 0 x0a84 },900 , .rx2 = 0 x38, .trio0 = 0 x024a, .trio1 = 0 x0015, .trio2 = 0 x0b, .lane27 = 0 x0000, .lane29 = 0 x0a84 },1000 , .rx2 = 0 x3e, .trio0 = 0 x024a, .trio1 = 0 x0012, .trio2 = 0 x0a, .lane27 = 0 x0400, .lane29 = 0 x0a84 },1100 , .rx2 = 0 x44, .trio0 = 0 x024a, .trio1 = 0 x000f, .trio2 = 0 x09, .lane27 = 0 x0800, .lane29 = 0 x0a84 },1200 , .rx2 = 0 x4a, .trio0 = 0 x024a, .trio1 = 0 x000e, .trio2 = 0 x08, .lane27 = 0 x0c00, .lane29 = 0 x0a84 },1300 , .rx2 = 0 x51, .trio0 = 0 x024a, .trio1 = 0 x000c, .trio2 = 0 x08, .lane27 = 0 x0c00, .lane29 = 0 x0aa4 },1400 , .rx2 = 0 x57, .trio0 = 0 x024a, .trio1 = 0 x000b, .trio2 = 0 x07, .lane27 = 0 x1000, .lane29 = 0 x0aa4 },1500 , .rx2 = 0 x5d, .trio0 = 0 x044a, .trio1 = 0 x0009, .trio2 = 0 x07, .lane27 = 0 x1000, .lane29 = 0 x0aa4 },1600 , .rx2 = 0 x63, .trio0 = 0 x044a, .trio1 = 0 x0008, .trio2 = 0 x07, .lane27 = 0 x1400, .lane29 = 0 x0aa4 },1700 , .rx2 = 0 x6a, .trio0 = 0 x044a, .trio1 = 0 x0007, .trio2 = 0 x06, .lane27 = 0 x1400, .lane29 = 0 x0aa4 },1800 , .rx2 = 0 x70, .trio0 = 0 x044a, .trio1 = 0 x0007, .trio2 = 0 x06, .lane27 = 0 x1400, .lane29 = 0 x0aa4 },1900 , .rx2 = 0 x76, .trio0 = 0 x044a, .trio1 = 0 x0006, .trio2 = 0 x06, .lane27 = 0 x1400, .lane29 = 0 x0aa4 },2000 , .rx2 = 0 x7c, .trio0 = 0 x044a, .trio1 = 0 x0005, .trio2 = 0 x06, .lane27 = 0 x1800, .lane29 = 0 x0aa4 },2100 , .rx2 = 0 x83, .trio0 = 0 x044a, .trio1 = 0 x0005, .trio2 = 0 x05, .lane27 = 0 x1800, .lane29 = 0 x0aa4 },2200 , .rx2 = 0 x89, .trio0 = 0 x064a, .trio1 = 0 x0004, .trio2 = 0 x05, .lane27 = 0 x1800, .lane29 = 0 x0aa4 },2300 , .rx2 = 0 x8f, .trio0 = 0 x064a, .trio1 = 0 x0003, .trio2 = 0 x05, .lane27 = 0 x1800, .lane29 = 0 x0aa4 },2400 , .rx2 = 0 x95, .trio0 = 0 x064a, .trio1 = 0 x0003, .trio2 = 0 x05, .lane27 = 0 x1800, .lane29 = 0 x0aa4 },2500 , .rx2 = 0 x9c, .trio0 = 0 x064a, .trio1 = 0 x0003, .trio2 = 0 x05, .lane27 = 0 x1c00, .lane29 = 0 x0aa4 },2600 , .rx2 = 0 xa2, .trio0 = 0 x064a, .trio1 = 0 x0002, .trio2 = 0 x05, .lane27 = 0 x1c00, .lane29 = 0 x0ad4 },2700 , .rx2 = 0 xa8, .trio0 = 0 x064a, .trio1 = 0 x0002, .trio2 = 0 x05, .lane27 = 0 x1c00, .lane29 = 0 x0ad4 },2800 , .rx2 = 0 xae, .trio0 = 0 x064a, .trio1 = 0 x0002, .trio2 = 0 x04, .lane27 = 0 x1c00, .lane29 = 0 x0ad4 },2900 , .rx2 = 0 xb5, .trio0 = 0 x084a, .trio1 = 0 x0001, .trio2 = 0 x04, .lane27 = 0 x1c00, .lane29 = 0 x0ad4 },3000 , .rx2 = 0 xbb, .trio0 = 0 x084a, .trio1 = 0 x0001, .trio2 = 0 x04, .lane27 = 0 x1c00, .lane29 = 0 x0ad4 },3100 , .rx2 = 0 xc1, .trio0 = 0 x084a, .trio1 = 0 x0001, .trio2 = 0 x04, .lane27 = 0 x1c00, .lane29 = 0 x0ad4 },3200 , .rx2 = 0 xc7, .trio0 = 0 x084a, .trio1 = 0 x0001, .trio2 = 0 x04, .lane27 = 0 x1c00, .lane29 = 0 x0ad4 },3300 , .rx2 = 0 xce, .trio0 = 0 x084a, .trio1 = 0 x0001, .trio2 = 0 x04, .lane27 = 0 x1c00, .lane29 = 0 x0ad4 },3400 , .rx2 = 0 xd4, .trio0 = 0 x084a, .trio1 = 0 x0001, .trio2 = 0 x04, .lane27 = 0 x1c00, .lane29 = 0 x0ad4 },3500 , .rx2 = 0 xda, .trio0 = 0 x084a, .trio1 = 0 x0001, .trio2 = 0 x04, .lane27 = 0 x1c00, .lane29 = 0 x0ad4 },/* sentinel */ }, /* V4M registers */ #define V4M_OVR1_REG 0 x0848#define V4M_OVR1_FORCERXMODE_3 BIT(12 )#define V4M_OVR1_FORCERXMODE_2 BIT(11 )#define V4M_OVR1_FORCERXMODE_1 BIT(10 )#define V4M_OVR1_FORCERXMODE_0 BIT(9 )#define V4M_FRXM_REG 0 x2004#define V4M_FRXM_FORCERXMODE_3 BIT(3 )#define V4M_FRXM_FORCERXMODE_2 BIT(2 )#define V4M_FRXM_FORCERXMODE_1 BIT(1 )#define V4M_FRXM_FORCERXMODE_0 BIT(0 )#define V4M_PHYPLL_REG 0 x02050#define V4M_CSI0CLKFCPR_REG 0 x02054#define V4M_PHTW_REG 0 x02060#define V4M_PHTR_REG 0 x02064#define V4M_PHTC_REG 0 x02068struct phtw_value {struct rcsi2_mbps_info {/* V4M */ static const struct rcsi2_mbps_info phtw_mbps_v3u[] = {1500 , .reg = 0 xcc },1550 , .reg = 0 x1d },1600 , .reg = 0 x27 },1650 , .reg = 0 x30 },1700 , .reg = 0 x39 },1750 , .reg = 0 x42 },1800 , .reg = 0 x4b },1850 , .reg = 0 x55 },1900 , .reg = 0 x5e },1950 , .reg = 0 x67 },2000 , .reg = 0 x71 },2050 , .reg = 0 x79 },2100 , .reg = 0 x83 },2150 , .reg = 0 x8c },2200 , .reg = 0 x95 },2250 , .reg = 0 x9e },2300 , .reg = 0 xa7 },2350 , .reg = 0 xb0 },2400 , .reg = 0 xba },2450 , .reg = 0 xc3 },2500 , .reg = 0 xcc },/* sentinel */ }, static const struct rcsi2_mbps_info phtw_mbps_h3_v3h_m3n[] = {80 , .reg = 0 x86 },90 , .reg = 0 x86 },100 , .reg = 0 x87 },110 , .reg = 0 x87 },120 , .reg = 0 x88 },130 , .reg = 0 x88 },140 , .reg = 0 x89 },150 , .reg = 0 x89 },160 , .reg = 0 x8a },170 , .reg = 0 x8a },180 , .reg = 0 x8b },190 , .reg = 0 x8b },205 , .reg = 0 x8c },220 , .reg = 0 x8d },235 , .reg = 0 x8e },250 , .reg = 0 x8e },/* sentinel */ }, static const struct rcsi2_mbps_info phtw_mbps_v3m_e3[] = {80 , .reg = 0 x00 },90 , .reg = 0 x20 },100 , .reg = 0 x40 },110 , .reg = 0 x02 },130 , .reg = 0 x22 },140 , .reg = 0 x42 },150 , .reg = 0 x04 },170 , .reg = 0 x24 },180 , .reg = 0 x44 },200 , .reg = 0 x06 },220 , .reg = 0 x26 },240 , .reg = 0 x46 },250 , .reg = 0 x08 },270 , .reg = 0 x28 },300 , .reg = 0 x0a },330 , .reg = 0 x2a },360 , .reg = 0 x4a },400 , .reg = 0 x0c },450 , .reg = 0 x2c },500 , .reg = 0 x0e },550 , .reg = 0 x2e },600 , .reg = 0 x10 },650 , .reg = 0 x30 },700 , .reg = 0 x12 },750 , .reg = 0 x32 },800 , .reg = 0 x52 },850 , .reg = 0 x72 },900 , .reg = 0 x14 },950 , .reg = 0 x34 },1000 , .reg = 0 x54 },1050 , .reg = 0 x74 },1125 , .reg = 0 x16 },/* sentinel */ }, /* PHY Test Interface Clear */ #define PHTC_REG 0 x58#define PHTC_TESTCLR BIT(0 )/* PHY Frequency Control */ #define PHYPLL_REG 0 x68#define PHYPLL_HSFREQRANGE(n) ((n) << 16 )static const struct rcsi2_mbps_info hsfreqrange_v3u[] = {80 , .reg = 0 x00 },90 , .reg = 0 x10 },100 , .reg = 0 x20 },110 , .reg = 0 x30 },120 , .reg = 0 x01 },130 , .reg = 0 x11 },140 , .reg = 0 x21 },150 , .reg = 0 x31 },160 , .reg = 0 x02 },170 , .reg = 0 x12 },180 , .reg = 0 x22 },190 , .reg = 0 x32 },205 , .reg = 0 x03 },220 , .reg = 0 x13 },235 , .reg = 0 x23 },250 , .reg = 0 x33 },275 , .reg = 0 x04 },300 , .reg = 0 x14 },325 , .reg = 0 x25 },350 , .reg = 0 x35 },400 , .reg = 0 x05 },450 , .reg = 0 x16 },500 , .reg = 0 x26 },550 , .reg = 0 x37 },600 , .reg = 0 x07 },650 , .reg = 0 x18 },700 , .reg = 0 x28 },750 , .reg = 0 x39 },800 , .reg = 0 x09 },850 , .reg = 0 x19 },900 , .reg = 0 x29 },950 , .reg = 0 x3a },1000 , .reg = 0 x0a },1050 , .reg = 0 x1a },1100 , .reg = 0 x2a },1150 , .reg = 0 x3b },1200 , .reg = 0 x0b },1250 , .reg = 0 x1b },1300 , .reg = 0 x2b },1350 , .reg = 0 x3c },1400 , .reg = 0 x0c },1450 , .reg = 0 x1c },1500 , .reg = 0 x2c },1550 , .reg = 0 x3d },1600 , .reg = 0 x0d },1650 , .reg = 0 x1d },1700 , .reg = 0 x2e },1750 , .reg = 0 x3e },1800 , .reg = 0 x0e },1850 , .reg = 0 x1e },1900 , .reg = 0 x2f },1950 , .reg = 0 x3f },2000 , .reg = 0 x0f },2050 , .reg = 0 x40 },2100 , .reg = 0 x41 },2150 , .reg = 0 x42 },2200 , .reg = 0 x43 },2300 , .reg = 0 x45 },2350 , .reg = 0 x46 },2400 , .reg = 0 x47 },2450 , .reg = 0 x48 },2500 , .reg = 0 x49 },/* sentinel */ }, static const struct rcsi2_mbps_info hsfreqrange_h3_v3h_m3n[] = {80 , .reg = 0 x00 },90 , .reg = 0 x10 },100 , .reg = 0 x20 },110 , .reg = 0 x30 },120 , .reg = 0 x01 },130 , .reg = 0 x11 },140 , .reg = 0 x21 },150 , .reg = 0 x31 },160 , .reg = 0 x02 },170 , .reg = 0 x12 },180 , .reg = 0 x22 },190 , .reg = 0 x32 },205 , .reg = 0 x03 },220 , .reg = 0 x13 },235 , .reg = 0 x23 },250 , .reg = 0 x33 },275 , .reg = 0 x04 },300 , .reg = 0 x14 },325 , .reg = 0 x25 },350 , .reg = 0 x35 },400 , .reg = 0 x05 },450 , .reg = 0 x16 },500 , .reg = 0 x26 },550 , .reg = 0 x37 },600 , .reg = 0 x07 },650 , .reg = 0 x18 },700 , .reg = 0 x28 },750 , .reg = 0 x39 },800 , .reg = 0 x09 },850 , .reg = 0 x19 },900 , .reg = 0 x29 },950 , .reg = 0 x3a },1000 , .reg = 0 x0a },1050 , .reg = 0 x1a },1100 , .reg = 0 x2a },1150 , .reg = 0 x3b },1200 , .reg = 0 x0b },1250 , .reg = 0 x1b },1300 , .reg = 0 x2b },1350 , .reg = 0 x3c },1400 , .reg = 0 x0c },1450 , .reg = 0 x1c },1500 , .reg = 0 x2c },/* sentinel */ }, static const struct rcsi2_mbps_info hsfreqrange_m3w[] = {80 , .reg = 0 x00 },90 , .reg = 0 x10 },100 , .reg = 0 x20 },110 , .reg = 0 x30 },120 , .reg = 0 x01 },130 , .reg = 0 x11 },140 , .reg = 0 x21 },150 , .reg = 0 x31 },160 , .reg = 0 x02 },170 , .reg = 0 x12 },180 , .reg = 0 x22 },190 , .reg = 0 x32 },205 , .reg = 0 x03 },220 , .reg = 0 x13 },235 , .reg = 0 x23 },250 , .reg = 0 x33 },275 , .reg = 0 x04 },300 , .reg = 0 x14 },325 , .reg = 0 x05 },350 , .reg = 0 x15 },400 , .reg = 0 x25 },450 , .reg = 0 x06 },500 , .reg = 0 x16 },550 , .reg = 0 x07 },600 , .reg = 0 x17 },650 , .reg = 0 x08 },700 , .reg = 0 x18 },750 , .reg = 0 x09 },800 , .reg = 0 x19 },850 , .reg = 0 x29 },900 , .reg = 0 x39 },950 , .reg = 0 x0a },1000 , .reg = 0 x1a },1050 , .reg = 0 x2a },1100 , .reg = 0 x3a },1150 , .reg = 0 x0b },1200 , .reg = 0 x1b },1250 , .reg = 0 x2b },1300 , .reg = 0 x3b },1350 , .reg = 0 x0c },1400 , .reg = 0 x1c },1450 , .reg = 0 x2c },1500 , .reg = 0 x3c },/* sentinel */ }, static const struct rcsi2_mbps_info hsfreqrange_v4m[] = {80 , .reg = 0 x00, .osc_freq = 0 x01a9 },90 , .reg = 0 x10, .osc_freq = 0 x01a9 },100 , .reg = 0 x20, .osc_freq = 0 x01a9 },110 , .reg = 0 x30, .osc_freq = 0 x01a9 },120 , .reg = 0 x01, .osc_freq = 0 x01a9 },130 , .reg = 0 x11, .osc_freq = 0 x01a9 },140 , .reg = 0 x21, .osc_freq = 0 x01a9 },150 , .reg = 0 x31, .osc_freq = 0 x01a9 },160 , .reg = 0 x02, .osc_freq = 0 x01a9 },170 , .reg = 0 x12, .osc_freq = 0 x01a9 },180 , .reg = 0 x22, .osc_freq = 0 x01a9 },190 , .reg = 0 x32, .osc_freq = 0 x01a9 },205 , .reg = 0 x03, .osc_freq = 0 x01a9 },220 , .reg = 0 x13, .osc_freq = 0 x01a9 },235 , .reg = 0 x23, .osc_freq = 0 x01a9 },250 , .reg = 0 x33, .osc_freq = 0 x01a9 },275 , .reg = 0 x04, .osc_freq = 0 x01a9 },300 , .reg = 0 x14, .osc_freq = 0 x01a9 },325 , .reg = 0 x25, .osc_freq = 0 x01a9 },350 , .reg = 0 x35, .osc_freq = 0 x01a9 },400 , .reg = 0 x05, .osc_freq = 0 x01a9 },450 , .reg = 0 x16, .osc_freq = 0 x01a9 },500 , .reg = 0 x26, .osc_freq = 0 x01a9 },550 , .reg = 0 x37, .osc_freq = 0 x01a9 },600 , .reg = 0 x07, .osc_freq = 0 x01a9 },650 , .reg = 0 x18, .osc_freq = 0 x01a9 },700 , .reg = 0 x28, .osc_freq = 0 x01a9 },750 , .reg = 0 x39, .osc_freq = 0 x01a9 },800 , .reg = 0 x09, .osc_freq = 0 x01a9 },850 , .reg = 0 x19, .osc_freq = 0 x01a9 },900 , .reg = 0 x29, .osc_freq = 0 x01a9 },950 , .reg = 0 x3a, .osc_freq = 0 x01a9 },1000 , .reg = 0 x0a, .osc_freq = 0 x01a9 },1050 , .reg = 0 x1a, .osc_freq = 0 x01a9 },1100 , .reg = 0 x2a, .osc_freq = 0 x01a9 },1150 , .reg = 0 x3b, .osc_freq = 0 x01a9 },1200 , .reg = 0 x0b, .osc_freq = 0 x01a9 },1250 , .reg = 0 x1b, .osc_freq = 0 x01a9 },1300 , .reg = 0 x2b, .osc_freq = 0 x01a9 },1350 , .reg = 0 x3c, .osc_freq = 0 x01a9 },1400 , .reg = 0 x0c, .osc_freq = 0 x01a9 },1450 , .reg = 0 x1c, .osc_freq = 0 x01a9 },1500 , .reg = 0 x2c, .osc_freq = 0 x01a9 },1550 , .reg = 0 x3d, .osc_freq = 0 x0108 },1600 , .reg = 0 x0d, .osc_freq = 0 x0110 },1650 , .reg = 0 x1d, .osc_freq = 0 x0119 },1700 , .reg = 0 x2e, .osc_freq = 0 x0121 },1750 , .reg = 0 x3e, .osc_freq = 0 x012a },1800 , .reg = 0 x0e, .osc_freq = 0 x0132 },1850 , .reg = 0 x1e, .osc_freq = 0 x013b },1900 , .reg = 0 x2f, .osc_freq = 0 x0143 },1950 , .reg = 0 x3f, .osc_freq = 0 x014c },2000 , .reg = 0 x0f, .osc_freq = 0 x0154 },2050 , .reg = 0 x40, .osc_freq = 0 x015d },2100 , .reg = 0 x41, .osc_freq = 0 x0165 },2150 , .reg = 0 x42, .osc_freq = 0 x016e },2200 , .reg = 0 x43, .osc_freq = 0 x0176 },2250 , .reg = 0 x44, .osc_freq = 0 x017f },2300 , .reg = 0 x45, .osc_freq = 0 x0187 },2350 , .reg = 0 x46, .osc_freq = 0 x0190 },2400 , .reg = 0 x47, .osc_freq = 0 x0198 },2450 , .reg = 0 x48, .osc_freq = 0 x01a1 },2500 , .reg = 0 x49, .osc_freq = 0 x01a9 },/* sentinel */ }, /* PHY ESC Error Monitor */ #define PHEERM_REG 0 x74/* PHY Clock Lane Monitor */ #define PHCLM_REG 0 x78#define PHCLM_STOPSTATECKL BIT(0 )/* PHY Data Lane Monitor */ #define PHDLM_REG 0 x7c/* CSI0CLK Frequency Configuration Preset Register */ #define CSI0CLKFCPR_REG 0 x260#define CSI0CLKFREQRANGE(n) ((n & 0 x3f) << 16 )struct rcar_csi2_format {unsigned int datatype;unsigned int bpp;static const struct rcar_csi2_format rcar_csi2_formats[] = {24 ,16 ,16 ,16 ,20 ,8 ,10 ,8 ,8 ,8 ,8 ,10 ,10 ,10 ,10 ,12 ,12 ,12 ,12 ,static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code)unsigned int i;for (i = 0 ; i < ARRAY_SIZE(rcar_csi2_formats); i++)if (rcar_csi2_formats[i].code == code)return &rcar_csi2_formats[i];return NULL;struct rcsi2_cphy_line_order {enum v4l2_mbus_csi2_cphy_line_orders_type order;static const struct rcsi2_cphy_line_order rcsi2_cphy_line_orders[] = {0 x0, .ctrl29 = 0 x0 },0 xa, .ctrl29 = 0 x1 },0 xc, .ctrl29 = 0 x1 },0 x5, .ctrl29 = 0 x0 },0 x3, .ctrl29 = 0 x0 },0 x9, .ctrl29 = 0 x1 }enum rcar_csi2_pads {struct rcsi2_register_layout {unsigned int phtw;unsigned int phypll;struct rcar_csi2_info {const struct rcsi2_register_layout *regs;int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps);int (*phy_post_init)(struct rcar_csi2 *priv);int (*start_receiver)(struct rcar_csi2 *priv,struct v4l2_subdev_state *state);void (*enter_standby)(struct rcar_csi2 *priv);const struct rcsi2_mbps_info *hsfreqrange;unsigned int csi0clkfreqrange;unsigned int num_channels;bool clear_ulps;bool use_isp;bool support_dphy;bool support_cphy;struct rcar_csi2 {struct device *dev;void __iomem *base;const struct rcar_csi2_info *info;struct reset_control *rstc;struct v4l2_subdev subdev;struct media_pad pads[NR_OF_RCAR_CSI2_PAD];struct v4l2_async_notifier notifier;struct v4l2_subdev *remote;unsigned int remote_pad;int channel_vc[4 ];int stream_count;bool cphy;unsigned short lanes;unsigned char lane_swap[4 ];enum v4l2_mbus_csi2_cphy_line_orders_type line_orders[3 ];static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd)return container_of(sd, struct rcar_csi2, subdev);static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)return container_of(n, struct rcar_csi2, notifier);static unsigned int rcsi2_num_pads(const struct rcar_csi2 *priv)/* Used together with R-Car ISP: one sink and one source pad. */ if (priv->info->use_isp)return 2 ;/* Used together with R-Car VIN: one sink and four source pads. */ return 5 ;static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg)return ioread32(priv->base + reg);static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data)static u16 rcsi2_read16(struct rcar_csi2 *priv, unsigned int reg)return ioread16(priv->base + reg);static void rcsi2_write16(struct rcar_csi2 *priv, unsigned int reg, u16 data)static void rcsi2_modify16(struct rcar_csi2 *priv, unsigned int reg, u16 data, u16 mask)static int rcsi2_phtw_write(struct rcar_csi2 *priv, u8 data, u8 code)unsigned int timeout;/* Wait for DWEN and CWEN to be cleared by hardware. */ for (timeout = 0 ; timeout <= 20 ; timeout++) {if (!(rcsi2_read(priv, priv->info->regs->phtw) & (PHTW_DWEN | PHTW_CWEN)))return 0 ;1000 , 2000 );"Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n" );return -ETIMEDOUT;static int rcsi2_phtw_write_array(struct rcar_csi2 *priv,const struct phtw_value *values,unsigned int size)int ret;for (unsigned int i = 0 ; i < size; i++) {if (ret)return ret;return 0 ;static const struct rcsi2_mbps_info *struct rcar_csi2 *priv,const struct rcsi2_mbps_info *infotable, unsigned int mbps)const struct rcsi2_mbps_info *info;const struct rcsi2_mbps_info *prev = NULL;if (mbps < infotable->mbps)"%u Mbps less than min PHY speed %u Mbps" ,for (info = infotable; info->mbps != 0 ; info++) {if (info->mbps >= mbps)break ;if (!info->mbps) {"Unsupported PHY speed (%u Mbps)" , mbps);return NULL;if (prev && ((mbps - prev->mbps) <= (info->mbps - mbps)))return info;static void rcsi2_enter_standby_gen3(struct rcar_csi2 *priv)0 );static void rcsi2_enter_standby(struct rcar_csi2 *priv)if (priv->info->enter_standby)100 , 150 );static int rcsi2_exit_standby(struct rcar_csi2 *priv)int ret;if (ret < 0 )return ret;return 0 ;static int rcsi2_wait_phy_start(struct rcar_csi2 *priv,unsigned int lanes)unsigned int timeout;/* Wait for the clock and data lanes to enter LP-11 state. */ for (timeout = 0 ; timeout <= 20 ; timeout++) {const u32 lane_mask = (1 << lanes) - 1 ;if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) &&return 0 ;1000 , 2000 );"Timeout waiting for LP-11 state\n" );return -ETIMEDOUT;static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps)const struct rcsi2_mbps_info *info;if (!info)return -ERANGE;return 0 ;static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp,unsigned int lanes)struct media_pad *remote_pad;struct v4l2_subdev *source;if (!priv->remote)return -ENODEV;2 * lanes);if (freq < 0 ) {int ret = (int )freq;"failed to get link freq for %s: %d\n" ,return ret;2 , MEGA);return mbps;static int rcsi2_get_active_lanes(struct rcar_csi2 *priv,unsigned int *lanes)struct v4l2_mbus_config mbus_config = { 0 };int ret;if (ret == -ENOIOCTLCMD) {"No remote mbus configuration available\n" );return 0 ;if (ret) {"Failed to get remote mbus configuration\n" );return ret;switch (mbus_config.type) {case V4L2_MBUS_CSI2_CPHY:if (!priv->cphy)return -EINVAL;break ;case V4L2_MBUS_CSI2_DPHY:if (priv->cphy)return -EINVAL;break ;default :"Unsupported media bus type %u\n" ,return -EINVAL;if (mbus_config.bus.mipi_csi2.num_data_lanes > priv->lanes) {"Unsupported mbus config: too many data lanes %u\n" ,return -EINVAL;return 0 ;static int rcsi2_start_receiver_gen3(struct rcar_csi2 *priv,struct v4l2_subdev_state *state)const struct rcar_csi2_format *format;0 , vcdt2 = 0 , fld = 0 ;const struct v4l2_mbus_framefmt *fmt;unsigned int lanes;unsigned int i;int mbps, ret;/* Use the format on the sink pad to compute the receiver config. */ "Input size (%ux%u%c)\n" ,'p' : 'i' );/* Code is validated in set_fmt. */ if (!format)return -EINVAL;/* * Enable all supported CSI-2 channels with virtual channel and * data type matching. * * NOTE: It's not possible to get individual datatype for each * source virtual channel. Once this is possible in V4L2 * it should be used here. for (i = 0 ; i < priv->info->num_channels; i++) {if (priv->channel_vc[i] < 0 )continue ;/* Store in correct reg and offset. */ if (i < 2 )2 ) * 16 );else 2 ) * 16 );if (fmt->field == V4L2_FIELD_ALTERNATE)1 ) | FLD_FLD_EN4 | FLD_FLD_EN3 | FLD_FLD_EN2/* * Get the number of active data lanes inspecting the remote mbus * configuration. if (ret)return ret;1 << lanes) - 1 ;if (mbps < 0 )return mbps;/* Enable interrupts. */ /* Init */ 0 );/* Configure */ if (!priv->info->use_isp) {if (vcdt2)/* Lanes are zero indexed. */ 0 ] - 1 ) |1 ] - 1 ) |2 ] - 1 ) |3 ] - 1 ));/* Start */ if (priv->info->init_phtw) {if (ret)return ret;if (priv->info->hsfreqrange) {if (ret)return ret;if (priv->info->csi0clkfreqrange)if (priv->info->use_isp)if (ret)return ret;if (priv->info->use_isp)0 );/* Run post PHY start initialization, if needed. */ if (priv->info->phy_post_init) {if (ret)return ret;/* Clear Ultra Low Power interrupt. */ if (priv->info->clear_ulps)return 0 ;static void rsci2_set_line_order(struct rcar_csi2 *priv,enum v4l2_mbus_csi2_cphy_line_orders_type order,unsigned int cfgreg, unsigned int ctrlreg)const struct rcsi2_cphy_line_order *info = NULL;for (unsigned int i = 0 ; i < ARRAY_SIZE(rcsi2_cphy_line_orders); i++) {if (rcsi2_cphy_line_orders[i].order == order) {break ;if (!info)return ;0 x000f);0 x0100);static int rcsi2_wait_phy_start_v4h(struct rcar_csi2 *priv, u32 match)unsigned int timeout;for (timeout = 0 ; timeout <= 10 ; timeout++) {if ((status & match) == match)return 0 ;1000 , 2000 );return -ETIMEDOUT;static const struct rcsi2_cphy_setting *struct rcar_csi2 *priv, int mbps)const struct rcsi2_cphy_setting *conf;int msps;/* Adjust for C-PHY symbols, divide by 2.8. */ 5 , 14 );for (conf = cphy_setting_table_r8a779g0; conf->msps != 0 ; conf++) {if (conf->msps > msps)break ;if (!conf->msps) {"Unsupported PHY speed for msps setting (%u Msps)" , msps);return NULL;/* C-PHY specific */ 7 ), 0 x0155);7 ), 0 x0068);8 ), 0 x0010);0 x463c);0 x463c);0 x463c);0 ), 0 x00d5);0 ), 0 x00d5);0 ), 0 x00d5);1 ), 0 x0013);1 ), 0 x0013);1 ), 0 x0013);5 ), 0 x0013);5 ), 0 x0013);5 ), 0 x0013);6 ), 0 x000a);6 ), 0 x000a);6 ), 0 x000a);2 ), conf->rx2);2 ), conf->rx2);2 ), conf->rx2);0 , 2 ), 0 x0001);1 , 2 ), 0 );2 , 2 ), 0 x0001);3 , 2 ), 0 x0001);4 , 2 ), 0 );0 ), conf->trio0);0 ), conf->trio0);0 ), conf->trio0);2 ), conf->trio2);2 ), conf->trio2);2 ), conf->trio2);1 ), conf->trio1);1 ), conf->trio1);1 ), conf->trio1);/* Configure data line order. */ 0 ],0 , 9 ));1 ],1 , 9 ));2 ],2 , 9 ));/* TODO: This registers is not documented. */ 0 x5000);return conf;struct rcsi2_d_phy_setting_v4h_lut_value {unsigned int mbps;unsigned char cfg_1;unsigned char cfg_5_94;unsigned char cfg_5_30;unsigned char lane_ctrl_2_8;unsigned char rw_hs_rx_3_83;unsigned char rw_hs_rx_3_20;unsigned char rw_hs_rx_6;unsigned char rw_hs_rx_1;static const struct rcsi2_d_phy_setting_v4h_lut_value *int mbps)static const struct rcsi2_d_phy_setting_v4h_lut_value values[] = {4500 , 0 x3f, 0 x07, 0 x00, 0 x01, 0 x02, 0 x01, 0 x0d, 0 x10 },4000 , 0 x47, 0 x08, 0 x01, 0 x01, 0 x05, 0 x01, 0 x0f, 0 x0d },3600 , 0 x4f, 0 x09, 0 x01, 0 x01, 0 x06, 0 x01, 0 x10, 0 x0b },3230 , 0 x57, 0 x0a, 0 x01, 0 x01, 0 x06, 0 x01, 0 x12, 0 x09 },3000 , 0 x47, 0 x08, 0 x00, 0 x00, 0 x03, 0 x01, 0 x0f, 0 x0c },2700 , 0 x4f, 0 x09, 0 x01, 0 x00, 0 x06, 0 x01, 0 x10, 0 x0b },2455 , 0 x57, 0 x0a, 0 x01, 0 x00, 0 x06, 0 x01, 0 x12, 0 x09 },2250 , 0 x5f, 0 x0b, 0 x01, 0 x00, 0 x08, 0 x01, 0 x13, 0 x08 },2077 , 0 x67, 0 x0c, 0 x01, 0 x00, 0 x06, 0 x02, 0 x15, 0 x0d },1929 , 0 x6f, 0 x0d, 0 x02, 0 x00, 0 x06, 0 x02, 0 x17, 0 x0d },1800 , 0 x77, 0 x0e, 0 x02, 0 x00, 0 x06, 0 x02, 0 x18, 0 x0d },1688 , 0 x7f, 0 x0f, 0 x02, 0 x00, 0 x08, 0 x02, 0 x1a, 0 x0d },1588 , 0 x87, 0 x10, 0 x02, 0 x00, 0 x08, 0 x02, 0 x1b, 0 x0d },1500 , 0 x8f, 0 x11, 0 x03, 0 x00, 0 x08, 0 x02, 0 x1d, 0 x0c },for (unsigned int i = 0 ; i < ARRAY_SIZE(values); i++)if (mbps >= values[i].mbps)return &values[i];return NULL;static int rcsi2_d_phy_setting_v4h(struct rcar_csi2 *priv, int mbps)const struct rcsi2_d_phy_setting_v4h_lut_value *lut =7 ), 0 x0000);7 ), mbps > 1500 ? 0 x0028 : 0 x0068);8 ), 0 x0050);0 ), 0 x0063);7 ), 0 x1132);1 ), 0 x1340);2 ), 0 x4b13);4 ), 0 x000a);6 ), 0 x800a);7 ), 0 x1109);if (mbps > 1500 ) {5 * mbps, 64 );3 ), val);if (lut) {1 ),0 x00ff);5 ),4 , 0 x03f0);5 ),0 , 0 x000f);for (unsigned int l = 0 ; l < 5 ; l++)8 ),12 , 0 x1000);for (unsigned int l = 0 ; l < 4 ; l++)0 ), 0 x463c);0 , 2 ), 0 x0000);1 , 2 ), 0 x0000);2 , 2 ), 0 x0001);3 , 2 ), 0 x0000);4 , 2 ), 0 x0000);6 ), 0 x0009);1500 ? 0 x0800 : 0 x0802;for (unsigned int l = 0 ; l < 5 ; l++)12 ), val);1500 ? 0 x0000 : 0 x0002;for (unsigned int l = 0 ; l < 5 ; l++)13 ), val);if (mbps >= 80 ) {/* 2560: 6, 1280: 5, 640: 4, 320: 3, 160: 2, 80: 1 */ 80 ) + 1 ;2 , 9 ),5 , 0 xe0);0 ), 0 x091c);7 ), 0 x3b06);1200 , mbps) + 12 ;for (unsigned int l = 0 ; l < 4 ; l++)0 ), val << 8 , 0 xf0);1500 ? 0 x0004 : 0 x0008;for (unsigned int l = 0 ; l < 4 ; l++)1 ), val);2500 ? 0 x669a : mbps > 1500 ? 0 xe69a : 0 xe69b;for (unsigned int l = 0 ; l < 4 ; l++)2 ), val);for (unsigned int l = 0 ; l < 4 ; l++)0 ), 0 x163c);0 ), 0 x163c);if (lut) {for (unsigned int l = 0 ; l < 4 ; l++)1 ),0 xff);for (unsigned int l = 0 ; l < 4 ; l++)3 ), 0 x9209);for (unsigned int l = 0 ; l < 4 ; l++)4 ), 0 x0096);for (unsigned int l = 0 ; l < 4 ; l++)5 ), 0 x0100);for (unsigned int l = 0 ; l < 4 ; l++)6 ), 0 x2d02);for (unsigned int l = 0 ; l < 4 ; l++)7 ), 0 x1b06);if (lut) {/* * Documentation LUT have two values but document writing both * values in a single write. for (unsigned int l = 0 ; l < 4 ; l++)3 ),3 | lut->rw_hs_rx_3_20, 0 x1ff);for (unsigned int l = 0 ; l < 4 ; l++)6 ),8 , 0 xff00);static const u16 deskew_fine[] = {0 x0404, 0 x040c, 0 x0414, 0 x041c, 0 x0423, 0 x0429, 0 x0430, 0 x043a,0 x0445, 0 x044a, 0 x0450, 0 x045a, 0 x0465, 0 x0469, 0 x0472, 0 x047a,0 x0485, 0 x0489, 0 x0490, 0 x049a, 0 x04a4, 0 x04ac, 0 x04b4, 0 x04bc,0 x04c4, 0 x04cc, 0 x04d4, 0 x04dc, 0 x04e4, 0 x04ec, 0 x04f4, 0 x04fc,0 x0504, 0 x050c, 0 x0514, 0 x051c, 0 x0523, 0 x0529, 0 x0530, 0 x053a,0 x0545, 0 x054a, 0 x0550, 0 x055a, 0 x0565, 0 x0569, 0 x0572, 0 x057a,0 x0585, 0 x0589, 0 x0590, 0 x059a, 0 x05a4, 0 x05ac, 0 x05b4, 0 x05bc,0 x05c4, 0 x05cc, 0 x05d4, 0 x05dc, 0 x05e4, 0 x05ec, 0 x05f4, 0 x05fc,0 x0604, 0 x060c, 0 x0614, 0 x061c, 0 x0623, 0 x0629, 0 x0632, 0 x063a,0 x0645, 0 x064a, 0 x0650, 0 x065a, 0 x0665, 0 x0669, 0 x0672, 0 x067a,0 x0685, 0 x0689, 0 x0690, 0 x069a, 0 x06a4, 0 x06ac, 0 x06b4, 0 x06bc,0 x06c4, 0 x06cc, 0 x06d4, 0 x06dc, 0 x06e4, 0 x06ec, 0 x06f4, 0 x06fc,0 x0704, 0 x070c, 0 x0714, 0 x071c, 0 x0723, 0 x072a, 0 x0730, 0 x073a,0 x0745, 0 x074a, 0 x0750, 0 x075a, 0 x0765, 0 x0769, 0 x0772, 0 x077a,0 x0785, 0 x0789, 0 x0790, 0 x079a, 0 x07a4, 0 x07ac, 0 x07b4, 0 x07bc,0 x07c4, 0 x07cc, 0 x07d4, 0 x07dc, 0 x07e4, 0 x07ec, 0 x07f4, 0 x07fc,for (unsigned int i = 0 ; i < ARRAY_SIZE(deskew_fine); i++) {return 0 ;static int rcsi2_start_receiver_v4h(struct rcar_csi2 *priv,struct v4l2_subdev_state *state)const struct rcsi2_cphy_setting *cphy = NULL;const struct rcar_csi2_format *format;const struct v4l2_mbus_framefmt *fmt;unsigned int lanes;int mbps;int ret;/* Use the format on the sink pad to compute the receiver config. */ if (!format)return -EINVAL;if (ret)return ret;if (mbps < 0 )return mbps;/* T0: Reset LINK and PHY*/ 0 );0 );0 );/* T1: PHY static setting */ 0 );0 );0 );1 );/* T2: Reset CSI2 */ 0 ));/* Registers static setting through APB */ /* Common setting */ 10 ), 0 x0030);2 ), 0 x1444);0 ), 0 x1bfd);0 x0233);6 ), 0 x0027);0 x01f4);0 x0013);0 x0003);0 x004f);0 x0320);0 x000f);0 xfe18);0 x0c3c);0 x0105);6 ), 0 x1000);0 x0003);0 ), 0 x0000);1 ), 0 x0400);3 ), 0 x41f6);0 ), 0 x0000);3 ), 0 x43f6);6 ), 0 x3000);7 ), 0 x0000);6 ), 0 x7000);7 ), 0 x0000);5 ), 0 x4000);/* T3: PHY settings */ if (priv->cphy) {if (!cphy)return -ERANGE;else {if (ret)return ret;/* T4: Leave Shutdown mode */ 0 ));0 ));/* T5: Wait for calibration */ if (rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_PHY_READY)) {"PHY calibration failed\n" );return -ETIMEDOUT;/* T6: Analog programming */ if (priv->cphy) {for (unsigned int l = 0 ; l < 3 ; l++) {9 ),7 ),else {2500 ? 0 x14 : mbps > 1500 ? 0 x04 : 0 x00;1500 ? 0 x03 : 0 x00;for (unsigned int l = 0 ; l < 5 ; l++) {9 ),15 ),/* T7: Wait for stop state */ /* T8: De-assert FRXM */ 0 );return 0 ;static int rcsi2_d_phy_setting_v4m(struct rcar_csi2 *priv, int mbps)unsigned int timeout;int ret;static const struct phtw_value step1[] = {0 x00, .code = 0 x00 },0 x00, .code = 0 x1e },/* Shutdown and reset PHY. */ 0 ));0 ));/* Start internal calibration (POR). */ if (ret)return ret;/* Wait for POR to complete. */ for (timeout = 10 ; timeout > 0 ; timeout--) {if ((rcsi2_read(priv, V4M_PHTR_REG) & 0 xf0000) == 0 x70000)break ;1000 , 2000 );if (!timeout) {"D-PHY calibration failed\n" );return -ETIMEDOUT;return 0 ;static int rcsi2_set_osc_freq(struct rcar_csi2 *priv, unsigned int mbps)const struct rcsi2_mbps_info *info;struct phtw_value steps[] = {0 x00, .code = 0 x00 },0 xe2 }, /* Data filled in below. */ 0 xe3 }, /* Data filled in below. */ 0 x01, .code = 0 xe4 },if (!info)return -ERANGE;/* Fill in data for command. */ 1 ].data = (info->osc_freq & 0 x00ff) >> 0 ;2 ].data = (info->osc_freq & 0 x0f00) >> 8 ;return rcsi2_phtw_write_array(priv, steps, ARRAY_SIZE(steps));static int rcsi2_init_common_v4m(struct rcar_csi2 *priv, unsigned int mbps)int ret;static const struct phtw_value step1[] = {0 x00, .code = 0 x00 },0 x3c, .code = 0 x08 },static const struct phtw_value step2[] = {0 x00, .code = 0 x00 },0 x80, .code = 0 xe0 },0 x31, .code = 0 xe1 },0 x06, .code = 0 x00 },0 x11, .code = 0 x11 },0 x08, .code = 0 x00 },0 x11, .code = 0 x11 },0 x0a, .code = 0 x00 },0 x11, .code = 0 x11 },0 x0c, .code = 0 x00 },0 x11, .code = 0 x11 },0 x01, .code = 0 x00 },0 x31, .code = 0 xaa },0 x05, .code = 0 x00 },0 x05, .code = 0 x09 },0 x07, .code = 0 x00 },0 x05, .code = 0 x09 },0 x09, .code = 0 x00 },0 x05, .code = 0 x09 },0 x0b, .code = 0 x00 },0 x05, .code = 0 x09 },static const struct phtw_value step3[] = {0 x01, .code = 0 x00 },0 x06, .code = 0 xab },if (priv->info->hsfreqrange) {if (ret)return ret;if (ret)return ret;if (mbps <= 1500 ) {if (ret)return ret;if (priv->info->csi0clkfreqrange)if (mbps > 1500 ) {if (ret)return ret;return rcsi2_phtw_write_array(priv, step3, ARRAY_SIZE(step3));static int rcsi2_start_receiver_v4m(struct rcar_csi2 *priv,struct v4l2_subdev_state *state)const struct rcar_csi2_format *format;const struct v4l2_mbus_framefmt *fmt;unsigned int lanes;int mbps;int ret;/* Calculate parameters */ if (!format)return -EINVAL;if (ret)return ret;if (mbps < 0 )return mbps;/* Reset LINK and PHY */ 0 );0 );0 );/* PHY static setting */ 0 );0 );0 );1 );/* Reset CSI2 */ 0 );0 ));/* Common settings */ if (ret)return ret;/* D-PHY settings */ if (ret)return ret;0 );return 0 ;static int rcsi2_start(struct rcar_csi2 *priv, struct v4l2_subdev_state *state)int ret;if (ret < 0 )return ret;if (ret) {return ret;0 ));if (ret) {return ret;return 0 ;static void rcsi2_stop(struct rcar_csi2 *priv)0 ));static int rcsi2_enable_streams(struct v4l2_subdev *sd,struct v4l2_subdev_state *state, u32 source_pad,struct rcar_csi2 *priv = sd_to_csi2(sd);int ret = 0 ;if (source_streams_mask != 1 )return -EINVAL;if (!priv->remote)return -ENODEV;if (priv->stream_count == 0 ) {if (ret)return ret;1 ;return ret;static int rcsi2_disable_streams(struct v4l2_subdev *sd,struct v4l2_subdev_state *state,struct rcar_csi2 *priv = sd_to_csi2(sd);int ret = 0 ;if (source_streams_mask != 1 )return -EINVAL;if (!priv->remote)return -ENODEV;if (priv->stream_count == 1 )1 ;return ret;static int rcsi2_set_pad_format(struct v4l2_subdev *sd,struct v4l2_subdev_state *state,struct v4l2_subdev_format *format)struct rcar_csi2 *priv = sd_to_csi2(sd);unsigned int num_pads = rcsi2_num_pads(priv);if (format->pad > RCAR_CSI2_SINK)return v4l2_subdev_get_fmt(sd, state, format);if (!rcsi2_code_to_fmt(format->format.code))0 ].code;/* Propagate the format to the source pads. */ for (unsigned int i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++)return 0 ;static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = {static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = {static int rcsi2_init_state(struct v4l2_subdev *sd,struct v4l2_subdev_state *state)struct rcar_csi2 *priv = sd_to_csi2(sd);unsigned int num_pads = rcsi2_num_pads(priv);static const struct v4l2_mbus_framefmt rcar_csi2_default_fmt = {1920 ,1080 ,for (unsigned int i = RCAR_CSI2_SINK; i < num_pads; i++)return 0 ;static const struct v4l2_subdev_internal_ops rcar_csi2_internal_ops = {static irqreturn_t rcsi2_irq(int irq, void *data)struct rcar_csi2 *priv = data;if (!status)return IRQ_HANDLED;if (!err_status)return IRQ_HANDLED;"Transfer error, restarting CSI-2 receiver\n" );return IRQ_WAKE_THREAD;static irqreturn_t rcsi2_irq_thread(int irq, void *data)struct v4l2_subdev_state *state;struct rcar_csi2 *priv = data;1000 , 2000 );if (rcsi2_start(priv, state))"Failed to restart CSI-2 receiver\n" );return IRQ_HANDLED;/* ----------------------------------------------------------------------------- * Async handling and registration of subdevices and links. static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier,struct v4l2_subdev *subdev,struct v4l2_async_connection *asc)struct rcar_csi2 *priv = notifier_to_csi2(notifier);int pad;if (pad < 0 ) {"Failed to find pad for %s\n" , subdev->name);return pad;"Bound %s pad: %d\n" , subdev->name, pad);return media_create_pad_link(&subdev->entity, pad,0 ,static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier,struct v4l2_subdev *subdev,struct v4l2_async_connection *asc)struct rcar_csi2 *priv = notifier_to_csi2(notifier);"Unbind %s\n" , subdev->name);static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = {static int rcsi2_parse_v4l2(struct rcar_csi2 *priv,struct v4l2_fwnode_endpoint *vep)unsigned int i;/* Only port 0 endpoint 0 is valid. */ if (vep->base.port || vep->base.id)return -ENOTCONN;switch (vep->bus_type) {case V4L2_MBUS_CSI2_DPHY:if (!priv->info->support_dphy) {"D-PHY not supported\n" );return -EINVAL;if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4 ) {"Unsupported number of data-lanes for D-PHY: %u\n" ,return -EINVAL;false ;break ;case V4L2_MBUS_CSI2_CPHY:if (!priv->info->support_cphy) {"C-PHY not supported\n" );return -EINVAL;if (priv->lanes != 3 ) {"Unsupported number of data-lanes for C-PHY: %u\n" ,return -EINVAL;true ;break ;default :"Unsupported bus: %u\n" , vep->bus_type);return -EINVAL;for (i = 0 ; i < ARRAY_SIZE(priv->lane_swap); i++) {/* Check for valid lane number. */ if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4 ) {"data-lanes must be in 1-4 range\n" );return -EINVAL;for (i = 0 ; i < ARRAY_SIZE(priv->line_orders); i++)return 0 ;static int rcsi2_parse_dt(struct rcar_csi2 *priv)struct v4l2_async_connection *asc;struct fwnode_handle *fwnode;struct fwnode_handle *ep;struct v4l2_fwnode_endpoint v4l2_ep = {int ret;0 , 0 , 0 );if (!ep) {"Not connected to subdevice\n" );return -EINVAL;if (ret) {"Could not parse v4l2 endpoint\n" );return -EINVAL;if (ret) {return ret;"Found '%pOF'\n" , to_of_node(fwnode));struct v4l2_async_connection);if (IS_ERR(asc))return PTR_ERR(asc);if (ret)return ret;/* ----------------------------------------------------------------------------- * PHTW initialization sequences. * * NOTE: Magic values are from the datasheet and lack documentation. static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps,const struct rcsi2_mbps_info *values, u8 code)const struct rcsi2_mbps_info *info;if (!info)return -ERANGE;return rcsi2_phtw_write(priv, info->reg, code);static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv,unsigned int mbps)static const struct phtw_value step1[] = {0 xcc, .code = 0 xe2 },0 x01, .code = 0 xe3 },0 x11, .code = 0 xe4 },0 x01, .code = 0 xe5 },0 x10, .code = 0 x04 },static const struct phtw_value step2[] = {0 x38, .code = 0 x08 },0 x01, .code = 0 x00 },0 x4b, .code = 0 xac },0 x03, .code = 0 x00 },0 x80, .code = 0 x07 },int ret;if (ret)return ret;if (mbps != 0 && mbps <= 250 ) {0 x39, 0 x05);if (ret)return ret;0 xf1);if (ret)return ret;return rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2));static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps)return __rcsi2_init_phtw_h3_v3h_m3n(priv, mbps);static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps)return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0 );static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps)return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0 x44);static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv)static const struct phtw_value step1[] = {0 xee, .code = 0 x34 },0 xee, .code = 0 x44 },0 xee, .code = 0 x54 },0 xee, .code = 0 x84 },0 xee, .code = 0 x94 },return rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1));static int rcsi2_init_phtw_v3u(struct rcar_csi2 *priv,unsigned int mbps)/* In case of 1500Mbps or less */ static const struct phtw_value step1[] = {0 xcc, .code = 0 xe2 },static const struct phtw_value step2[] = {0 x01, .code = 0 xe3 },0 x11, .code = 0 xe4 },0 x01, .code = 0 xe5 },/* In case of 1500Mbps or less */ static const struct phtw_value step3[] = {0 x38, .code = 0 x08 },static const struct phtw_value step4[] = {0 x01, .code = 0 x00 },0 x4b, .code = 0 xac },0 x03, .code = 0 x00 },0 x80, .code = 0 x07 },int ret;if (mbps != 0 && mbps <= 1500 )else 0 xe2);if (ret)return ret;if (ret)return ret;if (mbps != 0 && mbps <= 1500 ) {if (ret)return ret;if (ret)return ret;return ret;/* ----------------------------------------------------------------------------- * Platform Device Driver. static int rcsi2_link_setup(struct media_entity *entity,const struct media_pad *local,const struct media_pad *remote, u32 flags)struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);struct rcar_csi2 *priv = sd_to_csi2(sd);struct video_device *vdev;int channel, vc;if (!is_media_entity_v4l2_video_device(remote->entity)) {"Remote is not a video device\n" );return -EINVAL;if (of_property_read_u32(vdev->dev_parent->of_node, "renesas,id" , &id)) {"No renesas,id, can't configure routing\n" );return -EINVAL;4 ;if (flags & MEDIA_LNK_FL_ENABLED) {if (media_pad_remote_pad_first(local)) {"Each VC can only be routed to one output channel\n" );return -EINVAL;1 ;"Route VC%d to VIN%u on output channel %d\n" ,else {1 ;return 0 ;static const struct media_entity_operations rcar_csi2_entity_ops = {static int rcsi2_probe_resources(struct rcar_csi2 *priv,struct platform_device *pdev)int irq, ret;0 );if (IS_ERR(priv->base))return PTR_ERR(priv->base);0 );if (irq < 0 )return irq;if (ret)return ret;return PTR_ERR_OR_ZERO(priv->rstc);static const struct rcsi2_register_layout rcsi2_registers_gen3 = {static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = {0 x20,4 ,true ,true ,static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = {0 x20,4 ,true ,true ,static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = {4 ,true ,static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = {4 ,true ,static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = {0 x20,4 ,true ,true ,static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = {4 ,true ,static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = {0 x20,true ,true ,static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = {2 ,true ,static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = {0 x20,true ,true ,true ,static const struct rcar_csi2_info rcar_csi2_info_r8a779g0 = {true ,true ,true ,static const struct rcsi2_register_layout rcsi2_registers_v4m = {static const struct rcar_csi2_info rcar_csi2_info_r8a779h0 = {0 x0c,true ,true ,static const struct of_device_id rcar_csi2_of_table[] = {"renesas,r8a774a1-csi2" ,"renesas,r8a774b1-csi2" ,"renesas,r8a774c0-csi2" ,"renesas,r8a774e1-csi2" ,"renesas,r8a7795-csi2" ,"renesas,r8a7796-csi2" ,"renesas,r8a77961-csi2" ,"renesas,r8a77965-csi2" ,"renesas,r8a77970-csi2" ,"renesas,r8a77980-csi2" ,"renesas,r8a77990-csi2" ,"renesas,r8a779a0-csi2" ,"renesas,r8a779g0-csi2" ,"renesas,r8a779h0-csi2" ,/* sentinel */ }, static const struct soc_device_attribute r8a7795[] = {"r8a7795" , .revision = "ES2.*" ,/* sentinel */ } static int rcsi2_probe(struct platform_device *pdev)const struct soc_device_attribute *attr;struct rcar_csi2 *priv;unsigned int i, num_pads;int ret;sizeof (*priv), GFP_KERNEL);if (!priv)return -ENOMEM;/* * The different ES versions of r8a7795 (H3) behave differently but * share the same compatible string. if (attr)0 ;if (ret) {"Failed to get resources\n" );return ret;if (ret)return ret;sizeof (priv->subdev.name), "%s %s" ,for (i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++)if (ret)goto error_async;for (i = 0 ; i < ARRAY_SIZE(priv->channel_vc); i++)1 ;if (ret)goto error_pm_runtime;if (ret < 0 )goto error_subdev;"%d lanes found\n" , priv->lanes);return 0 ;return ret;static void rcsi2_remove(struct platform_device *pdev)struct rcar_csi2 *priv = platform_get_drvdata(pdev);static struct platform_driver rcar_csi2_pdrv = {"rcar-csi2" ,true ,"Niklas Söderlund <niklas.soderlund@ragnatech.se>" );"Renesas R-Car MIPI CSI-2 receiver driver" );"GPL" );
Messung V0.5 in Prozent C=94 H=92 G=92
¤ Dauer der Verarbeitung: 0.36 Sekunden
(vorverarbeitet am 2026-06-08)
¤ *© Formatika GbR, Deutschland
