// SPDX-License-Identifier: GPL-2.0 /* * Driver for Renesas R-Car MIPI CSI-2 Receiver * * Copyright (C) 2018 Renesas Electronics Corp. #include <linux/delay.h>#include <linux/interrupt.h>#include <linux/io.h>#include <linux/math64.h>#include <linux/module.h>#include <linux/of.h>#include <linux/of_graph.h>#include <linux/platform_device.h>#include <linux/pm_runtime.h>#include <linux/reset.h>#include <linux/sys_soc.h>#include <linux/units.h>#include <media/mipi-csi2.h>#include <media/v4l2-ctrls.h>#include <media/v4l2-device.h>#include <media/v4l2-fwnode.h>#include <media/v4l2-mc.h>#include <media/v4l2-subdev.h>struct rcar_csi2;/* Register offsets and bits */ /* Control Timing Select */ #define TREF_REG 0x00#define TREF_TREF BIT(0)/* Software Reset */ #define SRST_REG 0x04#define SRST_SRST BIT(0)/* PHY Operation Control */ #define PHYCNT_REG 0x08#define PHYCNT_SHUTDOWNZ BIT(17)#define PHYCNT_RSTZ BIT(16)#define PHYCNT_ENABLECLK BIT(4)#define PHYCNT_ENABLE_3 BIT(3)#define PHYCNT_ENABLE_2 BIT(2)#define PHYCNT_ENABLE_1 BIT(1)#define PHYCNT_ENABLE_0 BIT(0)/* Checksum Control */ #define CHKSUM_REG 0x0c#define CHKSUM_ECC_EN BIT(1)#define CHKSUM_CRC_EN BIT(0)/* * Channel Data Type Select * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3 #define VCDT_REG 0x10#define VCDT2_REG 0x14#define VCDT_VCDTN_EN BIT(15)#define VCDT_SEL_VC(n) (((n) & 0x3) << 8)#define VCDT_SEL_DTN_ON BIT(6)#define VCDT_SEL_DT(n) (((n) & 0x3f) << 0)/* Frame Data Type Select */ #define FRDT_REG 0x18/* Field Detection Control */ #define FLD_REG 0x1c#define FLD_FLD_NUM(n) (((n) & 0xff) << 16)#define FLD_DET_SEL(n) (((n) & 0x3) << 4)#define FLD_FLD_EN4 BIT(3)#define FLD_FLD_EN3 BIT(2)#define FLD_FLD_EN2 BIT(1)#define FLD_FLD_EN BIT(0)/* Automatic Standby Control */ #define ASTBY_REG 0x20/* Long Data Type Setting 0 */ #define LNGDT0_REG 0x28/* Long Data Type Setting 1 */ #define LNGDT1_REG 0x2c/* Interrupt Enable */ #define INTEN_REG 0x30#define INTEN_INT_AFIFO_OF BIT(27)#define INTEN_INT_ERRSOTHS BIT(4)#define INTEN_INT_ERRSOTSYNCHS BIT(3)/* Interrupt Source Mask */ #define INTCLOSE_REG 0x34/* Interrupt Status Monitor */ #define INTSTATE_REG 0x38#define INTSTATE_INT_ULPS_START BIT(7)#define INTSTATE_INT_ULPS_END BIT(6)/* Interrupt Error Status Monitor */ #define INTERRSTATE_REG 0x3c/* Short Packet Data */ #define SHPDAT_REG 0x40/* Short Packet Count */ #define SHPCNT_REG 0x44/* LINK Operation Control */ #define LINKCNT_REG 0x48#define LINKCNT_MONITOR_EN BIT(31)#define LINKCNT_REG_MONI_PACT_EN BIT(25)#define LINKCNT_ICLK_NONSTOP BIT(24)/* Lane Swap */ #define LSWAP_REG 0x4c#define LSWAP_L3SEL(n) (((n) & 0x3) << 6)#define LSWAP_L2SEL(n) (((n) & 0x3) << 4)#define LSWAP_L1SEL(n) (((n) & 0x3) << 2)#define LSWAP_L0SEL(n) (((n) & 0x3) << 0)/* PHY Test Interface Write Register */ #define PHTW_REG 0x50#define PHTW_DWEN BIT(24)#define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16)#define PHTW_CWEN BIT(8)#define PHTW_TESTDIN_CODE(n) ((n & 0xff))#define PHYFRX_REG 0x64#define PHYFRX_FORCERX_MODE_3 BIT(3)#define PHYFRX_FORCERX_MODE_2 BIT(2)#define PHYFRX_FORCERX_MODE_1 BIT(1)#define PHYFRX_FORCERX_MODE_0 BIT(0)/* V4H BASE registers */ #define V4H_N_LANES_REG 0x0004#define V4H_CSI2_RESETN_REG 0x0008#define V4H_PHY_MODE_REG 0x001c#define V4H_PHY_MODE_DPHY 0#define V4H_PHY_MODE_CPHY 1#define V4H_PHY_SHUTDOWNZ_REG 0x0040#define V4H_DPHY_RSTZ_REG 0x0044#define V4H_FLDC_REG 0x0804#define V4H_FLDD_REG 0x0808#define V4H_IDIC_REG 0x0810#define V4H_PHY_EN_REG 0x2000#define V4H_PHY_EN_ENABLE_3 BIT(7)#define V4H_PHY_EN_ENABLE_2 BIT(6)#define V4H_PHY_EN_ENABLE_1 BIT(5)#define V4H_PHY_EN_ENABLE_0 BIT(4)#define V4H_PHY_EN_ENABLE_CLK BIT(0)#define V4H_ST_PHYST_REG 0x2814#define V4H_ST_PHYST_ST_PHY_READY BIT(31)#define V4H_ST_PHYST_ST_STOPSTATE_3 BIT(3)#define V4H_ST_PHYST_ST_STOPSTATE_2 BIT(2)#define V4H_ST_PHYST_ST_STOPSTATE_1 BIT(1)#define V4H_ST_PHYST_ST_STOPSTATE_0 BIT(0)/* V4H PPI registers */ #define V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(n) (0x21800 + ((n) * 2)) /* n = 0 - 9 */ #define V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG 0x21822#define V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG 0x2184c#define V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG 0x21c02#define V4H_PPI_RW_LPDCOCAL_NREF_REG 0x21c04#define V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG 0x21c06#define V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG 0x21c0a#define V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG 0x21c0c#define V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG 0x21c10#define V4H_PPI_RW_DDLCAL_CFG_n_REG(n) (0x21c40 + ((n) * 2)) /* n = 0 - 7 */ #define V4H_PPI_RW_COMMON_CFG_REG 0x21c6c#define V4H_PPI_RW_TERMCAL_CFG_0_REG 0x21c80#define V4H_PPI_RW_OFFSETCAL_CFG_0_REG 0x21ca0/* V4H CORE registers */ #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_2_REG(l, n) (0x22040 + ((l) * 0x400) + ((n) * 2))#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_3_REG(l, n) (0x22060 + ((l) * 0x400) + ((n) * 2))#define V4H_CORE_DIG_IOCTRL_RW_AFE_LANEl_CTRL_4_REG(l, n) (0x22080 + ((l) * 0x400) + ((n) * 2))#define V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(n) (0x23840 + ((n) * 2)) /* n = 0 - 11 */ #define V4H_CORE_DIG_RW_COMMON_REG(n) (0x23880 + ((n) * 2)) /* n = 0 - 15 */ #define V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(n) (0x239e0 + ((n) * 2)) /* n = 0 - 3 */ #define V4H_CORE_DIG_COMMON_RW_DESKEW_FINE_MEM_REG 0x23fe0#define V4H_CORE_DIG_DLANE_l_RW_CFG_n_REG(l, n) (0x26000 + ((l) * 0x400) + ((n) * 2))#define V4H_CORE_DIG_DLANE_l_RW_LP_n_REG(l, n) (0x26080 + ((l) * 0x400) + ((n) * 2))#define V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(l, n) (0x26100 + ((l) * 0x400) + ((n) * 2))#define V4H_CORE_DIG_DLANE_CLK_RW_LP_n_REG(n) V4H_CORE_DIG_DLANE_l_RW_LP_n_REG(4, (n))#define V4H_CORE_DIG_DLANE_CLK_RW_HS_RX_n_REG(n) V4H_CORE_DIG_DLANE_l_RW_HS_RX_n_REG(4, (n))/* V4H C-PHY */ #define V4H_CORE_DIG_RW_TRIO0_REG(n) (0x22100 + ((n) * 2)) /* n = 0 - 3 */ #define V4H_CORE_DIG_RW_TRIO1_REG(n) (0x22500 + ((n) * 2)) /* n = 0 - 3 */ #define V4H_CORE_DIG_RW_TRIO2_REG(n) (0x22900 + ((n) * 2)) /* n = 0 - 3 */ #define V4H_CORE_DIG_CLANE_0_RW_CFG_0_REG 0x2a000#define V4H_CORE_DIG_CLANE_0_RW_LP_0_REG 0x2a080#define V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(n) (0x2a100 + ((n) * 2)) /* n = 0 - 6 */ #define V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG 0x2a400#define V4H_CORE_DIG_CLANE_1_RW_LP_0_REG 0x2a480#define V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(n) (0x2a500 + ((n) * 2)) /* n = 0 - 6 */ #define V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG 0x2a60c#define V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG 0x2a800#define V4H_CORE_DIG_CLANE_2_RW_LP_0_REG 0x2a880#define V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(n) (0x2a900 + ((n) * 2)) /* n = 0 - 6 */ struct rcsi2_cphy_setting {static const struct rcsi2_cphy_setting cphy_setting_table_r8a779g0[] = {29 = 0x0a24 },e29 = 0x0a24 },e29 = 0x0a44 },e29 = 0x0a44 },e29 = 0x0a64 },e29 = 0x0a64 },e29 = 0x0a64 },e29 = 0x0a84 },e29 = 0x0a84 },e29 = 0x0a84 },ne29 = 0x0a84 },ne29 = 0x0a84 },ne29 = 0x0a84 },ne29 = 0x0aa4 },ne29 = 0x0aa4 },ne29 = 0x0aa4 },ne29 = 0x0aa4 },ne29 = 0x0aa4 },ne29 = 0x0aa4 },ne29 = 0x0aa4 },ne29 = 0x0aa4 },ne29 = 0x0aa4 },ne29 = 0x0aa4 },ne29 = 0x0aa4 },ne29 = 0x0aa4 },ne29 = 0x0aa4 },ne29 = 0x0ad4 },ne29 = 0x0ad4 },ne29 = 0x0ad4 },ne29 = 0x0ad4 },ne29 = 0x0ad4 },ne29 = 0x0ad4 },ne29 = 0x0ad4 },ne29 = 0x0ad4 },ne29 = 0x0ad4 },ne29 = 0x0ad4 },/* sentinel */ }, /* V4M registers */ #define V4M_OVR1_REG 0x0848#define V4M_OVR1_FORCERXMODE_3 BIT(12)#define V4M_OVR1_FORCERXMODE_2 BIT(11)#define V4M_OVR1_FORCERXMODE_1 BIT(10)#define V4M_OVR1_FORCERXMODE_0 BIT(9)#define V4M_FRXM_REG 0x2004#define V4M_FRXM_FORCERXMODE_3 BIT(3)#define V4M_FRXM_FORCERXMODE_2 BIT(2)#define V4M_FRXM_FORCERXMODE_1 BIT(1)#define V4M_FRXM_FORCERXMODE_0 BIT(0)#define V4M_PHYPLL_REG 0x02050#define V4M_CSI0CLKFCPR_REG 0x02054#define V4M_PHTW_REG 0x02060#define V4M_PHTR_REG 0x02064#define V4M_PHTC_REG 0x02068struct phtw_value {struct rcsi2_mbps_info {/* V4M */ static const struct rcsi2_mbps_info phtw_mbps_v3u[] = {/* sentinel */ }, static const struct rcsi2_mbps_info phtw_mbps_h3_v3h_m3n[] = {/* sentinel */ }, static const struct rcsi2_mbps_info phtw_mbps_v3m_e3[] = {/* sentinel */ }, /* PHY Test Interface Clear */ #define PHTC_REG 0x58#define PHTC_TESTCLR BIT(0)/* PHY Frequency Control */ #define PHYPLL_REG 0x68#define PHYPLL_HSFREQRANGE(n) ((n) << 16)static const struct rcsi2_mbps_info hsfreqrange_v3u[] = {/* sentinel */ }, static const struct rcsi2_mbps_info hsfreqrange_h3_v3h_m3n[] = {/* sentinel */ }, static const struct rcsi2_mbps_info hsfreqrange_m3w[] = {/* sentinel */ }, static const struct rcsi2_mbps_info hsfreqrange_v4m[] = {/* sentinel */ }, /* PHY ESC Error Monitor */ #define PHEERM_REG 0x74/* PHY Clock Lane Monitor */ #define PHCLM_REG 0x78#define PHCLM_STOPSTATECKL BIT(0)/* PHY Data Lane Monitor */ #define PHDLM_REG 0x7c/* CSI0CLK Frequency Configuration Preset Register */ #define CSI0CLKFCPR_REG 0x260#define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16)struct rcar_csi2_format {unsigned int datatype;unsigned int bpp;static const struct rcar_csi2_format rcar_csi2_formats[] = {static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code)unsigned int i;for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++)if (rcar_csi2_formats[i].code == code)return &rcar_csi2_formats[i];return NULL;struct rcsi2_cphy_line_order {enum v4l2_mbus_csi2_cphy_line_orders_type order;static const struct rcsi2_cphy_line_order rcsi2_cphy_line_orders[] = {enum rcar_csi2_pads {struct rcsi2_register_layout {unsigned int phtw;unsigned int phypll;struct rcar_csi2_info {const struct rcsi2_register_layout *regs;int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps);int (*phy_post_init)(struct rcar_csi2 *priv);int (*start_receiver)(struct rcar_csi2 *priv,struct v4l2_subdev_state *state);void (*enter_standby)(struct rcar_csi2 *priv);const struct rcsi2_mbps_info *hsfreqrange;unsigned int csi0clkfreqrange;unsigned int num_channels;bool clear_ulps;bool use_isp;bool support_dphy;bool support_cphy;struct rcar_csi2 {struct device *dev;void __iomem *base;const struct rcar_csi2_info *info;struct reset_control *rstc;struct v4l2_subdev subdev;struct media_pad pads[NR_OF_RCAR_CSI2_PAD];struct v4l2_async_notifier notifier;struct v4l2_subdev *remote;unsigned int remote_pad;int channel_vc[4];int stream_count;bool cphy;unsigned short lanes;unsigned char lane_swap[4];enum v4l2_mbus_csi2_cphy_line_orders_type line_orders[3];static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd)return container_of(sd, struct rcar_csi2, subdev);static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)return container_of(n, struct rcar_csi2, notifier);static unsigned int rcsi2_num_pads(const struct rcar_csi2 *priv)/* Used together with R-Car ISP: one sink and one source pad. */ if (priv->info->use_isp)return 2;/* Used together with R-Car VIN: one sink and four source pads. */ return 5;static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg)return ioread32(priv->base + reg);static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data)static u16 rcsi2_read16(struct rcar_csi2 *priv, unsigned int reg)return ioread16(priv->base + reg);static void rcsi2_write16(struct rcar_csi2 *priv, unsigned int reg, u16 data)static void rcsi2_modify16(struct rcar_csi2 *priv, unsigned int reg, u16 data, u16 mask)static int rcsi2_phtw_write(struct rcar_csi2 *priv, u8 data, u8 code)unsigned int timeout;/* Wait for DWEN and CWEN to be cleared by hardware. */ for (timeout = 0; timeout <= 20; timeout++) {if (!(rcsi2_read(priv, priv->info->regs->phtw) & (PHTW_DWEN | PHTW_CWEN)))return 0;"Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n" );return -ETIMEDOUT;static int rcsi2_phtw_write_array(struct rcar_csi2 *priv,const struct phtw_value *values,unsigned int size)int ret;for (unsigned int i = 0; i < size; i++) {if (ret)return ret;return 0;static const struct rcsi2_mbps_info *struct rcar_csi2 *priv,const struct rcsi2_mbps_info *infotable, unsigned int mbps)const struct rcsi2_mbps_info *info;const struct rcsi2_mbps_info *prev = NULL;if (mbps < infotable->mbps)"%u Mbps less than min PHY speed %u Mbps" ,for (info = infotable; info->mbps != 0; info++) {if (info->mbps >= mbps)break ;if (!info->mbps) {"Unsupported PHY speed (%u Mbps)" , mbps);return NULL;if (prev && ((mbps - prev->mbps) <= (info->mbps - mbps)))return info;static void rcsi2_enter_standby_gen3(struct rcar_csi2 *priv)static void rcsi2_enter_standby(struct rcar_csi2 *priv)if (priv->info->enter_standby)static int rcsi2_exit_standby(struct rcar_csi2 *priv)int ret;if (ret < 0)return ret;return 0;static int rcsi2_wait_phy_start(struct rcar_csi2 *priv,unsigned int lanes)unsigned int timeout;/* Wait for the clock and data lanes to enter LP-11 state. */ for (timeout = 0; timeout <= 20; timeout++) {const u32 lane_mask = (1 << lanes) - 1;if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) &&return 0;"Timeout waiting for LP-11 state\n" );return -ETIMEDOUT;static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps)const struct rcsi2_mbps_info *info;if (!info)return -ERANGE;return 0;static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp,unsigned int lanes)struct media_pad *remote_pad;struct v4l2_subdev *source;if (!priv->remote)return -ENODEV;if (freq < 0) {int ret = (int )freq;"failed to get link freq for %s: %d\n" ,return ret;return mbps;static int rcsi2_get_active_lanes(struct rcar_csi2 *priv,unsigned int *lanes)struct v4l2_mbus_config mbus_config = { 0 };int ret;if (ret == -ENOIOCTLCMD) {"No remote mbus configuration available\n" );return 0;if (ret) {"Failed to get remote mbus configuration\n" );return ret;switch (mbus_config.type) {case V4L2_MBUS_CSI2_CPHY:if (!priv->cphy)return -EINVAL;break ;case V4L2_MBUS_CSI2_DPHY:if (priv->cphy)return -EINVAL;break ;default :"Unsupported media bus type %u\n" ,return -EINVAL;if (mbus_config.bus.mipi_csi2.num_data_lanes > priv->lanes) {"Unsupported mbus config: too many data lanes %u\n" ,return -EINVAL;return 0;static int rcsi2_start_receiver_gen3(struct rcar_csi2 *priv,struct v4l2_subdev_state *state)const struct rcar_csi2_format *format;const struct v4l2_mbus_framefmt *fmt;unsigned int lanes;unsigned int i;int mbps, ret;/* Use the format on the sink pad to compute the receiver config. */ "Input size (%ux%u%c)\n" ,'p' : 'i' );/* Code is validated in set_fmt. */ if (!format)return -EINVAL;/* * Enable all supported CSI-2 channels with virtual channel and * data type matching. * * NOTE: It's not possible to get individual datatype for each * source virtual channel. Once this is possible in V4L2 * it should be used here. for (i = 0; i < priv->info->num_channels; i++) {if (priv->channel_vc[i] < 0)continue ;/* Store in correct reg and offset. */ if (i < 2)else if (fmt->field == V4L2_FIELD_ALTERNATE)/* * Get the number of active data lanes inspecting the remote mbus * configuration. if (ret)return ret;if (mbps < 0)return mbps;/* Enable interrupts. */ /* Init */ /* Configure */ if (!priv->info->use_isp) {if (vcdt2)/* Lanes are zero indexed. */ /* Start */ if (priv->info->init_phtw) {if (ret)return ret;if (priv->info->hsfreqrange) {if (ret)return ret;if (priv->info->csi0clkfreqrange)if (priv->info->use_isp)if (ret)return ret;if (priv->info->use_isp)/* Run post PHY start initialization, if needed. */ if (priv->info->phy_post_init) {if (ret)return ret;/* Clear Ultra Low Power interrupt. */ if (priv->info->clear_ulps)return 0;static void rsci2_set_line_order(struct rcar_csi2 *priv,enum v4l2_mbus_csi2_cphy_line_orders_type order,unsigned int cfgreg, unsigned int ctrlreg)const struct rcsi2_cphy_line_order *info = NULL;for (unsigned int i = 0; i < ARRAY_SIZE(rcsi2_cphy_line_orders); i++) {if (rcsi2_cphy_line_orders[i].order == order) {break ;if (!info)return ;static int rcsi2_wait_phy_start_v4h(struct rcar_csi2 *priv, u32 match)unsigned int timeout;for (timeout = 0; timeout <= 10; timeout++) {if ((status & match) == match)return 0;return -ETIMEDOUT;static const struct rcsi2_cphy_setting *struct rcar_csi2 *priv, int mbps)const struct rcsi2_cphy_setting *conf;int msps;/* Adjust for C-PHY symbols, divide by 2.8. */ for (conf = cphy_setting_table_r8a779g0; conf->msps != 0; conf++) {if (conf->msps > msps)break ;if (!conf->msps) {"Unsupported PHY speed for msps setting (%u Msps)" , msps);return NULL;/* C-PHY specific */ /* Configure data line order. */ /* TODO: This registers is not documented. */ return conf;struct rcsi2_d_phy_setting_v4h_lut_value {unsigned int mbps;unsigned char cfg_1;unsigned char cfg_5_94;unsigned char cfg_5_30;unsigned char lane_ctrl_2_8;unsigned char rw_hs_rx_3_83;unsigned char rw_hs_rx_3_20;unsigned char rw_hs_rx_6;unsigned char rw_hs_rx_1;static const struct rcsi2_d_phy_setting_v4h_lut_value *int mbps)static const struct rcsi2_d_phy_setting_v4h_lut_value values[] = {for (unsigned int i = 0; i < ARRAY_SIZE(values); i++)if (mbps >= values[i].mbps)return &values[i];return NULL;static int rcsi2_d_phy_setting_v4h(struct rcar_csi2 *priv, int mbps)const struct rcsi2_d_phy_setting_v4h_lut_value *lut =;if (mbps > 1500) {if (lut) {for (unsigned int l = 0; l < 5; l++)for (unsigned int l = 0; l < 4; l++)for (unsigned int l = 0; l < 5; l++)for (unsigned int l = 0; l < 5; l++)if (mbps >= 80) {/* 2560: 6, 1280: 5, 640: 4, 320: 3, 160: 2, 80: 1 */ for (unsigned int l = 0; l < 4; l++)for (unsigned int l = 0; l < 4; l++)for (unsigned int l = 0; l < 4; l++)for (unsigned int l = 0; l < 4; l++)if (lut) {for (unsigned int l = 0; l < 4; l++)for (unsigned int l = 0; l < 4; l++)for (unsigned int l = 0; l < 4; l++)for (unsigned int l = 0; l < 4; l++)for (unsigned int l = 0; l < 4; l++)for (unsigned int l = 0; l < 4; l++)if (lut) {/* * Documentation LUT have two values but document writing both * values in a single write. for (unsigned int l = 0; l < 4; l++)for (unsigned int l = 0; l < 4; l++)static const u16 deskew_fine[] = {for (unsigned int i = 0; i < ARRAY_SIZE(deskew_fine); i++) {return 0;static int rcsi2_start_receiver_v4h(struct rcar_csi2 *priv,struct v4l2_subdev_state *state)const struct rcsi2_cphy_setting *cphy = NULL;const struct rcar_csi2_format *format;const struct v4l2_mbus_framefmt *fmt;unsigned int lanes;int mbps;int ret;/* Use the format on the sink pad to compute the receiver config. */ if (!format)return -EINVAL;if (ret)return ret;if (mbps < 0)return mbps;/* T0: Reset LINK and PHY*/ /* T1: PHY static setting */ /* T2: Reset CSI2 */ /* Registers static setting through APB */ /* Common setting */ /* T3: PHY settings */ if (priv->cphy) {if (!cphy)return -ERANGE;else {if (ret)return ret;/* T4: Leave Shutdown mode */ /* T5: Wait for calibration */ if (rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_PHY_READY)) {"PHY calibration failed\n" );return -ETIMEDOUT;/* T6: Analog programming */ if (priv->cphy) {for (unsigned int l = 0; l < 3; l++) {else {for (unsigned int l = 0; l < 5; l++) {/* T7: Wait for stop state */ /* T8: De-assert FRXM */ return 0;static int rcsi2_d_phy_setting_v4m(struct rcar_csi2 *priv, int mbps)unsigned int timeout;int ret;static const struct phtw_value step1[] = {/* Shutdown and reset PHY. */ /* Start internal calibration (POR). */ if (ret)return ret;/* Wait for POR to complete. */ for (timeout = 10; timeout > 0; timeout--) {if ((rcsi2_read(priv, V4M_PHTR_REG) & 0xf0000) == 0x70000)break ;if (!timeout) {"D-PHY calibration failed\n" );return -ETIMEDOUT;return 0;static int rcsi2_set_osc_freq(struct rcar_csi2 *priv, unsigned int mbps)const struct rcsi2_mbps_info *info;struct phtw_value steps[] = {/* Data filled in below. */ /* Data filled in below. */ if (!info)return -ERANGE;/* Fill in data for command. */ return rcsi2_phtw_write_array(priv, steps, ARRAY_SIZE(steps));static int rcsi2_init_common_v4m(struct rcar_csi2 *priv, unsigned int mbps)int ret;static const struct phtw_value step1[] = {static const struct phtw_value step2[] = {static const struct phtw_value step3[] = {if (priv->info->hsfreqrange) {if (ret)return ret;if (ret)return ret;if (mbps <= 1500) {if (ret)return ret;if (priv->info->csi0clkfreqrange)if (mbps > 1500) {if (ret)return ret;return rcsi2_phtw_write_array(priv, step3, ARRAY_SIZE(step3));static int rcsi2_start_receiver_v4m(struct rcar_csi2 *priv,struct v4l2_subdev_state *state)const struct rcar_csi2_format *format;const struct v4l2_mbus_framefmt *fmt;unsigned int lanes;int mbps;int ret;/* Calculate parameters */ if (!format)return -EINVAL;if (ret)return ret;if (mbps < 0)return mbps;/* Reset LINK and PHY */ /* PHY static setting */ /* Reset CSI2 */ /* Common settings */ if (ret)return ret;/* D-PHY settings */ if (ret)return ret;return 0;static int rcsi2_start(struct rcar_csi2 *priv, struct v4l2_subdev_state *state)int ret;if (ret < 0)return ret;if (ret) {return ret;if (ret) {return ret;return 0;static void rcsi2_stop(struct rcar_csi2 *priv)static int rcsi2_enable_streams(struct v4l2_subdev *sd,struct v4l2_subdev_state *state, u32 source_pad,struct rcar_csi2 *priv = sd_to_csi2(sd);int ret = 0;if (source_streams_mask != 1)return -EINVAL;if (!priv->remote)return -ENODEV;if (priv->stream_count == 0) {if (ret)return ret;return ret;static int rcsi2_disable_streams(struct v4l2_subdev *sd,struct v4l2_subdev_state *state,struct rcar_csi2 *priv = sd_to_csi2(sd);int ret = 0;if (source_streams_mask != 1)return -EINVAL;if (!priv->remote)return -ENODEV;if (priv->stream_count == 1)return ret;static int rcsi2_set_pad_format(struct v4l2_subdev *sd,struct v4l2_subdev_state *state,struct v4l2_subdev_format *format)struct rcar_csi2 *priv = sd_to_csi2(sd);unsigned int num_pads = rcsi2_num_pads(priv);if (format->pad > RCAR_CSI2_SINK)return v4l2_subdev_get_fmt(sd, state, format);if (!rcsi2_code_to_fmt(format->format.code))/* Propagate the format to the source pads. */ for (unsigned int i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++)return 0;static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = {static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = {static int rcsi2_init_state(struct v4l2_subdev *sd,struct v4l2_subdev_state *state)struct rcar_csi2 *priv = sd_to_csi2(sd);unsigned int num_pads = rcsi2_num_pads(priv);static const struct v4l2_mbus_framefmt rcar_csi2_default_fmt = {for (unsigned int i = RCAR_CSI2_SINK; i < num_pads; i++)return 0;static const struct v4l2_subdev_internal_ops rcar_csi2_internal_ops = {static irqreturn_t rcsi2_irq(int irq, void *data)struct rcar_csi2 *priv = data;if (!status)return IRQ_HANDLED;if (!err_status)return IRQ_HANDLED;"Transfer error, restarting CSI-2 receiver\n" );return IRQ_WAKE_THREAD;static irqreturn_t rcsi2_irq_thread(int irq, void *data)struct v4l2_subdev_state *state;struct rcar_csi2 *priv = data;if (rcsi2_start(priv, state))"Failed to restart CSI-2 receiver\n" );return IRQ_HANDLED;/* ----------------------------------------------------------------------------- * Async handling and registration of subdevices and links. static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier,struct v4l2_subdev *subdev,struct v4l2_async_connection *asc)struct rcar_csi2 *priv = notifier_to_csi2(notifier);int pad;if (pad < 0) {"Failed to find pad for %s\n" , subdev->name);return pad;"Bound %s pad: %d\n" , subdev->name, pad);return media_create_pad_link(&subdev->entity, pad,static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier,struct v4l2_subdev *subdev,struct v4l2_async_connection *asc)struct rcar_csi2 *priv = notifier_to_csi2(notifier);"Unbind %s\n" , subdev->name);static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = {static int rcsi2_parse_v4l2(struct rcar_csi2 *priv,struct v4l2_fwnode_endpoint *vep)unsigned int i;/* Only port 0 endpoint 0 is valid. */ if (vep->base.port || vep->base.id)return -ENOTCONN;switch (vep->bus_type) {case V4L2_MBUS_CSI2_DPHY:if (!priv->info->support_dphy) {"D-PHY not supported\n" );return -EINVAL;if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) {"Unsupported number of data-lanes for D-PHY: %u\n" ,return -EINVAL;false ;break ;case V4L2_MBUS_CSI2_CPHY:if (!priv->info->support_cphy) {"C-PHY not supported\n" );return -EINVAL;if (priv->lanes != 3) {"Unsupported number of data-lanes for C-PHY: %u\n" ,return -EINVAL;true ;break ;default :"Unsupported bus: %u\n" , vep->bus_type);return -EINVAL;for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) {/* Check for valid lane number. */ if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) {"data-lanes must be in 1-4 range\n" );return -EINVAL;for (i = 0; i < ARRAY_SIZE(priv->line_orders); i++)return 0;static int rcsi2_parse_dt(struct rcar_csi2 *priv)struct v4l2_async_connection *asc;struct fwnode_handle *fwnode;struct fwnode_handle *ep;struct v4l2_fwnode_endpoint v4l2_ep = {int ret;if (!ep) {"Not connected to subdevice\n" );return -EINVAL;if (ret) {"Could not parse v4l2 endpoint\n" );return -EINVAL;if (ret) {return ret;
Messung V0.5 C=96 H=91 G=93
¤ Dauer der Verarbeitung: 0.18 Sekunden
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¤ *© Formatika GbR, Deutschland
