// SPDX-License-Identifier: GPL-2.0 /* * Intel MAX 10 BMC HWMON Driver * * Copyright (C) 2018-2020 Intel Corporation. All rights reserved. * #include <linux/device.h>#include <linux/hwmon.h>#include <linux/mfd/intel-m10-bmc.h>#include <linux/module.h>#include <linux/mod_devicetable.h>#include <linux/platform_device.h>struct m10bmc_sdata {unsigned int reg_input;unsigned int reg_max;unsigned int reg_crit;unsigned int reg_hyst;unsigned int reg_min;unsigned int multiplier;const char *label;struct m10bmc_hwmon_board_data {const struct m10bmc_sdata *tables[hwmon_max];const struct hwmon_channel_info * const *hinfo;struct m10bmc_hwmon {struct device *dev;struct hwmon_chip_info chip;char *hw_name;struct intel_m10bmc *m10bmc;const struct m10bmc_hwmon_board_data *bdata;static const struct m10bmc_sdata n3000bmc_temp_tbl[] = {0 x100, 0 x104, 0 x108, 0 x10c, 0 x0, 500 , "Board Temperature" },0 x110, 0 x114, 0 x118, 0 x0, 0 x0, 500 , "FPGA Die Temperature" },0 x11c, 0 x124, 0 x120, 0 x0, 0 x0, 500 , "QSFP0 Temperature" },0 x12c, 0 x134, 0 x130, 0 x0, 0 x0, 500 , "QSFP1 Temperature" },0 x168, 0 x0, 0 x0, 0 x0, 0 x0, 500 , "Retimer A Temperature" },0 x16c, 0 x0, 0 x0, 0 x0, 0 x0, 500 , "Retimer A SerDes Temperature" },0 x170, 0 x0, 0 x0, 0 x0, 0 x0, 500 , "Retimer B Temperature" },0 x174, 0 x0, 0 x0, 0 x0, 0 x0, 500 , "Retimer B SerDes Temperature" },static const struct m10bmc_sdata n3000bmc_in_tbl[] = {0 x128, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "QSFP0 Supply Voltage" },0 x138, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "QSFP1 Supply Voltage" },0 x13c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA Core Voltage" },0 x144, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "12V Backplane Voltage" },0 x14c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "1.2V Voltage" },0 x150, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "12V AUX Voltage" },0 x158, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "1.8V Voltage" },0 x15c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "3.3V Voltage" },static const struct m10bmc_sdata n3000bmc_curr_tbl[] = {0 x140, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA Core Current" },0 x148, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "12V Backplane Current" },0 x154, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "12V AUX Current" },static const struct m10bmc_sdata n3000bmc_power_tbl[] = {0 x160, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "Board Power" },static const struct hwmon_channel_info * const n3000bmc_hinfo[] = {static const struct m10bmc_sdata d5005bmc_temp_tbl[] = {0 x100, 0 x104, 0 x108, 0 x10c, 0 x0, 500 , "Board Inlet Air Temperature" },0 x110, 0 x114, 0 x118, 0 x0, 0 x0, 500 , "FPGA Core Temperature" },0 x11c, 0 x120, 0 x124, 0 x128, 0 x0, 500 , "Board Exhaust Air Temperature" },0 x12c, 0 x130, 0 x134, 0 x0, 0 x0, 500 , "FPGA Transceiver Temperature" },0 x138, 0 x13c, 0 x140, 0 x144, 0 x0, 500 , "RDIMM0 Temperature" },0 x148, 0 x14c, 0 x150, 0 x154, 0 x0, 500 , "RDIMM1 Temperature" },0 x158, 0 x15c, 0 x160, 0 x164, 0 x0, 500 , "RDIMM2 Temperature" },0 x168, 0 x16c, 0 x170, 0 x174, 0 x0, 500 , "RDIMM3 Temperature" },0 x178, 0 x17c, 0 x180, 0 x0, 0 x0, 500 , "QSFP0 Temperature" },0 x188, 0 x18c, 0 x190, 0 x0, 0 x0, 500 , "QSFP1 Temperature" },0 x1a0, 0 x1a4, 0 x1a8, 0 x0, 0 x0, 500 , "3.3v Temperature" },0 x1bc, 0 x1c0, 0 x1c4, 0 x0, 0 x0, 500 , "VCCERAM Temperature" },0 x1d8, 0 x1dc, 0 x1e0, 0 x0, 0 x0, 500 , "VCCR Temperature" },0 x1f4, 0 x1f8, 0 x1fc, 0 x0, 0 x0, 500 , "VCCT Temperature" },0 x210, 0 x214, 0 x218, 0 x0, 0 x0, 500 , "1.8v Temperature" },0 x22c, 0 x230, 0 x234, 0 x0, 0 x0, 500 , "12v Backplane Temperature" },0 x248, 0 x24c, 0 x250, 0 x0, 0 x0, 500 , "12v AUX Temperature" },static const struct m10bmc_sdata d5005bmc_in_tbl[] = {0 x184, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "QSFP0 Supply Voltage" },0 x194, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "QSFP1 Supply Voltage" },0 x198, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA Core Voltage" },0 x1ac, 0 x1b0, 0 x1b4, 0 x0, 0 x0, 1 , "3.3v Voltage" },0 x1c8, 0 x1cc, 0 x1d0, 0 x0, 0 x0, 1 , "VCCERAM Voltage" },0 x1e4, 0 x1e8, 0 x1ec, 0 x0, 0 x0, 1 , "VCCR Voltage" },0 x200, 0 x204, 0 x208, 0 x0, 0 x0, 1 , "VCCT Voltage" },0 x21c, 0 x220, 0 x224, 0 x0, 0 x0, 1 , "1.8v Voltage" },0 x238, 0 x0, 0 x0, 0 x0, 0 x23c, 1 , "12v Backplane Voltage" },0 x254, 0 x0, 0 x0, 0 x0, 0 x258, 1 , "12v AUX Voltage" },static const struct m10bmc_sdata d5005bmc_curr_tbl[] = {0 x19c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA Core Current" },0 x1b8, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "3.3v Current" },0 x1d4, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VCCERAM Current" },0 x1f0, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VCCR Current" },0 x20c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VCCT Current" },0 x228, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "1.8v Current" },0 x240, 0 x244, 0 x0, 0 x0, 0 x0, 1 , "12v Backplane Current" },0 x25c, 0 x260, 0 x0, 0 x0, 0 x0, 1 , "12v AUX Current" },static const struct m10bmc_hwmon_board_data n3000bmc_hwmon_bdata = {static const struct hwmon_channel_info * const d5005bmc_hinfo[] = {static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = {static const struct m10bmc_sdata n5010bmc_temp_tbl[] = {0 x100, 0 x0, 0 x104, 0 x0, 0 x0, 1000 , "Board Local Temperature" },0 x108, 0 x0, 0 x10c, 0 x0, 0 x0, 1000 , "FPGA 1 Temperature" },0 x110, 0 x0, 0 x114, 0 x0, 0 x0, 1000 , "FPGA 2 Temperature" },0 x118, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "Card Top Temperature" },0 x11c, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "Card Bottom Temperature" },0 x128, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "FPGA 1.2V Temperature" },0 x134, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "FPGA 5V Temperature" },0 x140, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "FPGA 0.9V Temperature" },0 x14c, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "FPGA 0.85V Temperature" },0 x158, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "AUX 12V Temperature" },0 x164, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "Backplane 12V Temperature" },0 x1a8, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "QSFP28-1 Temperature" },0 x1ac, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "QSFP28-2 Temperature" },0 x1b0, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "QSFP28-3 Temperature" },0 x1b4, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "QSFP28-4 Temperature" },0 x1b8, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "CVL1 Internal Temperature" },0 x1bc, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "CVL2 Internal Temperature" },static const struct m10bmc_sdata n5010bmc_in_tbl[] = {0 x120, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA 1.2V Voltage" },0 x12c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA 5V Voltage" },0 x138, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA 0.9V Voltage" },0 x144, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA 0.85V Voltage" },0 x150, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "AUX 12V Voltage" },0 x15c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "Backplane 12V Voltage" },0 x16c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "DDR4 1.2V Voltage" },0 x17c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA 1.8V Voltage" },0 x184, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "QDR 1.3V Voltage" },0 x18c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "CVL1 0.8V Voltage" },0 x194, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "CVL1 1.05V Voltage" },0 x19c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "CVL2 1.05V Voltage" },0 x1a4, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "CVL2 0.8V Voltage" },static const struct m10bmc_sdata n5010bmc_curr_tbl[] = {0 x124, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA 1.2V Current" },0 x130, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA 5V Current" },0 x13c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA 0.9V Current" },0 x148, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA 0.85V Current" },0 x154, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "AUX 12V Current" },0 x160, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "Backplane 12V Current" },0 x168, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "DDR4 1.2V Current" },0 x178, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA 1.8V Current" },0 x180, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "QDR 1.3V Current" },0 x188, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "CVL1 0.8V Current" },0 x190, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "CVL1 1.05V Current" },0 x198, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "CVL2 1.05V Current" },0 x1a0, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "CVL2 0.8V Current" },static const struct hwmon_channel_info * const n5010bmc_hinfo[] = {static const struct m10bmc_hwmon_board_data n5010bmc_hwmon_bdata = {static const struct m10bmc_sdata n6000bmc_temp_tbl[] = {0 x444, 0 x448, 0 x44c, 0 x0, 0 x0, 500 , "FPGA E-TILE Temperature #1" },0 x450, 0 x454, 0 x458, 0 x0, 0 x0, 500 , "FPGA E-TILE Temperature #2" },0 x45c, 0 x460, 0 x464, 0 x0, 0 x0, 500 , "FPGA E-TILE Temperature #3" },0 x468, 0 x46c, 0 x470, 0 x0, 0 x0, 500 , "FPGA E-TILE Temperature #4" },0 x474, 0 x478, 0 x47c, 0 x0, 0 x0, 500 , "FPGA P-TILE Temperature" },0 x484, 0 x488, 0 x48c, 0 x0, 0 x0, 500 , "FPGA FABRIC Digital Temperature #1" },0 x490, 0 x494, 0 x498, 0 x0, 0 x0, 500 , "FPGA FABRIC Digital Temperature #2" },0 x49c, 0 x4a0, 0 x4a4, 0 x0, 0 x0, 500 , "FPGA FABRIC Digital Temperature #3" },0 x4a8, 0 x4ac, 0 x4b0, 0 x0, 0 x0, 500 , "FPGA FABRIC Digital Temperature #4" },0 x4b4, 0 x4b8, 0 x4bc, 0 x0, 0 x0, 500 , "FPGA FABRIC Digital Temperature #5" },0 x4c0, 0 x4c4, 0 x4c8, 0 x0, 0 x0, 500 , "FPGA FABRIC Remote Digital Temperature #1" },0 x4cc, 0 x4d0, 0 x4d4, 0 x0, 0 x0, 500 , "FPGA FABRIC Remote Digital Temperature #2" },0 x4d8, 0 x4dc, 0 x4e0, 0 x0, 0 x0, 500 , "FPGA FABRIC Remote Digital Temperature #3" },0 x4e4, 0 x4e8, 0 x4ec, 0 x0, 0 x0, 500 , "FPGA FABRIC Remote Digital Temperature #4" },0 x4f0, 0 x4f4, 0 x4f8, 0 x52c, 0 x0, 500 , "Board Top Near FPGA Temperature" },0 x4fc, 0 x500, 0 x504, 0 x52c, 0 x0, 500 , "Board Bottom Near CVL Temperature" },0 x508, 0 x50c, 0 x510, 0 x52c, 0 x0, 500 , "Board Top East Near VRs Temperature" },0 x514, 0 x518, 0 x51c, 0 x52c, 0 x0, 500 , "CVL Die Temperature" },0 x520, 0 x524, 0 x528, 0 x52c, 0 x0, 500 , "Board Rear Side Temperature" },0 x530, 0 x534, 0 x538, 0 x52c, 0 x0, 500 , "Board Front Side Temperature" },0 x53c, 0 x540, 0 x544, 0 x0, 0 x0, 500 , "QSFP1 Case Temperature" },0 x548, 0 x54c, 0 x550, 0 x0, 0 x0, 500 , "QSFP2 Case Temperature" },0 x554, 0 x0, 0 x0, 0 x0, 0 x0, 500 , "FPGA Core Voltage Phase 0 VR Temperature" },0 x560, 0 x0, 0 x0, 0 x0, 0 x0, 500 , "FPGA Core Voltage Phase 1 VR Temperature" },0 x56c, 0 x0, 0 x0, 0 x0, 0 x0, 500 , "FPGA Core Voltage Phase 2 VR Temperature" },0 x578, 0 x0, 0 x0, 0 x0, 0 x0, 500 , "FPGA Core Voltage VR Controller Temperature" },0 x584, 0 x0, 0 x0, 0 x0, 0 x0, 500 , "FPGA VCCH VR Temperature" },0 x590, 0 x0, 0 x0, 0 x0, 0 x0, 500 , "FPGA VCC_1V2 VR Temperature" },0 x59c, 0 x0, 0 x0, 0 x0, 0 x0, 500 , "FPGA VCCH, VCC_1V2 VR Controller Temperature" },0 x5a8, 0 x0, 0 x0, 0 x0, 0 x0, 500 , "3V3 VR Temperature" },0 x5b4, 0 x0, 0 x0, 0 x0, 0 x0, 500 , "CVL Core Voltage VR Temperature" },0 x5c4, 0 x5c8, 0 x5cc, 0 x5c0, 0 x0, 500 , "FPGA P-Tile Temperature [Remote]" },0 x5d0, 0 x5d4, 0 x5d8, 0 x5c0, 0 x0, 500 , "FPGA E-Tile Temperature [Remote]" },0 x5dc, 0 x5e0, 0 x5e4, 0 x5c0, 0 x0, 500 , "FPGA SDM Temperature [Remote]" },0 x5e8, 0 x5ec, 0 x5f0, 0 x5c0, 0 x0, 500 , "FPGA Corner Temperature [Remote]" },static const struct m10bmc_sdata n6000bmc_in_tbl[] = {0 x5f4, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "Inlet 12V PCIe Rail Voltage" },0 x60c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "Inlet 12V Aux Rail Voltage" },0 x624, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "Inlet 3V3 PCIe Rail Voltage" },0 x63c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA Core Voltage Rail Voltage" },0 x644, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA VCCH Rail Voltage" },0 x64c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA VCC_1V2 Rail Voltage" },0 x654, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA VCCH_GXER_1V1, VCCA_1V8 Voltage" },0 x664, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA VCCIO_1V2 Voltage" },0 x674, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "CVL Non Core Rails Inlet Voltage" },0 x684, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "MAX10 & Board CLK PWR 3V3 Inlet Voltage" },0 x694, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "CVL Core Voltage Rail Voltage" },0 x6ac, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "Board 3V3 VR Voltage" },0 x6b4, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "QSFP 3V3 Rail Voltage" },0 x6c4, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "QSFP (Primary) Supply Rail Voltage" },0 x6c8, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "QSFP (Secondary) Supply Rail Voltage" },0 x6cc, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VCCCLK_GXER_2V5 Voltage" },0 x6d0, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "AVDDH_1V1_CVL Voltage" },0 x6d4, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VDDH_1V8_CVL Voltage" },0 x6d8, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VCCA_PLL Voltage" },0 x6e0, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VCCRT_GXER_0V9 Voltage" },0 x6e8, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VCCRT_GXPL_0V9 Voltage" },0 x6f0, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VCCH_GXPL_1V8 Voltage" },0 x6f4, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VCCPT_1V8 Voltage" },0 x6fc, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VCC_3V3_M10 Voltage" },0 x700, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VCC_1V8_M10 Voltage" },0 x704, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VCC_1V2_EMIF1_2_3 Voltage" },0 x70c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VCC_1V2_EMIF4_5 Voltage" },0 x714, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VCCA_1V8 Voltage" },0 x718, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "VCCH_GXER_1V1 Voltage" },0 x71c, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "AVDD_ETH_0V9_CVL Voltage" },0 x720, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "AVDD_PCIE_0V9_CVL Voltage" },static const struct m10bmc_sdata n6000bmc_curr_tbl[] = {0 x600, 0 x604, 0 x608, 0 x0, 0 x0, 1 , "Inlet 12V PCIe Rail Current" },0 x618, 0 x61c, 0 x620, 0 x0, 0 x0, 1 , "Inlet 12V Aux Rail Current" },0 x630, 0 x634, 0 x638, 0 x0, 0 x0, 1 , "Inlet 3V3 PCIe Rail Current" },0 x640, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA Core Voltage Rail Current" },0 x648, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA VCCH Rail Current" },0 x650, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "FPGA VCC_1V2 Rail Current" },0 x658, 0 x65c, 0 x660, 0 x0, 0 x0, 1 , "FPGA VCCH_GXER_1V1, VCCA_1V8 Current" },0 x668, 0 x66c, 0 x670, 0 x0, 0 x0, 1 , "FPGA VCCIO_1V2 Current" },0 x678, 0 x67c, 0 x680, 0 x0, 0 x0, 1 , "CVL Non Core Rails Inlet Current" },0 x688, 0 x68c, 0 x690, 0 x0, 0 x0, 1 , "MAX10 & Board CLK PWR 3V3 Inlet Current" },0 x698, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "CVL Core Voltage Rail Current" },0 x6b0, 0 x0, 0 x0, 0 x0, 0 x0, 1 , "Board 3V3 VR Current" },0 x6b8, 0 x6bc, 0 x6c0, 0 x0, 0 x0, 1 , "QSFP 3V3 Rail Current" },static const struct m10bmc_sdata n6000bmc_power_tbl[] = {0 x724, 0 x0, 0 x0, 0 x0, 0 x0, 1000 , "Board Power" },static const struct hwmon_channel_info * const n6000bmc_hinfo[] = {static const struct m10bmc_hwmon_board_data n6000bmc_hwmon_bdata = {static const struct m10bmc_sdata *struct m10bmc_hwmon *hw, enum hwmon_sensor_types type,int channel)const struct m10bmc_sdata *tbl;if (!tbl)return ERR_PTR(-EOPNOTSUPP);return &tbl[channel];static int do_sensor_read(struct m10bmc_hwmon *hw,const struct m10bmc_sdata *data,unsigned int regoff, long *val)unsigned int regval;int ret;if (ret)return ret;/* * BMC Firmware will return 0xdeadbeef if the sensor value is invalid * at that time. This usually happens on sensor channels which connect * to external pluggable modules, e.g. QSFP temperature and voltage. * When the QSFP is unplugged from cage, driver will get 0xdeadbeef * from their registers. if (regval == 0 xdeadbeef)return -ENODATA;return 0 ;static int m10bmc_hwmon_read(struct device *dev, enum hwmon_sensor_types type,int channel, long *val)struct m10bmc_hwmon *hw = dev_get_drvdata(dev);unsigned int reg = 0 , reg_hyst = 0 ;const struct m10bmc_sdata *data;long hyst, value;int ret;if (IS_ERR(data))return PTR_ERR(data);switch (type) {case hwmon_temp:switch (attr) {case hwmon_temp_input:break ;case hwmon_temp_max_hyst:case hwmon_temp_max:break ;case hwmon_temp_crit_hyst:case hwmon_temp_crit:break ;default :return -EOPNOTSUPP;break ;case hwmon_in:switch (attr) {case hwmon_in_input:break ;case hwmon_in_max:break ;case hwmon_in_crit:break ;case hwmon_in_min:break ;default :return -EOPNOTSUPP;break ;case hwmon_curr:switch (attr) {case hwmon_curr_input:break ;case hwmon_curr_max:break ;case hwmon_curr_crit:break ;default :return -EOPNOTSUPP;break ;case hwmon_power:switch (attr) {case hwmon_power_input:break ;default :return -EOPNOTSUPP;break ;default :return -EOPNOTSUPP;if (!reg)return -EOPNOTSUPP;if (ret)return ret;if (reg_hyst) {if (ret)return ret;return 0 ;static int m10bmc_hwmon_read_string(struct device *dev,enum hwmon_sensor_types type,int channel, const char **str)struct m10bmc_hwmon *hw = dev_get_drvdata(dev);const struct m10bmc_sdata *data;if (IS_ERR(data))return PTR_ERR(data);return 0 ;static const struct hwmon_ops m10bmc_hwmon_ops = {0444 ,static int m10bmc_hwmon_probe(struct platform_device *pdev)const struct platform_device_id *id = platform_get_device_id(pdev);struct intel_m10bmc *m10bmc = dev_get_drvdata(pdev->dev.parent);struct device *hwmon_dev, *dev = &pdev->dev;struct m10bmc_hwmon *hw;sizeof (*hw), GFP_KERNEL);if (!hw)return -ENOMEM;const struct m10bmc_hwmon_board_data *)id->driver_data;if (IS_ERR(hw->hw_name))return PTR_ERR(hw->hw_name);return PTR_ERR_OR_ZERO(hwmon_dev);static const struct platform_device_id intel_m10bmc_hwmon_ids[] = {"n3000bmc-hwmon" ,unsigned long )&n3000bmc_hwmon_bdata,"d5005bmc-hwmon" ,unsigned long )&d5005bmc_hwmon_bdata,"n5010bmc-hwmon" ,unsigned long )&n5010bmc_hwmon_bdata,"n6000bmc-hwmon" ,unsigned long )&n6000bmc_hwmon_bdata,static struct platform_driver intel_m10bmc_hwmon_driver = {"intel-m10-bmc-hwmon" ,"Intel Corporation" );"Intel MAX 10 BMC hardware monitor" );"GPL" );"INTEL_M10_BMC_CORE" );
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