/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation #ifndef _XE_LRC_LAYOUT_H_#define _XE_LRC_LAYOUT_H_#define CTX_CONTEXT_CONTROL (0 x02 + 1 )#define CTX_RING_HEAD (0 x04 + 1 )#define CTX_RING_TAIL (0 x06 + 1 )#define CTX_RING_START (0 x08 + 1 )#define CTX_RING_CTL (0 x0a + 1 )#define CTX_BB_PER_CTX_PTR (0 x12 + 1 )#define CTX_CS_INDIRECT_CTX (0 x14 + 1 )#define CTX_CS_INDIRECT_CTX_OFFSET (0 x16 + 1 )#define CTX_TIMESTAMP (0 x22 + 1 )#define CTX_TIMESTAMP_UDW (0 x24 + 1 )#define CTX_INDIRECT_RING_STATE (0 x26 + 1 )#define CTX_ACC_CTR_THOLD (0 x2a + 1 )#define CTX_ASID (0 x2e + 1 )#define CTX_PDP0_UDW (0 x30 + 1 )#define CTX_PDP0_LDW (0 x32 + 1 )#define CTX_LRM_INT_MASK_ENABLE 0 x50#define CTX_INT_MASK_ENABLE_REG (CTX_LRM_INT_MASK_ENABLE + 1 )#define CTX_INT_MASK_ENABLE_PTR (CTX_LRM_INT_MASK_ENABLE + 2 )#define CTX_LRI_INT_REPORT_PTR 0 x55#define CTX_INT_STATUS_REPORT_REG (CTX_LRI_INT_REPORT_PTR + 1 )#define CTX_INT_STATUS_REPORT_PTR (CTX_LRI_INT_REPORT_PTR + 2 )#define CTX_INT_SRC_REPORT_REG (CTX_LRI_INT_REPORT_PTR + 3 )#define CTX_INT_SRC_REPORT_PTR (CTX_LRI_INT_REPORT_PTR + 4 )#define CTX_CS_INT_VEC_REG 0 x5a#define CTX_CS_INT_VEC_DATA (CTX_CS_INT_VEC_REG + 1 )#define INDIRECT_CTX_RING_HEAD (0 x02 + 1 )#define INDIRECT_CTX_RING_TAIL (0 x04 + 1 )#define INDIRECT_CTX_RING_START (0 x06 + 1 )#define INDIRECT_CTX_RING_START_UDW (0 x08 + 1 )#define INDIRECT_CTX_RING_CTL (0 x0a + 1 )#define CTX_INDIRECT_CTX_OFFSET_MASK REG_GENMASK(15 , 6 )#define CTX_INDIRECT_CTX_OFFSET_DEFAULT REG_FIELD_PREP(CTX_INDIRECT_CTX_OFFSET_MASK, 0 xd)#endif
Messung V0.5 in Prozent C=94 H=95 G=94
¤ Dauer der Verarbeitung: 0.9 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
