// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net> #include <linux/delay.h>#include <linux/of.h>#include <linux/of_platform.h>#include <linux/platform_device.h>#include "sun8i_dw_hdmi.h" /* * Address can be actually any value. Here is set to same value as * it is set in BSP driver. #define I2C_ADDR 0 x69static const struct dw_hdmi_mpll_config sun50i_h6_mpll_cfg[] = {30666000 , {0 x00b3, 0 x0000 },0 x2153, 0 x0000 },0 x40f3, 0 x0000 },36800000 , {0 x00b3, 0 x0000 },0 x2153, 0 x0000 },0 x40a2, 0 x0001 },46000000 , {0 x00b3, 0 x0000 },0 x2142, 0 x0001 },0 x40a2, 0 x0001 },61333000 , {0 x0072, 0 x0001 },0 x2142, 0 x0001 },0 x40a2, 0 x0001 },73600000 , {0 x0072, 0 x0001 },0 x2142, 0 x0001 },0 x4061, 0 x0002 },92000000 , {0 x0072, 0 x0001 },0 x2145, 0 x0002 },0 x4061, 0 x0002 },122666000 , {0 x0051, 0 x0002 },0 x2145, 0 x0002 },0 x4061, 0 x0002 },147200000 , {0 x0051, 0 x0002 },0 x2145, 0 x0002 },0 x4064, 0 x0003 },184000000 , {0 x0051, 0 x0002 },0 x214c, 0 x0003 },0 x4064, 0 x0003 },226666000 , {0 x0040, 0 x0003 },0 x214c, 0 x0003 },0 x4064, 0 x0003 },272000000 , {0 x0040, 0 x0003 },0 x214c, 0 x0003 },0 x5a64, 0 x0003 },340000000 , {0 x0040, 0 x0003 },0 x3b4c, 0 x0003 },0 x5a64, 0 x0003 },594000000 , {0 x1a40, 0 x0003 },0 x3b4c, 0 x0003 },0 x5a64, 0 x0003 },0 UL, {0 x0000, 0 x0000 },0 x0000, 0 x0000 },0 x0000, 0 x0000 },static const struct dw_hdmi_curr_ctrl sun50i_h6_cur_ctr[] = {/* pixelclk bpp8 bpp10 bpp12 */ 27000000 , { 0 x0012, 0 x0000, 0 x0000 }, },74250000 , { 0 x0013, 0 x001a, 0 x001b }, },148500000 , { 0 x0019, 0 x0033, 0 x0034 }, },297000000 , { 0 x0019, 0 x001b, 0 x001b }, },594000000 , { 0 x0010, 0 x001b, 0 x001b }, },0 UL, { 0 x0000, 0 x0000, 0 x0000 }, }static const struct dw_hdmi_phy_config sun50i_h6_phy_config[] = {/*pixelclk symbol term vlev*/ 27000000 , 0 x8009, 0 x0007, 0 x02b0 },74250000 , 0 x8009, 0 x0006, 0 x022d },148500000 , 0 x8029, 0 x0006, 0 x0270 },297000000 , 0 x8039, 0 x0005, 0 x01ab },594000000 , 0 x8029, 0 x0000, 0 x008a },0 UL, 0 x0000, 0 x0000, 0 x0000}static void sun8i_hdmi_phy_set_polarity(struct sun8i_hdmi_phy *phy,const struct drm_display_mode *mode)0 ;if (mode->flags & DRM_MODE_FLAG_NHSYNC)if (mode->flags & DRM_MODE_FLAG_NVSYNC)static int sun8i_a83t_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,const struct drm_display_info *display,const struct drm_display_mode *mode)unsigned int clk_rate = mode->crtc_clock * 1000 ;struct sun8i_hdmi_phy *phy = data;/* power down */ 0 );1 );0 );/* * Values are taken from BSP HDMI driver. Although AW didn't * release any documentation, explanation of this values can * be found in i.MX 6Dual/6Quad Reference Manual. if (clk_rate <= 27000000 ) {0 x01e0, 0 x06);0 x0000, 0 x15);0 x08da, 0 x10);0 x0007, 0 x19);0 x0318, 0 x0e);0 x8009, 0 x09);else if (clk_rate <= 74250000 ) {0 x0540, 0 x06);0 x0005, 0 x15);0 x0000, 0 x10);0 x0007, 0 x19);0 x02b5, 0 x0e);0 x8009, 0 x09);else if (clk_rate <= 148500000 ) {0 x04a0, 0 x06);0 x000a, 0 x15);0 x0000, 0 x10);0 x0002, 0 x19);0 x0021, 0 x0e);0 x8029, 0 x09);else {0 x0000, 0 x06);0 x000f, 0 x15);0 x0000, 0 x10);0 x0002, 0 x19);0 x0000, 0 x0e);0 x802b, 0 x09);0 x0000, 0 x1e);0 x0000, 0 x13);0 x0000, 0 x17);1 );return 0 ;static void sun8i_a83t_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)struct sun8i_hdmi_phy *phy = data;0 );1 );0 );static const struct dw_hdmi_phy_ops sun8i_a83t_hdmi_phy_ops = {static int sun8i_h3_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,const struct drm_display_info *display,const struct drm_display_mode *mode)unsigned int clk_rate = mode->crtc_clock * 1000 ;struct sun8i_hdmi_phy *phy = data;0 ;if (phy->variant->has_phy_clk)/* bandwidth / frequency independent settings */ 7 ) |1 ) |2 ) |63 ) |1 ) |1 ) |1 );0 x3e0) |/* bandwidth / frequency dependent settings */ if (clk_rate <= 27000000 ) {32 );4 ) |4 );4 ) |3 ) |5 );else if (clk_rate <= 74250000 ) {32 );4 ) |5 );4 ) |5 ) |7 );else if (clk_rate <= 148500000 ) {32 );4 ) |6 );2 );7 ) |9 );else {2 ;63 );6 ) |7 );4 );9 ) |13 ) |3 );0 );/* * NOTE: We have to be careful not to overwrite PHY parent * clock selection bit and clock divider. 10000 , 15000 );100 );/* get B value */ 0 x3f);100 );return 0 ;static void sun8i_h3_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)struct sun8i_hdmi_phy *phy = data;0 );static const struct dw_hdmi_phy_ops sun8i_h3_hdmi_phy_ops = {static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy)/* enable read access to HDMI controller */ /* unscramble register offsets */ static void sun50i_hdmi_phy_init_h6(struct sun8i_hdmi_phy *phy)0 xffff0000, 0 x80c00000);static void sun8i_hdmi_phy_init_a83t(struct sun8i_hdmi_phy *phy)/* * Set PHY I2C address. It must match to the address set by * dw_hdmi_phy_set_slave_addr(). static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy)unsigned int val;0 );5 );10 , 20 );5 );40 , 100 );100 , 200 );/* wait for calibration to finish */ 100 , 2000 );/* enable DDC communication */ /* reset PHY PLL clock parent */ 0 );/* set HW control of CEC pins */ 0 );/* read calibration data */ 2 ;int sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy)int ret;if (ret) {"Cannot deassert phy reset control: %d\n" , ret);return ret;if (ret) {"Cannot enable bus clock: %d\n" , ret);goto err_assert_rst_phy;if (ret) {"Cannot enable mod clock: %d\n" , ret);goto err_disable_clk_bus;if (phy->variant->has_phy_clk) {if (ret) {"Couldn't create the PHY clock\n" );goto err_disable_clk_mod;return 0 ;return ret;void sun8i_hdmi_phy_deinit(struct sun8i_hdmi_phy *phy)void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy,struct dw_hdmi_plat_data *plat_data)const struct sun8i_hdmi_phy_variant *variant = phy->variant;if (variant->phy_ops) {"sun8i_dw_hdmi_phy" ;else {static const struct regmap_config sun8i_hdmi_phy_regmap_config = {32 ,32 ,4 ,"phy" static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = {static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {true ,static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = {true ,true ,static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = {true ,static const struct sun8i_hdmi_phy_variant sun50i_h6_hdmi_phy = {static const struct of_device_id sun8i_hdmi_phy_of_table[] = {"allwinner,sun8i-a83t-hdmi-phy" ,"allwinner,sun8i-h3-hdmi-phy" ,"allwinner,sun8i-r40-hdmi-phy" ,"allwinner,sun50i-a64-hdmi-phy" ,"allwinner,sun50i-h6-hdmi-phy" ,/* sentinel */ } int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node)struct platform_device *pdev = of_find_device_by_node(node);struct sun8i_hdmi_phy *phy;if (!pdev)return -EPROBE_DEFER;if (!phy) {return -EPROBE_DEFER;return 0 ;static int sun8i_hdmi_phy_probe(struct platform_device *pdev)struct device *dev = &pdev->dev;struct sun8i_hdmi_phy *phy;void __iomem *regs;sizeof (*phy), GFP_KERNEL);if (!phy)return -ENOMEM;0 );if (IS_ERR(regs))return dev_err_probe(dev, PTR_ERR(regs),"Couldn't map the HDMI PHY registers\n" );if (IS_ERR(phy->regs))return dev_err_probe(dev, PTR_ERR(phy->regs),"Couldn't create the HDMI PHY regmap\n" );"bus" );if (IS_ERR(phy->clk_bus))return dev_err_probe(dev, PTR_ERR(phy->clk_bus),"Could not get bus clock\n" );"mod" );if (IS_ERR(phy->clk_mod))return dev_err_probe(dev, PTR_ERR(phy->clk_mod),"Could not get mod clock\n" );if (phy->variant->has_phy_clk) {"pll-0" );if (IS_ERR(phy->clk_pll0))return dev_err_probe(dev, PTR_ERR(phy->clk_pll0),"Could not get pll-0 clock\n" );if (phy->variant->has_second_pll) {"pll-1" );if (IS_ERR(phy->clk_pll1))return dev_err_probe(dev, PTR_ERR(phy->clk_pll1),"Could not get pll-1 clock\n" );"phy" );if (IS_ERR(phy->rst_phy))return dev_err_probe(dev, PTR_ERR(phy->rst_phy),"Could not get phy reset control\n" );return 0 ;struct platform_driver sun8i_hdmi_phy_driver = {"sun8i-hdmi-phy" ,
Messung V0.5 in Prozent C=94 H=92 G=92
¤ Dauer der Verarbeitung: 0.9 Sekunden
(vorverarbeitet am 2026-06-08)
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