/* SPDX-License-Identifier: GPL-2.0 */ /* * R-Car Display Unit Registers Definitions * * Copyright (C) 2013-2015 Renesas Electronics Corporation * * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) #ifndef __RCAR_DU_REGS_H__#define __RCAR_DU_REGS_H__#define DU0_REG_OFFSET 0 x00000#define DU1_REG_OFFSET 0 x30000#define DU2_REG_OFFSET 0 x40000#define DU3_REG_OFFSET 0 x70000/* ----------------------------------------------------------------------------- * Display Control Registers #define DSYSR 0 x00000 /* display 1 */ #define DSYSR_ILTS (1 << 29 )#define DSYSR_DSEC (1 << 20 )#define DSYSR_IUPD (1 << 16 )#define DSYSR_DRES (1 << 9 )#define DSYSR_DEN (1 << 8 )#define DSYSR_TVM_MASTER (0 << 6 )#define DSYSR_TVM_SWITCH (1 << 6 )#define DSYSR_TVM_TVSYNC (2 << 6 )#define DSYSR_TVM_MASK (3 << 6 )#define DSYSR_SCM_INT_NONE (0 << 4 )#define DSYSR_SCM_INT_SYNC (2 << 4 )#define DSYSR_SCM_INT_VIDEO (3 << 4 )#define DSYSR_SCM_MASK (3 << 4 )#define DSMR 0 x00004#define DSMR_VSPM (1 << 28 )#define DSMR_ODPM (1 << 27 )#define DSMR_DIPM_DISP (0 << 25 )#define DSMR_DIPM_CSYNC (1 << 25 )#define DSMR_DIPM_DE (3 << 25 )#define DSMR_DIPM_MASK (3 << 25 )#define DSMR_CSPM (1 << 24 )#define DSMR_DIL (1 << 19 )#define DSMR_VSL (1 << 18 )#define DSMR_HSL (1 << 17 )#define DSMR_DDIS (1 << 16 )#define DSMR_CDEL (1 << 15 )#define DSMR_CDEM_CDE (0 << 13 )#define DSMR_CDEM_LOW (2 << 13 )#define DSMR_CDEM_HIGH (3 << 13 )#define DSMR_CDEM_MASK (3 << 13 )#define DSMR_CDED (1 << 12 )#define DSMR_ODEV (1 << 8 )#define DSMR_CSY_VH_OR (0 << 6 )#define DSMR_CSY_333 (2 << 6 )#define DSMR_CSY_222 (3 << 6 )#define DSMR_CSY_MASK (3 << 6 )#define DSSR 0 x00008#define DSSR_VC1FB_DSA0 (0 << 30 )#define DSSR_VC1FB_DSA1 (1 << 30 )#define DSSR_VC1FB_DSA2 (2 << 30 )#define DSSR_VC1FB_INIT (3 << 30 )#define DSSR_VC1FB_MASK (3 << 30 )#define DSSR_VC0FB_DSA0 (0 << 28 )#define DSSR_VC0FB_DSA1 (1 << 28 )#define DSSR_VC0FB_DSA2 (2 << 28 )#define DSSR_VC0FB_INIT (3 << 28 )#define DSSR_VC0FB_MASK (3 << 28 )#define DSSR_DFB(n) (1 << ((n)+15 ))#define DSSR_TVR (1 << 15 )#define DSSR_FRM (1 << 14 )#define DSSR_VBK (1 << 11 )#define DSSR_RINT (1 << 9 )#define DSSR_HBK (1 << 8 )#define DSSR_ADC(n) (1 << ((n)-1 ))#define DSRCR 0 x0000c#define DSRCR_TVCL (1 << 15 )#define DSRCR_FRCL (1 << 14 )#define DSRCR_VBCL (1 << 11 )#define DSRCR_RICL (1 << 9 )#define DSRCR_HBCL (1 << 8 )#define DSRCR_ADCL(n) (1 << ((n)-1 ))#define DSRCR_MASK 0 x0000cbff#define DIER 0 x00010#define DIER_TVE (1 << 15 )#define DIER_FRE (1 << 14 )#define DIER_VBE (1 << 11 )#define DIER_RIE (1 << 9 )#define DIER_HBE (1 << 8 )#define DIER_ADCE(n) (1 << ((n)-1 ))#define CPCR 0 x00014#define CPCR_CP4CE (1 << 19 )#define CPCR_CP3CE (1 << 18 )#define CPCR_CP2CE (1 << 17 )#define CPCR_CP1CE (1 << 16 )#define DPPR 0 x00018#define DPPR_DPE(n) (1 << ((n)*4 -1 ))#define DPPR_DPS(n, p) (((p)-1 ) << DPPR_DPS_SHIFT(n))#define DPPR_DPS_SHIFT(n) (((n)-1 )*4 )#define DPPR_BPP16 (DPPR_DPE(8 ) | DPPR_DPS(8 , 1 )) /* plane1 */ #define DPPR_BPP32_P1 (DPPR_DPE(7 ) | DPPR_DPS(7 , 1 ))#define DPPR_BPP32_P2 (DPPR_DPE(8 ) | DPPR_DPS(8 , 2 ))#define DPPR_BPP32 (DPPR_BPP32_P1 | DPPR_BPP32_P2) /* plane1 & 2 */ #define DEFR 0 x00020#define DEFR_CODE (0 x7773 << 16 )#define DEFR_EXSL (1 << 12 )#define DEFR_EXVL (1 << 11 )#define DEFR_EXUP (1 << 5 )#define DEFR_VCUP (1 << 4 )#define DEFR_DEFE (1 << 0 )#define DAPCR 0 x00024#define DAPCR_CODE (0 x7773 << 16 )#define DAPCR_AP2E (1 << 4 )#define DAPCR_AP1E (1 << 0 )#define DCPCR 0 x00028#define DCPCR_CODE (0 x7773 << 16 )#define DCPCR_CA2B (1 << 13 )#define DCPCR_CD2F (1 << 12 )#define DCPCR_DC2E (1 << 8 )#define DCPCR_CAB (1 << 5 )#define DCPCR_CDF (1 << 4 )#define DCPCR_DCE (1 << 0 )#define DEFR2 0 x00034#define DEFR2_CODE (0 x7775 << 16 )#define DEFR2_DEFE2G (1 << 0 )#define DEFR3 0 x00038#define DEFR3_CODE (0 x7776 << 16 )#define DEFR3_EVDA (1 << 14 )#define DEFR3_EVDM_1 (1 << 12 )#define DEFR3_EVDM_2 (2 << 12 )#define DEFR3_EVDM_3 (3 << 12 )#define DEFR3_VMSM2_EMA (1 << 6 )#define DEFR3_VMSM1_ENA (1 << 4 )#define DEFR3_DEFE3 (1 << 0 )#define DEFR4 0 x0003c#define DEFR4_CODE (0 x7777 << 16 )#define DEFR4_LRUO (1 << 5 )#define DEFR4_SPCE (1 << 4 )#define DVCSR 0 x000d0#define DVCSR_VCnFB2_DSA0(n) (0 << ((n)*2 +16 ))#define DVCSR_VCnFB2_DSA1(n) (1 << ((n)*2 +16 ))#define DVCSR_VCnFB2_DSA2(n) (2 << ((n)*2 +16 ))#define DVCSR_VCnFB2_INIT(n) (3 << ((n)*2 +16 ))#define DVCSR_VCnFB2_MASK(n) (3 << ((n)*2 +16 ))#define DVCSR_VCnFB_DSA0(n) (0 << ((n)*2 ))#define DVCSR_VCnFB_DSA1(n) (1 << ((n)*2 ))#define DVCSR_VCnFB_DSA2(n) (2 << ((n)*2 ))#define DVCSR_VCnFB_INIT(n) (3 << ((n)*2 ))#define DVCSR_VCnFB_MASK(n) (3 << ((n)*2 ))#define DEFR5 0 x000e0#define DEFR5_CODE (0 x66 << 24 )#define DEFR5_YCRGB2_DIS (0 << 14 )#define DEFR5_YCRGB2_PRI1 (1 << 14 )#define DEFR5_YCRGB2_PRI2 (2 << 14 )#define DEFR5_YCRGB2_PRI3 (3 << 14 )#define DEFR5_YCRGB2_MASK (3 << 14 )#define DEFR5_YCRGB1_DIS (0 << 12 )#define DEFR5_YCRGB1_PRI1 (1 << 12 )#define DEFR5_YCRGB1_PRI2 (2 << 12 )#define DEFR5_YCRGB1_PRI3 (3 << 12 )#define DEFR5_YCRGB1_MASK (3 << 12 )#define DEFR5_DEFE5 (1 << 0 )#define DDLTR 0 x000e4#define DDLTR_CODE (0 x7766 << 16 )#define DDLTR_DLAR2 (1 << 6 )#define DDLTR_DLAY2 (1 << 5 )#define DDLTR_DLAY1 (1 << 1 )#define DEFR6 0 x000e8#define DEFR6_CODE (0 x7778 << 16 )#define DEFR6_ODPM12_DSMR (0 << 10 )#define DEFR6_ODPM12_DISP (2 << 10 )#define DEFR6_ODPM12_CDE (3 << 10 )#define DEFR6_ODPM12_MASK (3 << 10 )#define DEFR6_ODPM02_DSMR (0 << 8 )#define DEFR6_ODPM02_DISP (2 << 8 )#define DEFR6_ODPM02_CDE (3 << 8 )#define DEFR6_ODPM02_MASK (3 << 8 )#define DEFR6_TCNE1 (1 << 6 )#define DEFR6_TCNE0 (1 << 4 )#define DEFR6_MLOS1 (1 << 2 )#define DEFR6_DEFAULT (DEFR6_CODE | DEFR6_TCNE1)#define DEFR7 0 x000ec#define DEFR7_CODE (0 x7779 << 16 )#define DEFR7_CMME1 BIT(6 )#define DEFR7_CMME0 BIT(4 )/* ----------------------------------------------------------------------------- * R8A7790-only Control Registers #define DD1SSR 0 x20008#define DD1SSR_TVR (1 << 15 )#define DD1SSR_FRM (1 << 14 )#define DD1SSR_BUF (1 << 12 )#define DD1SSR_VBK (1 << 11 )#define DD1SSR_RINT (1 << 9 )#define DD1SSR_HBK (1 << 8 )#define DD1SSR_ADC(n) (1 << ((n)-1 ))#define DD1SRCR 0 x2000c#define DD1SRCR_TVR (1 << 15 )#define DD1SRCR_FRM (1 << 14 )#define DD1SRCR_BUF (1 << 12 )#define DD1SRCR_VBK (1 << 11 )#define DD1SRCR_RINT (1 << 9 )#define DD1SRCR_HBK (1 << 8 )#define DD1SRCR_ADC(n) (1 << ((n)-1 ))#define DD1IER 0 x20010#define DD1IER_TVR (1 << 15 )#define DD1IER_FRM (1 << 14 )#define DD1IER_BUF (1 << 12 )#define DD1IER_VBK (1 << 11 )#define DD1IER_RINT (1 << 9 )#define DD1IER_HBK (1 << 8 )#define DD1IER_ADC(n) (1 << ((n)-1 ))#define DEFR8 0 x20020#define DEFR8_CODE (0 x7790 << 16 )#define DEFR8_VSCS (1 << 6 )#define DEFR8_DRGBS_DU(n) ((n) << 4 )#define DEFR8_DRGBS_MASK (3 << 4 )#define DEFR8_DEFE8 (1 << 0 )#define DOFLR 0 x20024#define DOFLR_CODE (0 x7790 << 16 )#define DOFLR_HSYCFL1 (1 << 13 )#define DOFLR_VSYCFL1 (1 << 12 )#define DOFLR_ODDFL1 (1 << 11 )#define DOFLR_DISPFL1 (1 << 10 )#define DOFLR_CDEFL1 (1 << 9 )#define DOFLR_RGBFL1 (1 << 8 )#define DOFLR_HSYCFL0 (1 << 5 )#define DOFLR_VSYCFL0 (1 << 4 )#define DOFLR_ODDFL0 (1 << 3 )#define DOFLR_DISPFL0 (1 << 2 )#define DOFLR_CDEFL0 (1 << 1 )#define DOFLR_RGBFL0 (1 << 0 )#define DIDSR 0 x20028#define DIDSR_CODE (0 x7790 << 16 )#define DIDSR_LDCS_DCLKIN(n) (0 << (8 + (n) * 2 ))#define DIDSR_LDCS_DSI(n) (2 << (8 + (n) * 2 )) /* V3U only */ #define DIDSR_LDCS_LVDS0(n) (2 << (8 + (n) * 2 ))#define DIDSR_LDCS_LVDS1(n) (3 << (8 + (n) * 2 ))#define DIDSR_LDCS_MASK(n) (3 << (8 + (n) * 2 ))#define DIDSR_PDCS_CLK(n, clk) (clk << ((n) * 2 ))#define DIDSR_PDCS_MASK(n) (3 << ((n) * 2 ))#define DEFR10 0 x20038#define DEFR10_CODE (0 x7795 << 16 )#define DEFR10_VSPF1_RGB (0 << 14 )#define DEFR10_VSPF1_YC (1 << 14 )#define DEFR10_DOCF1_RGB (0 << 12 )#define DEFR10_DOCF1_YC (1 << 12 )#define DEFR10_YCDF0_YCBCR444 (0 << 11 )#define DEFR10_YCDF0_YCBCR422 (1 << 11 )#define DEFR10_VSPF0_RGB (0 << 10 )#define DEFR10_VSPF0_YC (1 << 10 )#define DEFR10_DOCF0_RGB (0 << 8 )#define DEFR10_DOCF0_YC (1 << 8 )#define DEFR10_TSEL_H3_TCON1 (0 << 1 ) /* DEFR102 register only (DU2/DU3) */ #define DEFR10_DEFE10 (1 << 0 )#define DPLLCR 0 x20044#define DPLLCR_CODE (0 x95 << 24 )#define DPLLCR_PLCS1 (1 << 23 )#define DPLLCR_PLCS0 (1 << 21 )#define DPLLCR_CLKE (1 << 18 )#define DPLLCR_FDPLL(n) ((n) << 12 )#define DPLLCR_N(n) ((n) << 5 )#define DPLLCR_M(n) ((n) << 3 )#define DPLLCR_STBY (1 << 2 )#define DPLLCR_INCS_DOTCLKIN0 (0 << 0 )#define DPLLCR_INCS_DOTCLKIN1 (1 << 1 )#define DPLLC2R 0 x20048#define DPLLC2R_CODE (0 x95 << 24 )#define DPLLC2R_SELC (1 << 12 )#define DPLLC2R_M(n) ((n) << 8 )#define DPLLC2R_FDPLL(n) ((n) << 0 )/* ----------------------------------------------------------------------------- * Display Timing Generation Registers #define HDSR 0 x00040#define HDER 0 x00044#define VDSR 0 x00048#define VDER 0 x0004c#define HCR 0 x00050#define HSWR 0 x00054#define VCR 0 x00058#define VSPR 0 x0005c#define EQWR 0 x00060#define SPWR 0 x00064#define CLAMPSR 0 x00070#define CLAMPWR 0 x00074#define DESR 0 x00078#define DEWR 0 x0007c/* ----------------------------------------------------------------------------- * Display Attribute Registers #define CP1TR 0 x00080#define CP2TR 0 x00084#define CP3TR 0 x00088#define CP4TR 0 x0008c#define DOOR 0 x00090#define DOOR_RGB(r, g, b) (((r) << 18 ) | ((g) << 10 ) | ((b) << 2 ))#define CDER 0 x00094#define CDER_RGB(r, g, b) (((r) << 18 ) | ((g) << 10 ) | ((b) << 2 ))#define BPOR 0 x00098#define BPOR_RGB(r, g, b) (((r) << 18 ) | ((g) << 10 ) | ((b) << 2 ))#define RINTOFSR 0 x0009c#define DSHPR 0 x000c8#define DSHPR_CODE (0 x7776 << 16 )#define DSHPR_PRIH (0 xa << 4 )#define DSHPR_PRIL_BPP16 (0 x8 << 0 )#define DSHPR_PRIL_BPP32 (0 x9 << 0 )/* ----------------------------------------------------------------------------- * Display Plane Registers #define PLANE_OFF 0 x00100#define PnMR 0 x00100 /* plane 1 */ #define PnMR_VISL_VIN0 (0 << 26 ) /* use Video Input 0 */ #define PnMR_VISL_VIN1 (1 << 26 ) /* use Video Input 1 */ #define PnMR_VISL_VIN2 (2 << 26 ) /* use Video Input 2 */ #define PnMR_VISL_VIN3 (3 << 26 ) /* use Video Input 3 */ #define PnMR_YCDF_YUYV (1 << 20 ) /* YUYV format */ #define PnMR_TC_R (0 << 17 ) /* Tranparent color is PnTC1R */ #define PnMR_TC_CP (1 << 17 ) /* Tranparent color is color palette */ #define PnMR_WAE (1 << 16 ) /* Wrap around Enable */ #define PnMR_SPIM_TP (0 << 12 ) /* Transparent Color */ #define PnMR_SPIM_ALP (1 << 12 ) /* Alpha Blending */ #define PnMR_SPIM_EOR (2 << 12 ) /* EOR */ #define PnMR_SPIM_TP_OFF (1 << 14 ) /* No Transparent Color */ #define PnMR_CPSL_CP1 (0 << 8 ) /* Color Palette selected 1 */ #define PnMR_CPSL_CP2 (1 << 8 ) /* Color Palette selected 2 */ #define PnMR_CPSL_CP3 (2 << 8 ) /* Color Palette selected 3 */ #define PnMR_CPSL_CP4 (3 << 8 ) /* Color Palette selected 4 */ #define PnMR_DC (1 << 7 ) /* Display Area Change */ #define PnMR_BM_MD (0 << 4 ) /* Manual Display Change Mode */ #define PnMR_BM_AR (1 << 4 ) /* Auto Rendering Mode */ #define PnMR_BM_AD (2 << 4 ) /* Auto Display Change Mode */ #define PnMR_BM_VC (3 << 4 ) /* Video Capture Mode */ #define PnMR_DDDF_8BPP (0 << 0 ) /* 8bit */ #define PnMR_DDDF_16BPP (1 << 0 ) /* 16bit or 32bit */ #define PnMR_DDDF_ARGB (2 << 0 ) /* ARGB */ #define PnMR_DDDF_YC (3 << 0 ) /* YC */ #define PnMR_DDDF_MASK (3 << 0 )#define PnMWR 0 x00104#define PnALPHAR 0 x00108#define PnALPHAR_ABIT_1 (0 << 12 )#define PnALPHAR_ABIT_0 (1 << 12 )#define PnALPHAR_ABIT_X (2 << 12 )#define PnDSXR 0 x00110#define PnDSYR 0 x00114#define PnDPXR 0 x00118#define PnDPYR 0 x0011c#define PnDSA0R 0 x00120#define PnDSA1R 0 x00124#define PnDSA2R 0 x00128#define PnDSA_MASK 0 xfffffff0#define PnSPXR 0 x00130#define PnSPYR 0 x00134#define PnWASPR 0 x00138#define PnWAMWR 0 x0013c#define PnBTR 0 x00140#define PnTC1R 0 x00144#define PnTC2R 0 x00148#define PnTC3R 0 x0014c#define PnTC3R_CODE (0 x66 << 24 )#define PnMLR 0 x00150#define PnSWAPR 0 x00180#define PnSWAPR_DIGN (1 << 4 )#define PnSWAPR_SPQW (1 << 3 )#define PnSWAPR_SPLW (1 << 2 )#define PnSWAPR_SPWD (1 << 1 )#define PnSWAPR_SPBY (1 << 0 )#define PnDDCR 0 x00184#define PnDDCR_CODE (0 x7775 << 16 )#define PnDDCR_LRGB1 (1 << 11 )#define PnDDCR_LRGB0 (1 << 10 )#define PnDDCR2 0 x00188#define PnDDCR2_CODE (0 x7776 << 16 )#define PnDDCR2_NV21 (1 << 5 )#define PnDDCR2_Y420 (1 << 4 )#define PnDDCR2_DIVU (1 << 1 )#define PnDDCR2_DIVY (1 << 0 )#define PnDDCR4 0 x00190#define PnDDCR4_CODE (0 x7766 << 16 )#define PnDDCR4_VSPS (1 << 13 )#define PnDDCR4_SDFS_RGB (0 << 4 )#define PnDDCR4_SDFS_YC (5 << 4 )#define PnDDCR4_SDFS_MASK (7 << 4 )#define PnDDCR4_EDF_NONE (0 << 0 )#define PnDDCR4_EDF_ARGB8888 (1 << 0 )#define PnDDCR4_EDF_RGB888 (2 << 0 )#define PnDDCR4_EDF_RGB666 (3 << 0 )#define PnDDCR4_EDF_MASK (7 << 0 )#define APnMR 0 x0a100#define APnMR_WAE (1 << 16 ) /* Wrap around Enable */ #define APnMR_DC (1 << 7 ) /* Display Area Change */ #define APnMR_BM_MD (0 << 4 ) /* Manual Display Change Mode */ #define APnMR_BM_AD (2 << 4 ) /* Auto Display Change Mode */ #define APnMWR 0 x0a104#define APnDSXR 0 x0a110#define APnDSYR 0 x0a114#define APnDPXR 0 x0a118#define APnDPYR 0 x0a11c#define APnDSA0R 0 x0a120#define APnDSA1R 0 x0a124#define APnDSA2R 0 x0a128#define APnSPXR 0 x0a130#define APnSPYR 0 x0a134#define APnWASPR 0 x0a138#define APnWAMWR 0 x0a13c#define APnBTR 0 x0a140#define APnMLR 0 x0a150#define APnSWAPR 0 x0a180/* ----------------------------------------------------------------------------- * Display Capture Registers #define DCMR 0 x0c100#define DCMWR 0 x0c104#define DCSAR 0 x0c120#define DCMLR 0 x0c150/* ----------------------------------------------------------------------------- * Color Palette Registers #define CP1_000R 0 x01000#define CP1_255R 0 x013fc#define CP2_000R 0 x02000#define CP2_255R 0 x023fc#define CP3_000R 0 x03000#define CP3_255R 0 x033fc#define CP4_000R 0 x04000#define CP4_255R 0 x043fc/* ----------------------------------------------------------------------------- * External Synchronization Control Registers #define ESCR02 0 x10000#define ESCR13 0 x01000#define ESCR_DCLKOINV (1 << 25 )#define ESCR_DCLKSEL_DCLKIN (0 << 20 )#define ESCR_DCLKSEL_CLKS (1 << 20 )#define ESCR_DCLKSEL_MASK (1 << 20 )#define ESCR_DCLKDIS (1 << 16 )#define ESCR_SYNCSEL_OFF (0 << 8 )#define ESCR_SYNCSEL_EXVSYNC (2 << 8 )#define ESCR_SYNCSEL_EXHSYNC (3 << 8 )#define ESCR_FRQSEL_MASK (0 x3f << 0 )#define OTAR02 0 x10004#define OTAR13 0 x01004/* ----------------------------------------------------------------------------- * Dual Display Output Control Registers #define DORCR 0 x11000#define DORCR_PG1T (1 << 30 )#define DORCR_DK1S (1 << 28 )#define DORCR_PG1D_DS0 (0 << 24 )#define DORCR_PG1D_DS1 (1 << 24 )#define DORCR_PG1D_FIX0 (2 << 24 )#define DORCR_PG1D_DOOR (3 << 24 )#define DORCR_PG1D_MASK (3 << 24 )#define DORCR_DR0D (1 << 21 )#define DORCR_PG0D_DS0 (0 << 16 )#define DORCR_PG0D_DS1 (1 << 16 )#define DORCR_PG0D_FIX0 (2 << 16 )#define DORCR_PG0D_DOOR (3 << 16 )#define DORCR_PG0D_MASK (3 << 16 )#define DORCR_RGPV (1 << 4 )#define DORCR_DPRS (1 << 0 )#define DPTSR 0 x11004#define DPTSR_PnDK(n) (1 << ((n) + 16 ))#define DPTSR_PnTS(n) (1 << (n))#define DAPTSR 0 x11008#define DAPTSR_APnDK(n) (1 << ((n) + 16 ))#define DAPTSR_APnTS(n) (1 << (n))#define DS1PR 0 x11020#define DS2PR 0 x11024/* ----------------------------------------------------------------------------- * YC-RGB Conversion Coefficient Registers #define YNCR 0 x11080#define YNOR 0 x11084#define CRNOR 0 x11088#define CBNOR 0 x1108c#define RCRCR 0 x11090#define GCRCR 0 x11094#define GCBCR 0 x11098#define BCBCR 0 x1109c#endif /* __RCAR_DU_REGS_H__ */
Messung V0.5 in Prozent C=95 H=94 G=94
¤ Dauer der Verarbeitung: 0.11 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
