// SPDX-License-Identifier: GPL-2.0
/*
* NV3051D MIPI-DSI panel driver for Anbernic RG353x
* Copyright (C) 2022 Chris Morgan
*
* based on
*
* Elida kd35t133 3.5" MIPI-DSI panel driver
* Copyright (C) Theobroma Systems 2020
*/
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/media-bus-format.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>
#include <video/display_timing.h>
#include <video/mipi_display.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_modes.h>
#include <drm/drm_panel.h>
struct nv3051d_panel_info {
const struct drm_display_mode *display_modes;
unsigned int num_modes;
u16 width_mm, height_mm;
u32 bus_flags;
u32 mode_flags;
};
struct panel_nv3051d {
struct device *dev;
struct drm_panel panel;
struct gpio_desc *reset_gpio;
const struct nv3051d_panel_info *panel_info;
struct regulator *vdd;
};
static inline struct panel_nv3051d *panel_to_panelnv3051d(struct drm_panel *panel)
{
return container_of(panel, struct panel_nv3051d, panel);
}
static int panel_nv3051d_init_sequence(struct panel_nv3051d *ctx)
{
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi};
/*
* Init sequence was supplied by device vendor with no
* documentation.
*/
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xFF, 0 x30);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xFF, 0 x52);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xFF, 0 x01);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xE3, 0 x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x03, 0 x40);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x04, 0 x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x05, 0 x03);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x24, 0 x12);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x25, 0 x1E);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x26, 0 x28);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x27, 0 x52);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x28, 0 x57);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x29, 0 x01);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x2A, 0 xDF);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x38, 0 x9C);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x39, 0 xA7);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x3A, 0 x53);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x44, 0 x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x49, 0 x3C);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x59, 0 xFE);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x5C, 0 x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x91, 0 x77);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x92, 0 x77);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xA0, 0 x55);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xA1, 0 x50);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xA4, 0 x9C);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xA7, 0 x02);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xA8, 0 x01);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xA9, 0 x01);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xAA, 0 xFC);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xAB, 0 x28);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xAC, 0 x06);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xAD, 0 x06);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xAE, 0 x06);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xAF, 0 x03);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB0, 0 x08);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB1, 0 x26);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB2, 0 x28);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB3, 0 x28);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB4, 0 x33);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB5, 0 x08);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB6, 0 x26);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB7, 0 x08);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB8, 0 x26);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xFF, 0 x30);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xFF, 0 x52);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xFF, 0 x02);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB1, 0 x0E);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xD1, 0 x0E);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB4, 0 x29);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xD4, 0 x2B);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB2, 0 x0C);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xD2, 0 x0A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB3, 0 x28);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xD3, 0 x28);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB6, 0 x11);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xD6, 0 x0D);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB7, 0 x32);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xD7, 0 x30);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xC1, 0 x04);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xE1, 0 x06);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB8, 0 x0A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xD8, 0 x0A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB9, 0 x01);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xD9, 0 x01);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xBD, 0 x13);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xDD, 0 x13);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xBC, 0 x11);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xDC, 0 x11);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xBB, 0 x0F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xDB, 0 x0F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xBA, 0 x0F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xDA, 0 x0F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xBE, 0 x18);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xDE, 0 x18);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xBF, 0 x0F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xDF, 0 x0F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xC0, 0 x17);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xE0, 0 x17);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB5, 0 x3B);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xD5, 0 x3C);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB0, 0 x0B);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xD0, 0 x0C);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xFF, 0 x30);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xFF, 0 x52);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xFF, 0 x03);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x00, 0 x2A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x01, 0 x2A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x02, 0 x2A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x03, 0 x2A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x04, 0 x61);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x05, 0 x80);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x06, 0 xC7);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x07, 0 x01);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x08, 0 x82);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x09, 0 x83);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x30, 0 x2A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x31, 0 x2A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x32, 0 x2A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x33, 0 x2A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x34, 0 x61);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x35, 0 xC5);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x36, 0 x80);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x37, 0 x23);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x40, 0 x82);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x41, 0 x83);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x42, 0 x80);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x43, 0 x81);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x44, 0 x11);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x45, 0 xF2);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x46, 0 xF1);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x47, 0 x11);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x48, 0 xF4);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x49, 0 xF3);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x50, 0 x02);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x51, 0 x01);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x52, 0 x04);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x53, 0 x03);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x54, 0 x11);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x55, 0 xF6);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x56, 0 xF5);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x57, 0 x11);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x58, 0 xF8);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x59, 0 xF7);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x7E, 0 x02);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x7F, 0 x80);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xE0, 0 x5A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB1, 0 x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB4, 0 x0E);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB5, 0 x0F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB6, 0 x04);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB7, 0 x07);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB8, 0 x06);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xB9, 0 x05);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xBA, 0 x0F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xC7, 0 x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xCA, 0 x0E);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xCB, 0 x0F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xCC, 0 x04);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xCD, 0 x07);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xCE, 0 x06);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xCF, 0 x05);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xD0, 0 x0F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x81, 0 x0F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x84, 0 x0E);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x85, 0 x0F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x86, 0 x07);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x87, 0 x04);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x88, 0 x05);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x89, 0 x06);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x8A, 0 x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x97, 0 x0F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x9A, 0 x0E);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x9B, 0 x0F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x9C, 0 x07);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x9D, 0 x04);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x9E, 0 x05);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x9F, 0 x06);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xA0, 0 x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xFF, 0 x30);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xFF, 0 x52);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xFF, 0 x02);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x01, 0 x01);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x02, 0 xDA);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x03, 0 xBA);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x04, 0 xA8);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x05, 0 x9A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x06, 0 x70);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x07, 0 xFF);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x08, 0 x91);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x09, 0 x90);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x0A, 0 xFF);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x0B, 0 x8F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x0C, 0 x60);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x0D, 0 x58);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x0E, 0 x48);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x0F, 0 x38);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x10, 0 x2B);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xFF, 0 x30);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xFF, 0 x52);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 xFF, 0 x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x36, 0 x02);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0 x3A, 0 x70);
dev_dbg(ctx->dev, "Panel init sequence done\n" );
return 0 ;
}
static int panel_nv3051d_unprepare(struct drm_panel *panel)
{
struct panel_nv3051d *ctx = panel_to_panelnv3051d(panel);
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
int ret;
ret = mipi_dsi_dcs_set_display_off(dsi);
if (ret < 0 )
dev_err(ctx->dev, "failed to set display off: %d\n" , ret);
msleep(20 );
ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
if (ret < 0 ) {
dev_err(ctx->dev, "failed to enter sleep mode: %d\n" , ret);
return ret;
}
usleep_range(10000 , 15000 );
gpiod_set_value_cansleep(ctx->reset_gpio, 1 );
regulator_disable(ctx->vdd);
return 0 ;
}
static int panel_nv3051d_prepare(struct drm_panel *panel)
{
struct panel_nv3051d *ctx = panel_to_panelnv3051d(panel);
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
int ret;
dev_dbg(ctx->dev, "Resetting the panel\n" );
ret = regulator_enable(ctx->vdd);
if (ret < 0 ) {
dev_err(ctx->dev, "Failed to enable vdd supply: %d\n" , ret);
return ret;
}
usleep_range(2000 , 3000 );
gpiod_set_value_cansleep(ctx->reset_gpio, 1 );
msleep(150 );
gpiod_set_value_cansleep(ctx->reset_gpio, 0 );
msleep(20 );
ret = panel_nv3051d_init_sequence(ctx);
if (ret < 0 ) {
dev_err(ctx->dev, "Panel init sequence failed: %d\n" , ret);
goto disable_vdd;
}
ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
if (ret < 0 ) {
dev_err(ctx->dev, "Failed to exit sleep mode: %d\n" , ret);
goto disable_vdd;
}
msleep(200 );
ret = mipi_dsi_dcs_set_display_on(dsi);
if (ret < 0 ) {
dev_err(ctx->dev, "Failed to set display on: %d\n" , ret);
goto disable_vdd;
}
usleep_range(10000 , 15000 );
return 0 ;
disable_vdd:
regulator_disable(ctx->vdd);
return ret;
}
static int panel_nv3051d_get_modes(struct drm_panel *panel,
struct drm_connector *connector)
{
struct panel_nv3051d *ctx = panel_to_panelnv3051d(panel);
const struct nv3051d_panel_info *panel_info = ctx->panel_info;
struct drm_display_mode *mode;
unsigned int i;
for (i = 0 ; i < panel_info->num_modes; i++) {
mode = drm_mode_duplicate(connector->dev,
&panel_info->display_modes[i]);
if (!mode)
return -ENOMEM;
drm_mode_set_name(mode);
mode->type = DRM_MODE_TYPE_DRIVER;
if (panel_info->num_modes == 1 )
mode->type |= DRM_MODE_TYPE_PREFERRED;
drm_mode_probed_add(connector, mode);
}
connector->display_info.bpc = 8 ;
connector->display_info.width_mm = panel_info->width_mm;
connector->display_info.height_mm = panel_info->height_mm;
connector->display_info.bus_flags = panel_info->bus_flags;
return panel_info->num_modes;
}
static const struct drm_panel_funcs panel_nv3051d_funcs = {
.unprepare = panel_nv3051d_unprepare,
.prepare = panel_nv3051d_prepare,
.get_modes = panel_nv3051d_get_modes,
};
static int panel_nv3051d_probe(struct mipi_dsi_device *dsi)
{
struct device *dev = &dsi->dev;
struct panel_nv3051d *ctx;
int ret;
ctx = devm_drm_panel_alloc(dev, struct panel_nv3051d, panel,
&panel_nv3051d_funcs,
DRM_MODE_CONNECTOR_DSI);
if (IS_ERR(ctx))
return PTR_ERR(ctx);
ctx->dev = dev;
ctx->panel_info = of_device_get_match_data(dev);
if (!ctx->panel_info)
return -EINVAL;
ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset" , GPIOD_OUT_HIGH);
if (IS_ERR(ctx->reset_gpio)) {
dev_err(dev, "cannot get reset gpio\n" );
return PTR_ERR(ctx->reset_gpio);
}
ctx->vdd = devm_regulator_get(dev, "vdd" );
if (IS_ERR(ctx->vdd)) {
ret = PTR_ERR(ctx->vdd);
if (ret != -EPROBE_DEFER)
dev_err(dev, "Failed to request vdd regulator: %d\n" , ret);
return ret;
}
mipi_dsi_set_drvdata(dsi, ctx);
dsi->lanes = 4 ;
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->mode_flags = ctx->panel_info->mode_flags;
ret = drm_panel_of_backlight(&ctx->panel);
if (ret)
return ret;
drm_panel_add(&ctx->panel);
ret = mipi_dsi_attach(dsi);
if (ret < 0 ) {
dev_err(dev, "mipi_dsi_attach failed: %d\n" , ret);
drm_panel_remove(&ctx->panel);
return ret;
}
return 0 ;
}
static void panel_nv3051d_shutdown(struct mipi_dsi_device *dsi)
{
struct panel_nv3051d *ctx = mipi_dsi_get_drvdata(dsi);
drm_panel_unprepare(&ctx->panel);
drm_panel_disable(&ctx->panel);
}
static void panel_nv3051d_remove(struct mipi_dsi_device *dsi)
{
struct panel_nv3051d *ctx = mipi_dsi_get_drvdata(dsi);
int ret;
panel_nv3051d_shutdown(dsi);
ret = mipi_dsi_detach(dsi);
if (ret < 0 )
dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n" , ret);
drm_panel_remove(&ctx->panel);
}
static const struct drm_display_mode nv3051d_rgxx3_modes[] = {
{ /* 120hz */
.hdisplay = 640 ,
.hsync_start = 640 + 40 ,
.hsync_end = 640 + 40 + 2 ,
.htotal = 640 + 40 + 2 + 80 ,
.vdisplay = 480 ,
.vsync_start = 480 + 18 ,
.vsync_end = 480 + 18 + 2 ,
.vtotal = 480 + 18 + 2 + 28 ,
.clock = 48300 ,
.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
},
{ /* 100hz */
.hdisplay = 640 ,
.hsync_start = 640 + 40 ,
.hsync_end = 640 + 40 + 2 ,
.htotal = 640 + 40 + 2 + 80 ,
.vdisplay = 480 ,
.vsync_start = 480 + 18 ,
.vsync_end = 480 + 18 + 2 ,
.vtotal = 480 + 18 + 2 + 28 ,
.clock = 40250 ,
.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
},
{ /* 60hz */
.hdisplay = 640 ,
.hsync_start = 640 + 40 ,
.hsync_end = 640 + 40 + 2 ,
.htotal = 640 + 40 + 2 + 80 ,
.vdisplay = 480 ,
.vsync_start = 480 + 18 ,
.vsync_end = 480 + 18 + 2 ,
.vtotal = 480 + 18 + 2 + 28 ,
.clock = 24150 ,
.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
},
};
static const struct drm_display_mode nv3051d_rk2023_modes[] = {
{
.hdisplay = 640 ,
.hsync_start = 640 + 40 ,
.hsync_end = 640 + 40 + 2 ,
.htotal = 640 + 40 + 2 + 80 ,
.vdisplay = 480 ,
.vsync_start = 480 + 18 ,
.vsync_end = 480 + 18 + 2 ,
.vtotal = 480 + 18 + 2 + 4 ,
.clock = 24150 ,
.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
},
};
static const struct nv3051d_panel_info nv3051d_rg351v_info = {
.display_modes = nv3051d_rgxx3_modes,
.num_modes = ARRAY_SIZE(nv3051d_rgxx3_modes),
.width_mm = 70 ,
.height_mm = 57 ,
.bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET |
MIPI_DSI_CLOCK_NON_CONTINUOUS,
};
static const struct nv3051d_panel_info nv3051d_rg353p_info = {
.display_modes = nv3051d_rgxx3_modes,
.num_modes = ARRAY_SIZE(nv3051d_rgxx3_modes),
.width_mm = 70 ,
.height_mm = 57 ,
.bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET,
};
static const struct nv3051d_panel_info nv3051d_rk2023_info = {
.display_modes = nv3051d_rk2023_modes,
.num_modes = ARRAY_SIZE(nv3051d_rk2023_modes),
.width_mm = 70 ,
.height_mm = 57 ,
.bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET,
};
static const struct of_device_id newvision_nv3051d_of_match[] = {
{ .compatible = "anbernic,rg351v-panel" , .data = &nv3051d_rg351v_info },
{ .compatible = "anbernic,rg353p-panel" , .data = &nv3051d_rg353p_info },
{ .compatible = "powkiddy,rk2023-panel" , .data = &nv3051d_rk2023_info },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, newvision_nv3051d_of_match);
static struct mipi_dsi_driver newvision_nv3051d_driver = {
.driver = {
.name = "panel-newvision-nv3051d" ,
.of_match_table = newvision_nv3051d_of_match,
},
.probe = panel_nv3051d_probe,
.remove = panel_nv3051d_remove,
.shutdown = panel_nv3051d_shutdown,
};
module_mipi_dsi_driver(newvision_nv3051d_driver);
MODULE_AUTHOR("Chris Morgan <macromorgan@hotmail.com>" );
MODULE_DESCRIPTION("DRM driver for Newvision NV3051D based MIPI DSI panels" );
MODULE_LICENSE("GPL" );
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¤ Dauer der Verarbeitung: 0.10 Sekunden
(vorverarbeitet am 2026-06-07)
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