// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2020 Icenowy Zheng <icenowy@aosc.io> #include <linux/gpio/consumer.h>#include <linux/delay.h>#include <linux/mod_devicetable.h>#include <linux/module.h>#include <linux/regulator/consumer.h>#include <drm/drm_mipi_dsi.h>#include <drm/drm_modes.h>#include <drm/drm_panel.h>#define K101_IM2BA02_INIT_CMD_LEN 2 static const char * const regulator_names[] = {"dvdd" ,"avdd" ,"cvdd" struct k101_im2ba02 {struct drm_panel panel;struct mipi_dsi_device *dsi;struct regulator_bulk_data supplies[ARRAY_SIZE(regulator_names)];struct gpio_desc *reset;static inline struct k101_im2ba02 *panel_to_k101_im2ba02(struct drm_panel *panel)return container_of(panel, struct k101_im2ba02, panel);struct k101_im2ba02_init_cmd {static const struct k101_im2ba02_init_cmd k101_im2ba02_init_cmds[] = {/* Switch to page 0 */ 0 xE0, 0 x00 } },/* Seems to be some password */ 0 xE1, 0 x93} },0 xE2, 0 x65 } },0 xE3, 0 xF8 } },/* Lane number, 0x02 - 3 lanes, 0x03 - 4 lanes */ 0 x80, 0 x03 } },/* Sequence control */ 0 x70, 0 x02 } },0 x71, 0 x23 } },0 x72, 0 x06 } },/* Switch to page 1 */ 0 xE0, 0 x01 } },/* Set VCOM */ 0 x00, 0 x00 } },0 x01, 0 x66 } },/* Set VCOM_Reverse */ 0 x03, 0 x00 } },0 x04, 0 x25 } },/* Set Gamma Power, VG[MS][PN] */ 0 x17, 0 x00 } },0 x18, 0 x6D } },0 x19, 0 x00 } },0 x1A, 0 x00 } },0 x1B, 0 xBF } }, /* VGMN = -4.5V */ 0 x1C, 0 x00 } },/* Set Gate Power */ 0 x1F, 0 x3E } }, /* VGH_R = 15V */ 0 x20, 0 x28 } }, /* VGL_R = -11V */ 0 x21, 0 x28 } }, /* VGL_R2 = -11V */ 0 x22, 0 x0E } }, /* PA[6:4] = 0, PA[0] = 0 */ /* Set Panel */ 0 x37, 0 x09 } }, /* SS = 1, BGR = 1 */ /* Set RGBCYC */ 0 x38, 0 x04 } }, /* JDT = 100 column inversion */ 0 x39, 0 x08 } }, /* RGB_N_EQ1 */ 0 x3A, 0 x12 } }, /* RGB_N_EQ2 */ 0 x3C, 0 x78 } }, /* set EQ3 for TE_H */ 0 x3D, 0 xFF } }, /* set CHGEN_ON */ 0 x3E, 0 xFF } }, /* set CHGEN_OFF */ 0 x3F, 0 x7F } }, /* set CHGEN_OFF2 */ /* Set TCON parameter */ 0 x40, 0 x06 } }, /* RSO = 800 points */ 0 x41, 0 xA0 } }, /* LN = 1280 lines */ /* Set power voltage */ 0 x55, 0 x0F } }, /* DCDCM */ 0 x56, 0 x01 } },0 x57, 0 x69 } },0 x58, 0 x0A } },0 x59, 0 x0A } },0 x5A, 0 x45 } },0 x5B, 0 x15 } },/* Set gamma */ 0 x5D, 0 x7C } },0 x5E, 0 x65 } },0 x5F, 0 x55 } },0 x60, 0 x49 } },0 x61, 0 x44 } },0 x62, 0 x35 } },0 x63, 0 x3A } },0 x64, 0 x23 } },0 x65, 0 x3D } },0 x66, 0 x3C } },0 x67, 0 x3D } },0 x68, 0 x5D } },0 x69, 0 x4D } },0 x6A, 0 x56 } },0 x6B, 0 x48 } },0 x6C, 0 x45 } },0 x6D, 0 x38 } },0 x6E, 0 x25 } },0 x6F, 0 x00 } },0 x70, 0 x7C } },0 x71, 0 x65 } },0 x72, 0 x55 } },0 x73, 0 x49 } },0 x74, 0 x44 } },0 x75, 0 x35 } },0 x76, 0 x3A } },0 x77, 0 x23 } },0 x78, 0 x3D } },0 x79, 0 x3C } },0 x7A, 0 x3D } },0 x7B, 0 x5D } },0 x7C, 0 x4D } },0 x7D, 0 x56 } },0 x7E, 0 x48 } },0 x7F, 0 x45 } },0 x80, 0 x38 } },0 x81, 0 x25 } },0 x82, 0 x00 } },/* Switch to page 2, for GIP */ 0 xE0, 0 x02 } },0 x00, 0 x1E } },0 x01, 0 x1E } },0 x02, 0 x41 } },0 x03, 0 x41 } },0 x04, 0 x43 } },0 x05, 0 x43 } },0 x06, 0 x1F } },0 x07, 0 x1F } },0 x08, 0 x1F } },0 x09, 0 x1F } },0 x0A, 0 x1E } },0 x0B, 0 x1E } },0 x0C, 0 x1F } },0 x0D, 0 x47 } },0 x0E, 0 x47 } },0 x0F, 0 x45 } },0 x10, 0 x45 } },0 x11, 0 x4B } },0 x12, 0 x4B } },0 x13, 0 x49 } },0 x14, 0 x49 } },0 x15, 0 x1F } },0 x16, 0 x1E } },0 x17, 0 x1E } },0 x18, 0 x40 } },0 x19, 0 x40 } },0 x1A, 0 x42 } },0 x1B, 0 x42 } },0 x1C, 0 x1F } },0 x1D, 0 x1F } },0 x1E, 0 x1F } },0 x1F, 0 x1f } },0 x20, 0 x1E } },0 x21, 0 x1E } },0 x22, 0 x1f } },0 x23, 0 x46 } },0 x24, 0 x46 } },0 x25, 0 x44 } },0 x26, 0 x44 } },0 x27, 0 x4A } },0 x28, 0 x4A } },0 x29, 0 x48 } },0 x2A, 0 x48 } },0 x2B, 0 x1f } },0 x2C, 0 x1F } },0 x2D, 0 x1F } },0 x2E, 0 x42 } },0 x2F, 0 x42 } },0 x30, 0 x40 } },0 x31, 0 x40 } },0 x32, 0 x1E } },0 x33, 0 x1E } },0 x34, 0 x1F } },0 x35, 0 x1F } },0 x36, 0 x1E } },0 x37, 0 x1E } },0 x38, 0 x1F } },0 x39, 0 x48 } },0 x3A, 0 x48 } },0 x3B, 0 x4A } },0 x3C, 0 x4A } },0 x3D, 0 x44 } },0 x3E, 0 x44 } },0 x3F, 0 x46 } },0 x40, 0 x46 } },0 x41, 0 x1F } },0 x42, 0 x1F } },0 x43, 0 x1F } },0 x44, 0 x43 } },0 x45, 0 x43 } },0 x46, 0 x41 } },0 x47, 0 x41 } },0 x48, 0 x1E } },0 x49, 0 x1E } },0 x4A, 0 x1E } },0 x4B, 0 x1F } },0 x4C, 0 x1E } },0 x4D, 0 x1E } },0 x4E, 0 x1F } },0 x4F, 0 x49 } },0 x50, 0 x49 } },0 x51, 0 x4B } },0 x52, 0 x4B } },0 x53, 0 x45 } },0 x54, 0 x45 } },0 x55, 0 x47 } },0 x56, 0 x47 } },0 x57, 0 x1F } },0 x58, 0 x10 } },0 x59, 0 x00 } },0 x5A, 0 x00 } },0 x5B, 0 x30 } },0 x5C, 0 x02 } },0 x5D, 0 x40 } },0 x5E, 0 x01 } },0 x5F, 0 x02 } },0 x60, 0 x30 } },0 x61, 0 x01 } },0 x62, 0 x02 } },0 x63, 0 x6A } },0 x64, 0 x6A } },0 x65, 0 x05 } },0 x66, 0 x12 } },0 x67, 0 x74 } },0 x68, 0 x04 } },0 x69, 0 x6A } },0 x6A, 0 x6A } },0 x6B, 0 x08 } },0 x6C, 0 x00 } },0 x6D, 0 x04 } },0 x6E, 0 x04 } },0 x6F, 0 x88 } },0 x70, 0 x00 } },0 x71, 0 x00 } },0 x72, 0 x06 } },0 x73, 0 x7B } },0 x74, 0 x00 } },0 x75, 0 x07 } },0 x76, 0 x00 } },0 x77, 0 x5D } },0 x78, 0 x17 } },0 x79, 0 x1F } },0 x7A, 0 x00 } },0 x7B, 0 x00 } },0 x7C, 0 x00 } },0 x7D, 0 x03 } },0 x7E, 0 x7B } },0 xE0, 0 x04 } },0 x2B, 0 x2B } },0 x2E, 0 x44 } },0 xE0, 0 x01 } },0 x0E, 0 x01 } },0 xE0, 0 x03 } },0 x98, 0 x2F } },0 xE0, 0 x00 } },0 xE6, 0 x02 } },0 xE7, 0 x02 } },0 x11, 0 x00 } },static const struct k101_im2ba02_init_cmd timed_cmds[] = {0 x29, 0 x00 } },0 x35, 0 x00 } },static int k101_im2ba02_prepare(struct drm_panel *panel)struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);struct mipi_dsi_device *dsi = ctx->dsi;unsigned int i;int ret;if (ret)return ret;30 );1 );50 );0 );50 );1 );200 );for (i = 0 ; i < ARRAY_SIZE(k101_im2ba02_init_cmds); i++) {const struct k101_im2ba02_init_cmd *cmd = &k101_im2ba02_init_cmds[i];if (ret < 0 )goto powerdown;return 0 ;0 );50 );return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);static int k101_im2ba02_enable(struct drm_panel *panel)struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);const struct k101_im2ba02_init_cmd *cmd = &timed_cmds[1 ];int ret;150 );if (ret < 0 )return ret;50 );return mipi_dsi_dcs_write_buffer(ctx->dsi, cmd->data, K101_IM2BA02_INIT_CMD_LEN);static int k101_im2ba02_disable(struct drm_panel *panel)struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);return mipi_dsi_dcs_set_display_off(ctx->dsi);static int k101_im2ba02_unprepare(struct drm_panel *panel)struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);int ret;if (ret < 0 )"failed to set display off: %d\n" , ret);if (ret < 0 )"failed to enter sleep mode: %d\n" , ret);200 );0 );20 );return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);static const struct drm_display_mode k101_im2ba02_default_mode = {70000 ,800 ,800 + 20 ,800 + 20 + 20 ,800 + 20 + 20 + 20 ,1280 ,1280 + 16 ,1280 + 16 + 4 ,1280 + 16 + 4 + 4 ,136 ,217 ,static int k101_im2ba02_get_modes(struct drm_panel *panel,struct drm_connector *connector)struct k101_im2ba02 *ctx = panel_to_k101_im2ba02(panel);struct drm_display_mode *mode;if (!mode) {"failed to add mode %ux%u@%u\n" ,return -ENOMEM;return 1 ;static const struct drm_panel_funcs k101_im2ba02_funcs = {static int k101_im2ba02_dsi_probe(struct mipi_dsi_device *dsi)struct k101_im2ba02 *ctx;unsigned int i;int ret;struct k101_im2ba02, panel,if (IS_ERR(ctx))return PTR_ERR(ctx);for (i = 0 ; i < ARRAY_SIZE(ctx->supplies); i++)if (ret < 0 )return dev_err_probe(&dsi->dev, ret, "Couldn't get regulators\n" );"reset" , GPIOD_OUT_LOW);if (IS_ERR(ctx->reset))return dev_err_probe(&dsi->dev, PTR_ERR(ctx->reset),"Couldn't get our reset GPIO\n" );if (ret)return ret;4 ;if (ret < 0 ) {return ret;return 0 ;static void k101_im2ba02_dsi_remove(struct mipi_dsi_device *dsi)struct k101_im2ba02 *ctx = mipi_dsi_get_drvdata(dsi);static const struct of_device_id k101_im2ba02_of_match[] = {"feixin,k101-im2ba02" , },/* sentinel */ } static struct mipi_dsi_driver k101_im2ba02_driver = {"feixin-k101-im2ba02" ,"Icenowy Zheng <icenowy@aosc.io>" );"Feixin K101 IM2BA02 MIPI-DSI LCD panel" );"GPL" );
Messung V0.5 in Prozent C=94 H=97 G=95
¤ Dauer der Verarbeitung: 0.12 Sekunden
(vorverarbeitet am 2026-06-05)
¤ *© Formatika GbR, Deutschland
