// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved #include <drm/drm_managed.h>#include <drm/display/drm_dsc_helper.h>#include "dpu_kms.h" #include "dpu_hw_catalog.h" #include "dpu_hwio.h" #include "dpu_hw_mdss.h" #include "dpu_hw_dsc.h" #define DSC_CMN_MAIN_CNF 0 x00/* DPU_DSC_ENC register offsets */ #define ENC_DF_CTRL 0 x00#define ENC_GENERAL_STATUS 0 x04#define ENC_HSLICE_STATUS 0 x08#define ENC_OUT_STATUS 0 x0C#define ENC_INT_STAT 0 x10#define ENC_INT_CLR 0 x14#define ENC_INT_MASK 0 x18#define DSC_MAIN_CONF 0 x30#define DSC_PICTURE_SIZE 0 x34#define DSC_SLICE_SIZE 0 x38#define DSC_MISC_SIZE 0 x3C#define DSC_HRD_DELAYS 0 x40#define DSC_RC_SCALE 0 x44#define DSC_RC_SCALE_INC_DEC 0 x48#define DSC_RC_OFFSETS_1 0 x4C#define DSC_RC_OFFSETS_2 0 x50#define DSC_RC_OFFSETS_3 0 x54#define DSC_RC_OFFSETS_4 0 x58#define DSC_FLATNESS_QP 0 x5C#define DSC_RC_MODEL_SIZE 0 x60#define DSC_RC_CONFIG 0 x64#define DSC_RC_BUF_THRESH_0 0 x68#define DSC_RC_BUF_THRESH_1 0 x6C#define DSC_RC_BUF_THRESH_2 0 x70#define DSC_RC_BUF_THRESH_3 0 x74#define DSC_RC_MIN_QP_0 0 x78#define DSC_RC_MIN_QP_1 0 x7C#define DSC_RC_MIN_QP_2 0 x80#define DSC_RC_MAX_QP_0 0 x84#define DSC_RC_MAX_QP_1 0 x88#define DSC_RC_MAX_QP_2 0 x8C#define DSC_RC_RANGE_BPG_OFFSETS_0 0 x90#define DSC_RC_RANGE_BPG_OFFSETS_1 0 x94#define DSC_RC_RANGE_BPG_OFFSETS_2 0 x98/* DPU_DSC_CTL register offsets */ #define DSC_CTL 0 x00#define DSC_CFG 0 x04#define DSC_DATA_IN_SWAP 0 x08#define DSC_CLK_CTRL 0 x0Cstatic int _dsc_calc_output_buf_max_addr(struct dpu_hw_dsc *hw_dsc, int num_softslice)int max_addr = 2400 / num_softslice;if (hw_dsc->caps->features & BIT(DPU_DSC_NATIVE_42x_EN))2 ;return max_addr - 1 ;static void dpu_hw_dsc_disable_1_2(struct dpu_hw_dsc *hw_dsc)struct dpu_hw_blk_reg_map *hw;const struct dpu_dsc_sub_blks *sblk;if (!hw_dsc)return ;0 );0 );0 );static void dpu_hw_dsc_config_1_2(struct dpu_hw_dsc *hw_dsc,struct drm_dsc_config *dsc,struct dpu_hw_blk_reg_map *hw;const struct dpu_dsc_sub_blks *sblk;0 ;if (!hw_dsc || !dsc)return ;if (mode & DSC_MODE_SPLIT_PANEL)0 );if (mode & DSC_MODE_MULTIPLEX)1 );if (mode & DSC_MODE_MULTIPLEX)2 ;0 x3) << 7 ;0 xff);if (mode & DSC_MODE_VIDEO)9 );18 );0 xf) << 28 ;if (dsc->dsc_version_minor == 0 x2) {if (dsc->native_422)22 );if (dsc->native_420)21 );/* as per hw requirement bpp should be programmed * twice the actual value in case of 420 or 422 encoding if (dsc->native_422 || dsc->native_420)2 * bpp;10 ;if (dsc->block_pred_enable)20 );if (dsc->convert_rgb)4 );0 xf) << 6 ;0 xf;0 xffff) |0 xffff) << 16 );0 xffff) |0 xffff) << 16 );0 xffff);0 xffff) |0 xffff) << 16 );0 x3f);0 xffff) |0 x7ff) << 16 );0 x1f) |0 x1f) << 5 );0 xffff) |0 xffff) << 16 );0 xffff) |0 xffff) << 16 );0 xffff) |0 xffff) << 16 );0 x1f) |0 x1f) << 5 ) |0 xff) << 10 );0 xffff);0 xf;0 x1f) << 8 ;0 x1f) << 13 ;0 xf) << 20 ;0 xf) << 24 ;/* program the dsc wrapper */ 0 ); /* encoder enable */ if (dsc->native_422)8 );else if (dsc->native_420)9 );if (!dsc->convert_rgb)10 );if (dsc->bits_per_component == 8 )11 );if (mode & DSC_MODE_SPLIT_PANEL)12 );if (mode & DSC_MODE_MULTIPLEX)13 );if (!(mode & DSC_MODE_VIDEO))17 );static void dpu_hw_dsc_config_thresh_1_2(struct dpu_hw_dsc *hw_dsc,struct drm_dsc_config *dsc)struct dpu_hw_blk_reg_map *hw;const struct dpu_dsc_sub_blks *sblk;struct drm_dsc_rc_range_parameters *rc;if (!hw_dsc || !dsc)return ;/* * With BUF_THRESH -- 14 in total * each register contains 4 thresh values with the last register * containing only 2 thresh values 0 ] << 0 ) |1 ] << 8 ) |2 ] << 16 ) |3 ] << 24 ));4 ] << 0 ) |5 ] << 8 ) |6 ] << 16 ) |7 ] << 24 ));8 ] << 0 ) |9 ] << 8 ) |10 ] << 16 ) |11 ] << 24 ));12 ] << 0 ) |13 ] << 8 ));/* * with min/max_QP -- 5 bits * each register contains 5 min_qp or max_qp for total of 15 * * With BPG_OFFSET -- 6 bits * each register contains 5 BPG_offset for total of 15 0 ].range_min_qp << 0 ) |1 ].range_min_qp << 5 ) |2 ].range_min_qp << 10 ) |3 ].range_min_qp << 15 ) |4 ].range_min_qp << 20 ));0 ].range_max_qp << 0 ) |1 ].range_max_qp << 5 ) |2 ].range_max_qp << 10 ) |3 ].range_max_qp << 15 ) |4 ].range_max_qp << 20 ));0 ].range_bpg_offset << 0 ) |1 ].range_bpg_offset << 6 ) |2 ].range_bpg_offset << 12 ) |3 ].range_bpg_offset << 18 ) |4 ].range_bpg_offset << 24 ));5 ].range_min_qp << 0 ) |6 ].range_min_qp << 5 ) |7 ].range_min_qp << 10 ) |8 ].range_min_qp << 15 ) |9 ].range_min_qp << 20 ));5 ].range_max_qp << 0 ) |6 ].range_max_qp << 5 ) |7 ].range_max_qp << 10 ) |8 ].range_max_qp << 15 ) |9 ].range_max_qp << 20 ));5 ].range_bpg_offset << 0 ) |6 ].range_bpg_offset << 6 ) |7 ].range_bpg_offset << 12 ) |8 ].range_bpg_offset << 18 ) |9 ].range_bpg_offset << 24 ));10 ].range_min_qp << 0 ) |11 ].range_min_qp << 5 ) |12 ].range_min_qp << 10 ) |13 ].range_min_qp << 15 ) |14 ].range_min_qp << 20 ));10 ].range_max_qp << 0 ) |11 ].range_max_qp << 5 ) |12 ].range_max_qp << 10 ) |13 ].range_max_qp << 15 ) |14 ].range_max_qp << 20 ));10 ].range_bpg_offset << 0 ) |11 ].range_bpg_offset << 6 ) |12 ].range_bpg_offset << 12 ) |13 ].range_bpg_offset << 18 ) |14 ].range_bpg_offset << 24 ));static void dpu_hw_dsc_bind_pingpong_blk_1_2(struct dpu_hw_dsc *hw_dsc,const enum dpu_pingpong pp)struct dpu_hw_blk_reg_map *hw;const struct dpu_dsc_sub_blks *sblk;int mux_cfg = 0 xf; /* Disabled */ if (pp)0 x7;static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops)/** * dpu_hw_dsc_init_1_2() - initializes the v1.2 DSC hw driver object * @dev: Corresponding device for devres management * @cfg: DSC catalog entry for which driver object is required * @addr: Mapped register io address of MDP * Returns: Error code or allocated dpu_hw_dsc context struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev,const struct dpu_dsc_cfg *cfg,void __iomem *addr)struct dpu_hw_dsc *c;sizeof (*c), GFP_KERNEL);if (!c)return ERR_PTR(-ENOMEM);return c;
Messung V0.5 in Prozent C=97 H=100 G=98
¤ Dauer der Verarbeitung: 0.12 Sekunden
(vorverarbeitet am 2026-06-06)
¤ *© Formatika GbR, Deutschland
