// SPDX-License-Identifier: MIT /* * Copyright © 2019 Intel Corporation #include <linux/math.h>#include <drm/drm_print.h>#include "i915_utils.h" #include "intel_ddi.h" #include "intel_ddi_buf_trans.h" #include "intel_de.h" #include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_snps_hdmi_pll.h" #include "intel_snps_phy.h" #include "intel_snps_phy_regs.h" /** * DOC: Synopsis PHY support * * Synopsis PHYs are primarily programmed by looking up magic register values * in tables rather than calculating the necessary values at runtime. * * Of special note is that the SNPS PHYs include a dedicated port PLL, known as * an "MPLLB." The MPLLB replaces the shared DPLL functionality used on other * platforms and must be programming directly during the modeset sequence * since it is not handled by the shared DPLL framework as on other platforms. void intel_snps_phy_wait_for_calibration(struct intel_display *display)enum phy phy;0 ) {if (!intel_phy_is_snps(display, phy))continue ;/* * If calibration does not complete successfully, we'll remember * which phy was affected and skip setup of the corresponding * output later. if (intel_de_wait_for_clear(display, DG2_PHY_MISC(phy),25 ))void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder,bool enable)struct intel_display *display = to_intel_display(encoder);enum phy phy = intel_encoder_to_phy(encoder);if (!intel_encoder_is_snps(encoder))return ;2 : 3 );void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,const struct intel_crtc_state *crtc_state)struct intel_display *display = to_intel_display(encoder);const struct intel_ddi_buf_trans *trans;enum phy phy = intel_encoder_to_phy(encoder);int n_entries, ln;if (drm_WARN_ON_ONCE(display->drm, !trans))return ;for (ln = 0 ; ln < 4 ; ln++) {int level = intel_ddi_level(encoder, crtc_state, ln);0 ;/* * Basic DP link rates with 100 MHz reference clock. static const struct intel_mpllb_state dg2_dp_rbr_100 = {162000 ,3 ),4 ) |20 ) |65 ) |127 ),1 ) |2 ) |1 ) |2 ) |2 ),2 ) |226 ),1 ) |1 ) |5 ),39321 ) |3 ),static const struct intel_mpllb_state dg2_dp_hbr1_100 = {270000 ,3 ),4 ) |20 ) |65 ) |127 ),1 ) |1 ) |2 ) |3 ),2 ) |184 ),1 ) |1 ),static const struct intel_mpllb_state dg2_dp_hbr2_100 = {540000 ,3 ),4 ) |20 ) |65 ) |127 ),1 ) |2 ) |3 ),2 ) |184 ),1 ) |1 ),static const struct intel_mpllb_state dg2_dp_hbr3_100 = {810000 ,3 ),4 ) |19 ) |65 ) |127 ),1 ) |2 ),2 ) |292 ),1 ) |1 ),static const struct intel_mpllb_state dg2_dp_uhbr10_100 = {1000000 ,3 ),4 ) |21 ) |65 ) |127 ),1 ) |1 ) |8 ) |1 ) |1 ) |1 ) |1 ) |2 ),2 ) |368 ),1 ) |1 ),/* * SSC will be enabled, DP UHBR has a minimum SSC requirement. 1 ) |58982 ),76101 ),static const struct intel_mpllb_state dg2_dp_uhbr13_100 = {1350000 ,3 ),5 ) |45 ) |65 ) |127 ),1 ) |1 ) |8 ) |1 ) |1 ) |1 ) |3 ),2 ) |508 ),1 ) |1 ),/* * SSC will be enabled, DP UHBR has a minimum SSC requirement. 1 ) |79626 ),102737 ),static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {/* * eDP link rates with 100 MHz reference clock. static const struct intel_mpllb_state dg2_edp_r216 = {216000 ,3 ),4 ) |19 ) |65 ) |127 ),1 ) |2 ) |1 ) |2 ),2 ) |312 ),1 ) |1 ) |5 ),52428 ) |4 ),1 ) |50961 ),65752 ),static const struct intel_mpllb_state dg2_edp_r243 = {243000 ,3 ),4 ) |20 ) |65 ) |127 ),1 ) |2 ) |1 ) |2 ),2 ) |356 ),1 ) |1 ) |5 ),26214 ) |2 ),1 ) |57331 ),73971 ),static const struct intel_mpllb_state dg2_edp_r324 = {324000 ,3 ),4 ) |20 ) |65 ) |127 ),1 ) |1 ) |1 ) |2 ) |2 ),2 ) |226 ),1 ) |1 ) |5 ),39321 ) |3 ),1 ) |38221 ),49314 ),static const struct intel_mpllb_state dg2_edp_r432 = {432000 ,3 ),4 ) |19 ) |65 ) |127 ),1 ) |1 ) |1 ) |2 ),2 ) |312 ),1 ) |1 ) |5 ),52428 ) |4 ),1 ) |50961 ),65752 ),static const struct intel_mpllb_state * const dg2_edp_tables[] = {/* * HDMI link rates with 100 MHz reference clock. static const struct intel_mpllb_state dg2_hdmi_25_175 = {25175 ,3 ),5 ) |15 ) |64 ) |124 ),1 ) |5 ) |1 ) |2 ),1 ) |128 ) |1 ),1 ) |1 ) |143 ),36663 ) |71 ),1 ),static const struct intel_mpllb_state dg2_hdmi_27_0 = {27000 ,3 ),5 ) |15 ) |64 ) |124 ),1 ) |5 ) |1 ) |2 ),1 ) |140 ) |1 ),1 ) |1 ) |5 ),26214 ) |2 ),1 ),static const struct intel_mpllb_state dg2_hdmi_74_25 = {74250 ,3 ),4 ) |15 ) |64 ) |124 ),1 ) |3 ) |1 ) |2 ) |3 ),1 ) |86 ) |1 ),1 ) |1 ) |5 ),26214 ) |2 ),1 ),static const struct intel_mpllb_state dg2_hdmi_148_5 = {148500 ,3 ),4 ) |15 ) |64 ) |124 ),1 ) |2 ) |1 ) |2 ) |3 ),1 ) |86 ) |1 ),1 ) |1 ) |5 ),26214 ) |2 ),1 ),/* values in the below table are calculated using the algo */ static const struct intel_mpllb_state dg2_hdmi_25200 = {25200 ,3 ),7 ) |14 ) |64 ) |124 ),1 ) |5 ) |1 ) |2 ) |0 ),1 ) |128 ) |1 ),1 ) |1 ) |65535 ),41943 ) |2621 ),1 ),static const struct intel_mpllb_state dg2_hdmi_27027 = {27027 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |5 ) |1 ) |2 ) |0 ),1 ) |140 ) |1 ),1 ) |1 ) |65535 ),31876 ) |46555 ),1 ),static const struct intel_mpllb_state dg2_hdmi_28320 = {28320 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |5 ) |1 ) |2 ) |0 ),1 ) |148 ) |1 ),1 ) |1 ) |65535 ),40894 ) |30408 ),1 ),static const struct intel_mpllb_state dg2_hdmi_30240 = {30240 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |5 ) |1 ) |2 ) |0 ),1 ) |160 ) |1 ),1 ) |1 ) |65535 ),50331 ) |42466 ),1 ),static const struct intel_mpllb_state dg2_hdmi_31500 = {31500 ,3 ),7 ) |14 ) |64 ) |124 ),1 ) |4 ) |1 ) |2 ) |3 ),1 ) |68 ) |1 ),1 ) |1 ) |65535 ),26214 ) |26214 ),1 ),static const struct intel_mpllb_state dg2_hdmi_36000 = {36000 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |4 ) |1 ) |2 ) |3 ),1 ) |82 ) |1 ),1 ) |1 ) |65535 ),39321 ) |39320 ),1 ),static const struct intel_mpllb_state dg2_hdmi_40000 = {40000 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |4 ) |0 ) |2 ) |2 ),1 ) |96 ) |1 ),1 ) |0 ) |65535 ),0 ) |0 ),1 ),static const struct intel_mpllb_state dg2_hdmi_49500 = {49500 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |4 ) |1 ) |2 ) |1 ),1 ) |126 ) |1 ),1 ) |1 ) |65535 ),13107 ) |13107 ),1 ),static const struct intel_mpllb_state dg2_hdmi_50000 = {50000 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |4 ) |0 ) |2 ) |1 ),1 ) |128 ) |1 ),1 ) |0 ) |65535 ),0 ) |0 ),1 ),static const struct intel_mpllb_state dg2_hdmi_57284 = {57284 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |4 ) |1 ) |2 ) |0 ),1 ) |150 ) |1 ),1 ) |1 ) |65535 ),42886 ) |49701 ),1 ),static const struct intel_mpllb_state dg2_hdmi_58000 = {58000 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |4 ) |1 ) |2 ) |0 ),1 ) |152 ) |1 ),1 ) |1 ) |65535 ),52428 ) |52427 ),1 ),static const struct intel_mpllb_state dg2_hdmi_65000 = {65000 ,3 ),7 ) |14 ) |64 ) |124 ),1 ) |3 ) |0 ) |2 ) |3 ),1 ) |72 ) |1 ),1 ) |0 ) |65535 ),0 ) |0 ),1 ),static const struct intel_mpllb_state dg2_hdmi_71000 = {71000 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |3 ) |1 ) |2 ) |3 ),1 ) |80 ) |1 ),1 ) |1 ) |65535 ),52428 ) |52427 ),1 ),static const struct intel_mpllb_state dg2_hdmi_74176 = {74176 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |3 ) |1 ) |2 ) |3 ),1 ) |86 ) |1 ),1 ) |1 ) |65535 ),22334 ) |43829 ),1 ),static const struct intel_mpllb_state dg2_hdmi_75000 = {75000 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |3 ) |0 ) |2 ) |3 ),1 ) |88 ) |1 ),1 ) |0 ) |65535 ),0 ) |0 ),1 ),static const struct intel_mpllb_state dg2_hdmi_78750 = {78750 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |3 ) |0 ) |2 ) |2 ),1 ) |94 ) |1 ),1 ) |0 ) |65535 ),0 ) |0 ),1 ),static const struct intel_mpllb_state dg2_hdmi_85500 = {85500 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |3 ) |1 ) |2 ) |2 ),1 ) |104 ) |1 ),1 ) |1 ) |65535 ),26214 ) |26214 ),1 ),static const struct intel_mpllb_state dg2_hdmi_88750 = {88750 ,3 ),7 ) |15 ) |64 ) |124 ),1 ) |3 ) |0 ) |2 ) |1 ),1 ) |110 ) |1 ),1 ) |0 ) |65535 ),0 ) |0 ),1 ),static const struct intel_mpllb_state dg2_hdmi_106500 = {106500 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |3 ) |1 ) |2 ) |0 ),1 ) |138 ) |1 ),1 ) |1 ) |65535 ),13107 ) |13107 ),1 ),static const struct intel_mpllb_state dg2_hdmi_108000 = {108000 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |3 ) |1 ) |2 ) |0 ),1 ) |140 ) |1 ),1 ) |1 ) |65535 ),26214 ) |26214 ),1 ),static const struct intel_mpllb_state dg2_hdmi_115500 = {115500 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |3 ) |1 ) |2 ) |0 ),1 ) |152 ) |1 ),1 ) |1 ) |65535 ),26214 ) |26214 ),1 ),static const struct intel_mpllb_state dg2_hdmi_119000 = {119000 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |3 ) |1 ) |2 ) |0 ),1 ) |158 ) |1 ),1 ) |1 ) |65535 ),13107 ) |13107 ),1 ),static const struct intel_mpllb_state dg2_hdmi_135000 = {135000 ,3 ),7 ) |15 ) |64 ) |124 ),1 ) |2 ) |0 ) |2 ) |3 ),1 ) |76 ) |1 ),1 ) |0 ) |65535 ),0 ) |0 ),1 ),static const struct intel_mpllb_state dg2_hdmi_138500 = {138500 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |2 ) |1 ) |2 ) |3 ),1 ) |78 ) |1 ),1 ) |1 ) |65535 ),26214 ) |26214 ),1 ),static const struct intel_mpllb_state dg2_hdmi_147160 = {147160 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |2 ) |1 ) |2 ) |3 ),1 ) |84 ) |1 ),1 ) |1 ) |65535 ),56623 ) |6815 ),1 ),static const struct intel_mpllb_state dg2_hdmi_148352 = {148352 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |2 ) |1 ) |2 ) |3 ),1 ) |86 ) |1 ),1 ) |1 ) |65535 ),22334 ) |43829 ),1 ),static const struct intel_mpllb_state dg2_hdmi_154000 = {154000 ,3 ),6 ) |13 ) |64 ) |124 ),1 ) |2 ) |1 ) |2 ) |2 ),1 ) |90 ) |1 ),1 ) |1 ) |65535 ),39321 ) |39320 ),1 ),static const struct intel_mpllb_state dg2_hdmi_162000 = {162000 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |2 ) |1 ) |2 ) |2 ),1 ) |96 ) |1 ),1 ) |1 ) |65535 ),52428 ) |52427 ),1 ),static const struct intel_mpllb_state dg2_hdmi_209800 = {209800 ,3 ),7 ) |14 ) |64 ) |124 ),1 ) |2 ) |1 ) |2 ) |0 ),1 ) |134 ) |1 ),1 ) |1 ) |65535 ),60293 ) |7864 ),1 ),static const struct intel_mpllb_state dg2_hdmi_262750 = {262750 ,3 ),7 ) |14 ) |64 ) |124 ),1 ) |1 ) |1 ) |2 ) |3 ),1 ) |72 ) |1 ),1 ) |1 ) |65535 ),36044 ) |52427 ),1 ),static const struct intel_mpllb_state dg2_hdmi_267300 = {267300 ,3 ),7 ) |14 ) |64 ) |124 ),1 ) |1 ) |1 ) |2 ) |3 ),1 ) |74 ) |1 ),1 ) |1 ) |65535 ),30146 ) |36699 ),1 ),static const struct intel_mpllb_state dg2_hdmi_268500 = {268500 ,3 ),7 ) |14 ) |64 ) |124 ),1 ) |1 ) |1 ) |2 ) |3 ),1 ) |74 ) |1 ),1 ) |1 ) |65535 ),45875 ) |13107 ),1 ),static const struct intel_mpllb_state dg2_hdmi_296703 = {296703 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |1 ) |1 ) |2 ) |3 ),1 ) |86 ) |1 ),1 ) |1 ) |65535 ),22321 ) |36804 ),1 ),static const struct intel_mpllb_state dg2_hdmi_241500 = {241500 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |2 ) |1 ) |2 ) |0 ),1 ) |160 ) |1 ),1 ) |1 ) |65535 ),39321 ) |39320 ),1 ),static const struct intel_mpllb_state dg2_hdmi_319890 = {319890 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |1 ) |1 ) |2 ) |2 ),1 ) |94 ) |1 ),1 ) |1 ) |65535 ),64094 ) |13631 ),1 ),static const struct intel_mpllb_state dg2_hdmi_497750 = {497750 ,3 ),6 ) |15 ) |64 ) |124 ),1 ) |1 ) |1 ) |2 ) |0 ),1 ) |166 ) |1 ),1 ) |1 ) |65535 ),36044 ) |52427 ),1 ),static const struct intel_mpllb_state dg2_hdmi_592000 = {592000 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |0 ) |1 ) |2 ) |3 ),1 ) |86 ) |1 ),1 ) |1 ) |65535 ),13107 ) |13107 ),1 ),static const struct intel_mpllb_state dg2_hdmi_593407 = {593407 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |0 ) |1 ) |2 ) |3 ),1 ) |86 ) |1 ),1 ) |1 ) |65535 ),22328 ) |7549 ),1 ),static const struct intel_mpllb_state dg2_hdmi_297 = {297000 ,3 ),6 ) |14 ) |64 ) |124 ),1 ) |1 ) |1 ) |2 ) |3 ),1 ) |86 ) |1 ),1 ) |1 ) |65535 ),26214 ) |26214 ),1 ),static const struct intel_mpllb_state dg2_hdmi_594 = {594000 ,3 ),4 ) |15 ) |64 ) |124 ),1 ) |1 ) |2 ) |3 ),1 ) |86 ) |1 ),1 ) |1 ) |5 ),26214 ) |2 ),1 ),static const struct intel_mpllb_state * const dg2_hdmi_tables[] = {static const struct intel_mpllb_state * const *struct intel_crtc_state *crtc_state,struct intel_encoder *encoder)if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {return dg2_edp_tables;else if (intel_crtc_has_dp_encoder(crtc_state)) {return dg2_dp_100_tables;else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {return dg2_hdmi_tables;return NULL;int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,struct intel_encoder *encoder)const struct intel_mpllb_state * const *tables;int i;if (!tables)return -EINVAL;for (i = 0 ; tables[i]; i++) {if (crtc_state->port_clock == tables[i]->clock) {return 0 ;/* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed tables */ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {return 0 ;return -EINVAL;void intel_mpllb_enable(struct intel_encoder *encoder,const struct intel_crtc_state *crtc_state)struct intel_display *display = to_intel_display(encoder);const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb;enum phy phy = intel_encoder_to_phy(encoder);0 ));/* * 3. Software programs the following PLL registers for the desired * frequency. /* * 4. If the frequency will result in a change to the voltage * requirement, follow the Display Voltage Frequency Switching - * Sequence Before Frequency Change. * * We handle this step in bxt_set_cdclk(). /* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */ 0 , PLL_ENABLE);/* * 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This * will keep the PLL running during the DDI lane programming and any * typeC DP cable disconnect. Do not set the force before enabling the * PLL because that will start the PLL before it has sampled the * divider values. /* * 10. Software polls on register DPLL_ENABLE [PLL Lock] to confirm PLL * is locked at new settings. This register bit is sampling PHY * dp_mpllb_state interface signal. if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 5 ))"Port %c PLL not locked\n" , phy_name(phy));/* * 11. If the frequency will result in a change to the voltage * requirement, follow the Display Voltage Frequency Switching - * Sequence After Frequency Change. * * We handle this step in bxt_set_cdclk(). void intel_mpllb_disable(struct intel_encoder *encoder)struct intel_display *display = to_intel_display(encoder);enum phy phy = intel_encoder_to_phy(encoder);0 ));/* * 1. If the frequency will result in a change to the voltage * requirement, follow the Display Voltage Frequency Switching - * Sequence Before Frequency Change. * * We handle this step in bxt_set_cdclk(). /* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */ 0 );/* * 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0". * This will allow the PLL to stop running. 0 );/* * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment * (dp_txX_ack) that the new transmitter setting request is completed. if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 5 ))"Port %c PLL not locked\n" , phy_name(phy));/* * 6. If the frequency will result in a change to the voltage * requirement, follow the Display Voltage Frequency Switching - * Sequence After Frequency Change. * * We handle this step in bxt_set_cdclk(). int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,const struct intel_mpllb_state *pll_state)unsigned int frac_quot = 0 , frac_rem = 0 , frac_den = 1 ;unsigned int multiplier, tx_clk_div, refclk;bool frac_en;if (0 )38400 ;else 100000 ;1 ;if (frac_en) {2 + 16 ;return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16 ) + frac_quot) +10 << (tx_clk_div + 16 ));void intel_mpllb_readout_hw_state(struct intel_encoder *encoder,struct intel_mpllb_state *pll_state)struct intel_display *display = to_intel_display(encoder);enum phy phy = intel_encoder_to_phy(encoder);/* * REF_CONTROL is under firmware control and never programmed by the * driver; we read it only for sanity checking purposes. The bspec * only tells us the expected value for one field in this register, * so we'll only read out those specific bits here. /* * MPLLB_DIV is programmed twice, once with the software-computed * state, then again with the MPLLB_FORCE_EN bit added. Drop that * extra bit during readout so that we return the actual expected * software state. void intel_mpllb_state_verify(struct intel_atomic_state *state,struct intel_crtc *crtc)struct intel_display *display = to_intel_display(state);const struct intel_crtc_state *new_crtc_state =struct intel_mpllb_state mpllb_hw_state = {};const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->dpll_hw_state.mpllb;struct intel_encoder *encoder;if (!display->platform.dg2)return ;if (!new_crtc_state->hw.active)return ;/* intel_get_crtc_new_encoder() only works for modeset/fastset commits */ if (!intel_crtc_needs_modeset(new_crtc_state) &&return ;#define MPLLB_CHECK(__name) \"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)" , \/* * ref_control is handled by the hardware/firemware and never * programmed by the software, but the proper values are supplied * in the bspec for verification purposes. #undef MPLLB_CHECK
Messung V0.5 in Prozent C=95 H=92 G=93
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(vorverarbeitet am 2026-06-08)
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