// SPDX-License-Identifier: GPL-2.0-only /* * Chrontel CH7033 Video Encoder Driver * * Copyright (C) 2019,2020 Lubomir Rintel #include <linux/gpio/consumer.h>#include <linux/i2c.h>#include <linux/module.h>#include <linux/regmap.h>#include <drm/drm_atomic_helper.h>#include <drm/drm_bridge.h>#include <drm/drm_edid.h>#include <drm/drm_of.h>#include <drm/drm_print.h>#include <drm/drm_probe_helper.h>/* Page 0, Register 0x07 */ enum {3 ),5 ),/* Page 0, Register 0x08 */ enum {7 , 4 ),3 , 1 ),0 ),/* Page 0, Register 0x09 */ enum {7 ),6 ),5 ),4 ),3 ),2 ),1 ),0 ),/* Page 0, Register 0x0a */ enum {7 ),6 ),5 ),4 ),3 ),2 ),1 ),0 ),/* Page 0, Register 0x18 */ enum {7 , 4 ),3 ),2 , 0 ),enum {0 ,1 ,2 ,3 ,4 ,5 ,/* Page 0, Register 0x19 */ enum {5 ),4 ),3 ),2 ),2 , 0 ),/* Page 0, Register 0x2e */ enum {7 ),6 ),5 ),4 ),3 ),2 , 0 ),/* Page 0, Register 0x2b */ enum {7 , 4 ),3 , 0 ),/* Page 0, Register 0x54 */ enum {7 ),6 ),5 , 3 ),2 , 0 ),/* Page 0, Register 0x57 */ enum {7 ),5 , 3 ),2 , 0 ),/* Page 0, Register 0x7e */ enum {7 ),6 ),5 ),4 ),3 , 0 ),/* Page 1, Register 0x07 */ enum {7 ),6 ),5 ),3 ),2 ),1 ),0 ),/* Page 1, Register 0x08 */ enum {6 ),5 ),4 ),3 ),2 , 1 ),0 ),/* Page 1, Register 0x0c */ enum {7 , 6 ),5 ),4 ),3 ),2 ),1 ),0 ),/* Page 1, Register 0x6b */ enum {7 , 6 ),5 , 3 ),2 ),1 ),0 ),/* Page 1, Register 0x6c */ enum {7 , 4 ),3 ),2 ),1 ),0 ),/* Page 3, Register 0x28 */ enum {7 , 6 ),5 , 4 ),3 ),2 ),1 ),/* Page 3, Register 0x2a */ enum {7 ),6 ),5 ),4 ),3 ),2 , 0 ),/* Page 4, Register 0x52 */ enum {7 ),6 ),2 ),1 ),0 ),struct ch7033_priv {struct regmap *regmap;struct drm_bridge *next_bridge;struct drm_bridge bridge;struct drm_connector connector;#define conn_to_ch7033_priv(x) \struct ch7033_priv, connector)#define bridge_to_ch7033_priv(x) \struct ch7033_priv, bridge)static enum drm_connector_status ch7033_connector_detect(struct drm_connector *connector, bool force)struct ch7033_priv *priv = conn_to_ch7033_priv(connector);return drm_bridge_detect(priv->next_bridge, connector);static const struct drm_connector_funcs ch7033_connector_funcs = {static int ch7033_connector_get_modes(struct drm_connector *connector)struct ch7033_priv *priv = conn_to_ch7033_priv(connector);const struct drm_edid *drm_edid;int ret;if (drm_edid) {else {1920 , 1080 );1024 , 768 );return ret;static struct drm_encoder *ch7033_connector_best_encoder(struct drm_connector *connector)struct ch7033_priv *priv = conn_to_ch7033_priv(connector);return priv->bridge.encoder;static const struct drm_connector_helper_funcs ch7033_connector_helper_funcs = {static void ch7033_hpd_event(void *arg, enum drm_connector_status status)struct ch7033_priv *priv = arg;if (priv->bridge.dev)static int ch7033_bridge_attach(struct drm_bridge *bridge,struct drm_encoder *encoder,enum drm_bridge_attach_flags flags)struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);struct drm_connector *connector = &priv->connector;int ret;if (ret)return ret;if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)return 0 ;if (priv->next_bridge->ops & DRM_BRIDGE_OP_DETECT) {else {if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD) {if (ret) {"Failed to initialize connector\n" );return ret;return drm_connector_attach_encoder(&priv->connector, encoder);static void ch7033_bridge_detach(struct drm_bridge *bridge)struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD)static enum drm_mode_status ch7033_bridge_mode_valid(struct drm_bridge *bridge,const struct drm_display_info *info,const struct drm_display_mode *mode)if (mode->clock > 165000 )return MODE_CLOCK_HIGH;if (mode->hdisplay >= 1920 )return MODE_BAD_HVALUE;if (mode->vdisplay >= 1080 )return MODE_BAD_VVALUE;return MODE_OK;static void ch7033_bridge_disable(struct drm_bridge *bridge)struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);0 x03, 0 x04);0 x52, RESETDB, 0 x00);static void ch7033_bridge_enable(struct drm_bridge *bridge)struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);0 x03, 0 x04);0 x52, RESETDB, RESETDB);static void ch7033_bridge_mode_set(struct drm_bridge *bridge,const struct drm_display_mode *mode,const struct drm_display_mode *adjusted_mode)struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);int hbporch = mode->hsync_start - mode->hdisplay;int hsynclen = mode->hsync_end - mode->hsync_start;int vbporch = mode->vsync_start - mode->vdisplay;int vsynclen = mode->vsync_end - mode->vsync_start;/* * Page 4 0 x03, 0 x04);/* Turn everything off to set all the registers to their defaults. */ 0 x52, 0 x00);/* Bring I/O block up. */ 0 x52, RESETIB);/* * Page 0 0 x03, 0 x00);/* Bring up parts we need from the power down. */ 0 x07, DRI_PD | IO_PD, 0 );0 x08, DRI_PDDRI | PDDAC | PANEN, 0 );0 x09, DPD | GCKOFF |0 );0 x0a, HD_DVIB, 0 );/* Horizontal input timing. */ 0 x0b, (mode->htotal >> 8 ) << 3 |8 ));0 x0c, mode->hdisplay);0 x0d, mode->htotal);0 x0e, (hsynclen >> 8 ) << 3 |8 ));0 x0f, hbporch);0 x10, hsynclen);/* Vertical input timing. */ 0 x11, (mode->vtotal >> 8 ) << 3 |8 ));0 x12, mode->vdisplay);0 x13, mode->vtotal);0 x14, ((vsynclen >> 8 ) << 3 ) |8 ));0 x15, vbporch);0 x16, vsynclen);/* Input color swap. */ 0 x18, SWAP, BYTE_SWAP_BGR);/* Input clock and sync polarity. */ 0 x19, 0 x1, mode->clock >> 16 );0 x19, HPO_I | VPO_I | GCLKFREQ,0 |0 |16 );0 x1a, mode->clock >> 8 );0 x1b, mode->clock);/* Horizontal output timing. */ 0 x1f, (mode->htotal >> 8 ) << 3 |8 ));0 x20, mode->hdisplay);0 x21, mode->htotal);/* Vertical output timing. */ 0 x25, (mode->vtotal >> 8 ) << 3 |8 ));0 x26, mode->vdisplay);0 x27, mode->vtotal);/* VGA channel bypass */ 0 x2b, VFMT, 9 );/* Output sync polarity. */ 0 x2e, HPO_O | VPO_O,0 |0 );/* HDMI horizontal output timing. */ 0 x54, HWO_HDMI_HI | HOO_HDMI_HI,8 ) << 3 |8 ));0 x55, hbporch);0 x56, hsynclen);/* HDMI vertical output timing. */ 0 x57, VWO_HDMI_HI | VOO_HDMI_HI,8 ) << 3 |8 ));0 x58, vbporch);0 x59, vsynclen);/* Pick HDMI, not LVDS. */ 0 x7e, HDMI_LVDS_SEL, HDMI_LVDS_SEL);/* * Page 1 0 x03, 0 x01);/* No idea what these do, but VGA is wobbly and blinky without them. */ 0 x07, CKINV, CKINV);0 x08, DISPON, DISPON);/* DRI PLL */ 0 x0c, DRI_PLL_DIVSEL, DRI_PLL_DIVSEL);if (mode->clock <= 40000 ) {0 x0c, DRI_PLL_N1_1 |0 );else if (mode->clock < 80000 ) {0 x0c, DRI_PLL_N1_1 |else {0 x0c, DRI_PLL_N1_1 |/* This seems to be color calibration for VGA. */ 0 x64, 0 x29); /* LSB Blue */ 0 x65, 0 x29); /* LSB Green */ 0 x66, 0 x29); /* LSB Red */ 0 x67, 0 x00); /* MSB Blue */ 0 x68, 0 x00); /* MSB Green */ 0 x69, 0 x00); /* MSB Red */ 0 x6b, DRI_PD_SER, 0 x00);0 x6c, DRI_PLL_PD, 0 x00);/* * Page 3 0 x03, 0 x03);/* More bypasses and apparently another HDMI/LVDS selector. */ 0 x28, VGACLK_BP | HM_LV_SEL,0 x2a, HDMICLK_BP | HDMI_BP,/* * Page 4 0 x03, 0 x04);/* Output clock. */ 0 x10, mode->clock >> 16 );0 x11, mode->clock >> 8 );0 x12, mode->clock);static const struct drm_bridge_funcs ch7033_bridge_funcs = {static const struct regmap_config ch7033_regmap_config = {8 ,8 ,0 x7f,static int ch7033_probe(struct i2c_client *client)struct device *dev = &client->dev;struct ch7033_priv *priv;unsigned int val;int ret;struct ch7033_priv, bridge,if (IS_ERR(priv))return PTR_ERR(priv);1 , -1 , NULL,if (ret)return ret;if (IS_ERR(priv->regmap)) {"regmap init failed\n" );return PTR_ERR(priv->regmap);0 x00, &val);if (ret < 0 ) {"error reading the model id: %d\n" , ret);return ret;if ((val & 0 xf7) != 0 x56) {"the device is not a ch7033\n" );return -ENODEV;0 x03, 0 x04);0 x51, &val);if (ret < 0 ) {"error reading the model id: %d\n" , ret);return ret;if ((val & 0 x0f) != 3 ) {"unknown revision %u\n" , val);return -ENODEV;"Chrontel CH7033 Video Encoder\n" );return 0 ;static void ch7033_remove(struct i2c_client *client)struct device *dev = &client->dev;struct ch7033_priv *priv = dev_get_drvdata(dev);static const struct of_device_id ch7033_dt_ids[] = {"chrontel,ch7033" , },static const struct i2c_device_id ch7033_ids[] = {"ch7033" },static struct i2c_driver ch7033_driver = {"ch7033" ,"Lubomir Rintel <lkundrak@v3.sk>" );"Chrontel CH7033 Video Encoder Driver" );"GPL v2" );
Messung V0.5 in Prozent C=96 H=95 G=95
¤ Dauer der Verarbeitung: 0.11 Sekunden
(vorverarbeitet am 2026-06-08)
¤ *© Formatika GbR, Deutschland
