/* * Copyright 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * #ifndef _FIJI_PP_SMC_H_#define _FIJI_PP_SMC_H_#pragma pack (push, 1 )#define PPSMC_SWSTATE_FLAG_DC 0 x01#define PPSMC_SWSTATE_FLAG_UVD 0 x02#define PPSMC_SWSTATE_FLAG_VCE 0 x04#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0 x00#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0 x01#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0 xff#define PPSMC_SYSTEMFLAG_GPIO_DC 0 x01#define PPSMC_SYSTEMFLAG_STEPVDDC 0 x02#define PPSMC_SYSTEMFLAG_GDDR5 0 x04#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0 x08#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0 x10#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0 x20#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0 x07#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0 x08#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0 x00#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0 x01/* Defines for DPM 2.0 */ #define PPSMC_DPM2FLAGS_TDPCLMP 0 x01#define PPSMC_DPM2FLAGS_PWRSHFT 0 x02#define PPSMC_DPM2FLAGS_OCP 0 x04/* Defines for display watermark level */ #define PPSMC_DISPLAY_WATERMARK_LOW 0 #define PPSMC_DISPLAY_WATERMARK_HIGH 1 /* In the HW performance level's state flags: */ #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0 x01#define PPSMC_STATEFLAG_POWERBOOST 0 x02#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0 x04#define PPSMC_STATEFLAG_POWERSHIFT 0 x08#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0 x10#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0 x20#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0 x40/* Fan control algorithm: */ #define FDO_MODE_HARDWARE 0 #define FDO_MODE_PIECE_WISE_LINEAR 1 enum FAN_CONTROL {/* Gemini Modes*/ #define PPSMC_GeminiModeNone 0 /*Single GPU board*/ #define PPSMC_GeminiModeMaster 1 /*Master GPU on a Gemini board*/ #define PPSMC_GeminiModeSlave 2 /*Slave GPU on a Gemini board*/ /* Return codes for driver to SMC communication. */ #define PPSMC_Result_OK ((uint16_t)0 x01)#define PPSMC_Result_NoMore ((uint16_t)0 x02)#define PPSMC_Result_NotNow ((uint16_t)0 x03)#define PPSMC_Result_Failed ((uint16_t)0 xFF)#define PPSMC_Result_UnknownCmd ((uint16_t)0 xFE)#define PPSMC_Result_UnknownVT ((uint16_t)0 xFD)#define PPSMC_isERROR(x) ((uint16_t)0 x80 & (x))#define PPSMC_MSG_Halt ((uint16_t)0 x10)#define PPSMC_MSG_Resume ((uint16_t)0 x11)#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0 x12)#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0 x13)#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0 x14)#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0 x15)#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0 x16)#define PPSMC_MSG_RunningOnAC ((uint16_t)0 x17)#define PPSMC_MSG_LevelUp ((uint16_t)0 x18)#define PPSMC_MSG_LevelDown ((uint16_t)0 x19)#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0 x1a)#define PPSMC_MSG_SwitchToSwState ((uint16_t)0 x20)#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0 x3f)#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0 x40)#define PPSMC_MSG_NoForcedLevel ((uint16_t)0 x41)#define PPSMC_MSG_ForceHigh ((uint16_t)0 x42)#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0 x43)#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0 x51)#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0 x52)#define PPSMC_MSG_EnableCac ((uint16_t)0 x53)#define PPSMC_MSG_DisableCac ((uint16_t)0 x54)#define PPSMC_DPMStateHistoryStart ((uint16_t)0 x55)#define PPSMC_DPMStateHistoryStop ((uint16_t)0 x56)#define PPSMC_CACHistoryStart ((uint16_t)0 x57)#define PPSMC_CACHistoryStop ((uint16_t)0 x58)#define PPSMC_TDPClampingActive ((uint16_t)0 x59)#define PPSMC_TDPClampingInactive ((uint16_t)0 x5A)#define PPSMC_StartFanControl ((uint16_t)0 x5B)#define PPSMC_StopFanControl ((uint16_t)0 x5C)#define PPSMC_NoDisplay ((uint16_t)0 x5D)#define PPSMC_HasDisplay ((uint16_t)0 x5E)#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0 x60)#define PPSMC_MSG_UVDPowerON ((uint16_t)0 x61)#define PPSMC_MSG_EnableULV ((uint16_t)0 x62)#define PPSMC_MSG_DisableULV ((uint16_t)0 x63)#define PPSMC_MSG_EnterULV ((uint16_t)0 x64)#define PPSMC_MSG_ExitULV ((uint16_t)0 x65)#define PPSMC_PowerShiftActive ((uint16_t)0 x6A)#define PPSMC_PowerShiftInactive ((uint16_t)0 x6B)#define PPSMC_OCPActive ((uint16_t)0 x6C)#define PPSMC_OCPInactive ((uint16_t)0 x6D)#define PPSMC_CACLongTermAvgEnable ((uint16_t)0 x6E)#define PPSMC_CACLongTermAvgDisable ((uint16_t)0 x6F)#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0 x70)#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0 x71)#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0 x72)#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0 x73)#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0 x74)#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0 x75)#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0 x76)#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0 x77)#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0 x78)#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0 x79)#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0 x7A)#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0 x7B)#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0 x7C)#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0 x7D)#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0 x7E)#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0 x7F)#define PPSMC_FlushDataCache ((uint16_t)0 x80)#define PPSMC_FlushInstrCache ((uint16_t)0 x81)#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0 x82)#define PPSMC_MSG_SetForcedLevels ((uint16_t)0 x83)#define PPSMC_MSG_ResetToDefaults ((uint16_t)0 x84)#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0 x85)#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0 x86)#define PPSMC_MSG_EnableDTE ((uint16_t)0 x87)#define PPSMC_MSG_DisableDTE ((uint16_t)0 x88)#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0 x89)#define PPSMC_MSG_BREAK ((uint16_t)0 xF8)/* Trinity Specific Messages*/ #define PPSMC_MSG_Test ((uint16_t) 0 x100)#define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0 x101)#define PPSMC_MSG_DPM_Config ((uint16_t) 0 x102)#define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0 x103)#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0 x104)#define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0 x105)#define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0 x106)#define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0 x107)#define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0 x108)#define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0 x109)#define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0 x10a)#define PPSMC_MSG_Reset_Service ((uint16_t) 0 x10b)#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0 x10e)#define PPSMC_MSG_VCEPowerON ((uint16_t) 0 x10f)#define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0 x110)#define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0 x111)#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0 x112)#define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0 x113)#define PPSMC_MSG_DCEPowerON ((uint16_t) 0 x114)#define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0 x117)#define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0 x118)#define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0 x119)#define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0 x11a)#define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0 x11b)#define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0 x11c)#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0 x11d)#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0 x11e)#define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0 x11f)#define PPSMC_MSG_EnableBAPM ((uint16_t) 0 x120)#define PPSMC_MSG_DisableBAPM ((uint16_t) 0 x121)#define PPSMC_MSG_Spmi_Enable ((uint16_t) 0 x122)#define PPSMC_MSG_Spmi_Timer ((uint16_t) 0 x123)#define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0 x124)#define PPSMC_MSG_VddNB_Request ((uint16_t) 0 x125)#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0 x126)#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint32_t) 0 x127)#define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0 x128)#define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0 x129)#define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0 x12A)#define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0 x12B)#define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0 x12C)#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0 x12D)#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0 x12E)#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0 x12F)#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0 x130)#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0 x131)#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0 x132)#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0 x133)#define PPSMC_MSG_SetTDPLimit ((uint16_t) 0 x134)#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0 x135)#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0 x136)#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0 x137)#define PPSMC_MSG_ACPPowerON ((uint16_t) 0 x138)#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0 x139)#define PPSMC_MSG_SAMPowerON ((uint16_t) 0 x13a)#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0 x13b)#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0 x13c)#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0 x13d)#define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0 x13e)#define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0 x13f)#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0 x140)#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0 x141)#define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0 x142)#define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0 x143)#define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0 x144)#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0 x145)#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0 x146)#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0 x147)#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0 x148)#define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0 x149)#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0 x14a)#define PPSMC_MSG_SwitchToAC ((uint16_t) 0 x14b)#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0 x14c)#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0 x14d)#define PPSMC_MSG_DPM_Enable ((uint16_t) 0 x14e)#define PPSMC_MSG_DPM_Disable ((uint16_t) 0 x14f)#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t) 0 x150)#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t) 0 x151)#define PPSMC_MSG_LCLKDPM_Enable ((uint16_t) 0 x152)#define PPSMC_MSG_LCLKDPM_Disable ((uint16_t) 0 x153)#define PPSMC_MSG_UVDDPM_Enable ((uint16_t) 0 x154)#define PPSMC_MSG_UVDDPM_Disable ((uint16_t) 0 x155)#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t) 0 x156)#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t) 0 x157)#define PPSMC_MSG_ACPDPM_Enable ((uint16_t) 0 x158)#define PPSMC_MSG_ACPDPM_Disable ((uint16_t) 0 x159)#define PPSMC_MSG_VCEDPM_Enable ((uint16_t) 0 x15a)#define PPSMC_MSG_VCEDPM_Disable ((uint16_t) 0 x15b)#define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t) 0 x15c)#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0 x15d)#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0 x15e)#define PPSMC_MSG_VddC_Request ((uint16_t) 0 x15f)#define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0 x160)#define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0 x161)#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0 x162)#define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0 x163)#define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0 x164)#define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0 x165)#define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0 x166)#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0 x167)#define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0 x168)#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0 x169)#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0 x16a)#define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0 x16b)#define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t) 0 x16c)#define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t) 0 x16d)#define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t) 0 x16e)#define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t) 0 x16f)#define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0 x170)#define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0 x171)#define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0 x172)#define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0 x173)#define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0 x174)#define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0 x175)#define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0 x176)#define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0 x177)#define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0 x178)#define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0 x179)#define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0 x17a)#define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0 x17b)#define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0 x17c)#define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0 x17d)#define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0 x17e)#define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0 x17f)#define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0 x180)#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0 x181)#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0 x182)#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0 x184)#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0 x185)#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0 x186)#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0 x187)#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0 x188)#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0 x189)#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0 x18A)#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0 x18B)#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0 x18C)#define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0 x18D)#define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0 x18E)#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0 x18F)#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0 x190)#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0 x191)#define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0 x192)#define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0 x193)#define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0 x194)#define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0 x195)#define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0 x207)#define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0 x196)#define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0 x208)#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0 x197)#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0 x198)#define PPSMC_MSG_SetTjMax ((uint16_t) 0 x199)#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0 x19A)#define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0 x19B)#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0 x19C)#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0 x19D)#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0 x200)#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0 x201)#define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0 x202)#define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0 x203)#define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0 x204)#define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0 x205)#define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0 x206)#define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0 x209)#define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0 x20A)#define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0 x240)#define PPSMC_MSG_BACO_Cancel ((uint16_t) 0 x241)#define PPSMC_MSG_EnableVddGfx ((uint16_t) 0 x242)#define PPSMC_MSG_DisableVddGfx ((uint16_t) 0 x243)#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0 x244)#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0 x245)#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0 x246)#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0 x250)#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0 x251)#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0 x252)#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0 x253)#define PPSMC_MSG_LoadUcodes ((uint16_t) 0 x254)#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0 x255)#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0 x256)#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0 x257)#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0 x258)#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0 x259)#define PPSMC_MSG_LoadVBios ((uint16_t) 0 x25A)#define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0 x25B)#define DMCUSMC_MSG_PSREntry ((uint16_t) 0 x25C)#define DMCUSMC_MSG_PSRExit ((uint16_t) 0 x25D)#define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0 x260)#define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0 x261)#define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0 x262)#define PPSMC_MSG_LoadMetaData ((uint16_t) 0 x263)#define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0 x264)#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0 x265)#define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0 x266)#define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0 x267)#define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0 x268)#define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0 x269)#define PPSMC_MSG_EnableAvfs ((uint16_t) 0 x26A)#define PPSMC_MSG_DisableAvfs ((uint16_t) 0 x26B)#define PPSMC_MSG_PerformBtc ((uint16_t) 0 x26C)#define PPSMC_MSG_GetHbmCode ((uint16_t) 0 x26D)#define PPSMC_MSG_GetVrVddcTemperature ((uint16_t) 0 x26E)#define PPSMC_MSG_GetVrMvddTemperature ((uint16_t) 0 x26F)#define PPSMC_MSG_GetLiquidTemperature ((uint16_t) 0 x270)#define PPSMC_MSG_GetPlxTemperature ((uint16_t) 0 x271)#define PPSMC_MSG_RequestI2CControl ((uint16_t) 0 x272)#define PPSMC_MSG_ReleaseI2CControl ((uint16_t) 0 x273)#define PPSMC_MSG_LedConfig ((uint16_t) 0 x274)#define PPSMC_MSG_SetHbmFanCode ((uint16_t) 0 x275)#define PPSMC_MSG_SetHbmThrottleCode ((uint16_t) 0 x276)#define PPSMC_MSG_GetEnabledPsm ((uint16_t) 0 x400)#define PPSMC_MSG_AgmStartPsm ((uint16_t) 0 x401)#define PPSMC_MSG_AgmReadPsm ((uint16_t) 0 x402)#define PPSMC_MSG_AgmResetPsm ((uint16_t) 0 x403)#define PPSMC_MSG_ReadVftCell ((uint16_t) 0 x404)/* AVFS Only - Remove Later */ #define PPSMC_MSG_VftTableIsValid ((uint16_t) 0 x666)/* If the SMC firmware has an event status soft register this is what the individual bits mean.*/ #define PPSMC_EVENT_STATUS_THERMAL 0 x00000001#define PPSMC_EVENT_STATUS_REGULATORHOT 0 x00000002#define PPSMC_EVENT_STATUS_DC 0 x00000004typedef uint16_t PPSMC_Msg;#pragma pack (pop)#endif
Messung V0.5 in Prozent C=96 H=93 G=94
¤ Dauer der Verarbeitung: 0.11 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
