/*
* GFX_8_1 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef GFX_8_1_D_H
#define GFX_8_1_D_H
#define mmCB_BLEND_RED 0 xa105
#define mmCB_BLEND_GREEN 0 xa106
#define mmCB_BLEND_BLUE 0 xa107
#define mmCB_BLEND_ALPHA 0 xa108
#define mmCB_DCC_CONTROL 0 xa109
#define mmCB_COLOR_CONTROL 0 xa202
#define mmCB_BLEND0_CONTROL 0 xa1e0
#define mmCB_BLEND1_CONTROL 0 xa1e1
#define mmCB_BLEND2_CONTROL 0 xa1e2
#define mmCB_BLEND3_CONTROL 0 xa1e3
#define mmCB_BLEND4_CONTROL 0 xa1e4
#define mmCB_BLEND5_CONTROL 0 xa1e5
#define mmCB_BLEND6_CONTROL 0 xa1e6
#define mmCB_BLEND7_CONTROL 0 xa1e7
#define mmCB_COLOR0_BASE 0 xa318
#define mmCB_COLOR1_BASE 0 xa327
#define mmCB_COLOR2_BASE 0 xa336
#define mmCB_COLOR3_BASE 0 xa345
#define mmCB_COLOR4_BASE 0 xa354
#define mmCB_COLOR5_BASE 0 xa363
#define mmCB_COLOR6_BASE 0 xa372
#define mmCB_COLOR7_BASE 0 xa381
#define mmCB_COLOR0_PITCH 0 xa319
#define mmCB_COLOR1_PITCH 0 xa328
#define mmCB_COLOR2_PITCH 0 xa337
#define mmCB_COLOR3_PITCH 0 xa346
#define mmCB_COLOR4_PITCH 0 xa355
#define mmCB_COLOR5_PITCH 0 xa364
#define mmCB_COLOR6_PITCH 0 xa373
#define mmCB_COLOR7_PITCH 0 xa382
#define mmCB_COLOR0_SLICE 0 xa31a
#define mmCB_COLOR1_SLICE 0 xa329
#define mmCB_COLOR2_SLICE 0 xa338
#define mmCB_COLOR3_SLICE 0 xa347
#define mmCB_COLOR4_SLICE 0 xa356
#define mmCB_COLOR5_SLICE 0 xa365
#define mmCB_COLOR6_SLICE 0 xa374
#define mmCB_COLOR7_SLICE 0 xa383
#define mmCB_COLOR0_VIEW 0 xa31b
#define mmCB_COLOR1_VIEW 0 xa32a
#define mmCB_COLOR2_VIEW 0 xa339
#define mmCB_COLOR3_VIEW 0 xa348
#define mmCB_COLOR4_VIEW 0 xa357
#define mmCB_COLOR5_VIEW 0 xa366
#define mmCB_COLOR6_VIEW 0 xa375
#define mmCB_COLOR7_VIEW 0 xa384
#define mmCB_COLOR0_INFO 0 xa31c
#define mmCB_COLOR1_INFO 0 xa32b
#define mmCB_COLOR2_INFO 0 xa33a
#define mmCB_COLOR3_INFO 0 xa349
#define mmCB_COLOR4_INFO 0 xa358
#define mmCB_COLOR5_INFO 0 xa367
#define mmCB_COLOR6_INFO 0 xa376
#define mmCB_COLOR7_INFO 0 xa385
#define mmCB_COLOR0_ATTRIB 0 xa31d
#define mmCB_COLOR1_ATTRIB 0 xa32c
#define mmCB_COLOR2_ATTRIB 0 xa33b
#define mmCB_COLOR3_ATTRIB 0 xa34a
#define mmCB_COLOR4_ATTRIB 0 xa359
#define mmCB_COLOR5_ATTRIB 0 xa368
#define mmCB_COLOR6_ATTRIB 0 xa377
#define mmCB_COLOR7_ATTRIB 0 xa386
#define mmCB_COLOR0_DCC_CONTROL 0 xa31e
#define mmCB_COLOR1_DCC_CONTROL 0 xa32d
#define mmCB_COLOR2_DCC_CONTROL 0 xa33c
#define mmCB_COLOR3_DCC_CONTROL 0 xa34b
#define mmCB_COLOR4_DCC_CONTROL 0 xa35a
#define mmCB_COLOR5_DCC_CONTROL 0 xa369
#define mmCB_COLOR6_DCC_CONTROL 0 xa378
#define mmCB_COLOR7_DCC_CONTROL 0 xa387
#define mmCB_COLOR0_CMASK 0 xa31f
#define mmCB_COLOR1_CMASK 0 xa32e
#define mmCB_COLOR2_CMASK 0 xa33d
#define mmCB_COLOR3_CMASK 0 xa34c
#define mmCB_COLOR4_CMASK 0 xa35b
#define mmCB_COLOR5_CMASK 0 xa36a
#define mmCB_COLOR6_CMASK 0 xa379
#define mmCB_COLOR7_CMASK 0 xa388
#define mmCB_COLOR0_CMASK_SLICE 0 xa320
#define mmCB_COLOR1_CMASK_SLICE 0 xa32f
#define mmCB_COLOR2_CMASK_SLICE 0 xa33e
#define mmCB_COLOR3_CMASK_SLICE 0 xa34d
#define mmCB_COLOR4_CMASK_SLICE 0 xa35c
#define mmCB_COLOR5_CMASK_SLICE 0 xa36b
#define mmCB_COLOR6_CMASK_SLICE 0 xa37a
#define mmCB_COLOR7_CMASK_SLICE 0 xa389
#define mmCB_COLOR0_FMASK 0 xa321
#define mmCB_COLOR1_FMASK 0 xa330
#define mmCB_COLOR2_FMASK 0 xa33f
#define mmCB_COLOR3_FMASK 0 xa34e
#define mmCB_COLOR4_FMASK 0 xa35d
#define mmCB_COLOR5_FMASK 0 xa36c
#define mmCB_COLOR6_FMASK 0 xa37b
#define mmCB_COLOR7_FMASK 0 xa38a
#define mmCB_COLOR0_FMASK_SLICE 0 xa322
#define mmCB_COLOR1_FMASK_SLICE 0 xa331
#define mmCB_COLOR2_FMASK_SLICE 0 xa340
#define mmCB_COLOR3_FMASK_SLICE 0 xa34f
#define mmCB_COLOR4_FMASK_SLICE 0 xa35e
#define mmCB_COLOR5_FMASK_SLICE 0 xa36d
#define mmCB_COLOR6_FMASK_SLICE 0 xa37c
#define mmCB_COLOR7_FMASK_SLICE 0 xa38b
#define mmCB_COLOR0_CLEAR_WORD0 0 xa323
#define mmCB_COLOR1_CLEAR_WORD0 0 xa332
#define mmCB_COLOR2_CLEAR_WORD0 0 xa341
#define mmCB_COLOR3_CLEAR_WORD0 0 xa350
#define mmCB_COLOR4_CLEAR_WORD0 0 xa35f
#define mmCB_COLOR5_CLEAR_WORD0 0 xa36e
#define mmCB_COLOR6_CLEAR_WORD0 0 xa37d
#define mmCB_COLOR7_CLEAR_WORD0 0 xa38c
#define mmCB_COLOR0_CLEAR_WORD1 0 xa324
#define mmCB_COLOR1_CLEAR_WORD1 0 xa333
#define mmCB_COLOR2_CLEAR_WORD1 0 xa342
#define mmCB_COLOR3_CLEAR_WORD1 0 xa351
#define mmCB_COLOR4_CLEAR_WORD1 0 xa360
#define mmCB_COLOR5_CLEAR_WORD1 0 xa36f
#define mmCB_COLOR6_CLEAR_WORD1 0 xa37e
#define mmCB_COLOR7_CLEAR_WORD1 0 xa38d
#define mmCB_COLOR0_DCC_BASE 0 xa325
#define mmCB_COLOR1_DCC_BASE 0 xa334
#define mmCB_COLOR2_DCC_BASE 0 xa343
#define mmCB_COLOR3_DCC_BASE 0 xa352
#define mmCB_COLOR4_DCC_BASE 0 xa361
#define mmCB_COLOR5_DCC_BASE 0 xa370
#define mmCB_COLOR6_DCC_BASE 0 xa37f
#define mmCB_COLOR7_DCC_BASE 0 xa38e
#define mmCB_TARGET_MASK 0 xa08e
#define mmCB_SHADER_MASK 0 xa08f
#define mmCB_HW_CONTROL 0 x2684
#define mmCB_HW_CONTROL_1 0 x2685
#define mmCB_HW_CONTROL_2 0 x2686
#define mmCB_HW_CONTROL_3 0 x2683
#define mmCB_DCC_CONFIG 0 x2687
#define mmCB_PERFCOUNTER_FILTER 0 xdc00
#define mmCB_PERFCOUNTER0_SELECT 0 xdc01
#define mmCB_PERFCOUNTER0_SELECT1 0 xdc02
#define mmCB_PERFCOUNTER1_SELECT 0 xdc03
#define mmCB_PERFCOUNTER2_SELECT 0 xdc04
#define mmCB_PERFCOUNTER3_SELECT 0 xdc05
#define mmCB_PERFCOUNTER0_LO 0 xd406
#define mmCB_PERFCOUNTER1_LO 0 xd408
#define mmCB_PERFCOUNTER2_LO 0 xd40a
#define mmCB_PERFCOUNTER3_LO 0 xd40c
#define mmCB_PERFCOUNTER0_HI 0 xd407
#define mmCB_PERFCOUNTER1_HI 0 xd409
#define mmCB_PERFCOUNTER2_HI 0 xd40b
#define mmCB_PERFCOUNTER3_HI 0 xd40d
#define mmCB_CGTT_SCLK_CTRL 0 xf0a8
#define mmCB_DEBUG_BUS_1 0 x2699
#define mmCB_DEBUG_BUS_2 0 x269a
#define mmCB_DEBUG_BUS_3 0 x269b
#define mmCB_DEBUG_BUS_4 0 x269c
#define mmCB_DEBUG_BUS_5 0 x269d
#define mmCB_DEBUG_BUS_6 0 x269e
#define mmCB_DEBUG_BUS_7 0 x269f
#define mmCB_DEBUG_BUS_8 0 x26a0
#define mmCB_DEBUG_BUS_9 0 x26a1
#define mmCB_DEBUG_BUS_10 0 x26a2
#define mmCB_DEBUG_BUS_11 0 x26a3
#define mmCB_DEBUG_BUS_12 0 x26a4
#define mmCB_DEBUG_BUS_13 0 x26a5
#define mmCB_DEBUG_BUS_14 0 x26a6
#define mmCB_DEBUG_BUS_15 0 x26a7
#define mmCB_DEBUG_BUS_16 0 x26a8
#define mmCB_DEBUG_BUS_17 0 x26a9
#define mmCB_DEBUG_BUS_18 0 x26aa
#define mmCB_DEBUG_BUS_19 0 x26ab
#define mmCB_DEBUG_BUS_20 0 x26ac
#define mmCB_DEBUG_BUS_21 0 x26ad
#define mmCB_DEBUG_BUS_22 0 x26ae
#define mmCP_DFY_CNTL 0 x3020
#define mmCP_DFY_STAT 0 x3021
#define mmCP_DFY_ADDR_HI 0 x3022
#define mmCP_DFY_ADDR_LO 0 x3023
#define mmCP_DFY_DATA_0 0 x3024
#define mmCP_DFY_DATA_1 0 x3025
#define mmCP_DFY_DATA_2 0 x3026
#define mmCP_DFY_DATA_3 0 x3027
#define mmCP_DFY_DATA_4 0 x3028
#define mmCP_DFY_DATA_5 0 x3029
#define mmCP_DFY_DATA_6 0 x302a
#define mmCP_DFY_DATA_7 0 x302b
#define mmCP_DFY_DATA_8 0 x302c
#define mmCP_DFY_DATA_9 0 x302d
#define mmCP_DFY_DATA_10 0 x302e
#define mmCP_DFY_DATA_11 0 x302f
#define mmCP_DFY_DATA_12 0 x3030
#define mmCP_DFY_DATA_13 0 x3031
#define mmCP_DFY_DATA_14 0 x3032
#define mmCP_DFY_DATA_15 0 x3033
#define mmCP_DFY_CMD 0 x3034
#define mmCP_CPC_MGCG_SYNC_CNTL 0 x3036
#define mmCP_ATCL1_CNTL 0 x303c
#define mmCP_RB0_BASE 0 x3040
#define mmCP_RB0_BASE_HI 0 x30b1
#define mmCP_RB_BASE 0 x3040
#define mmCP_RB1_BASE 0 x3060
#define mmCP_RB1_BASE_HI 0 x30b2
#define mmCP_RB2_BASE 0 x3065
#define mmCP_RB0_CNTL 0 x3041
#define mmCP_RB_CNTL 0 x3041
#define mmCP_RB1_CNTL 0 x3061
#define mmCP_RB2_CNTL 0 x3066
#define mmCP_RB_RPTR_WR 0 x3042
#define mmCP_RB0_RPTR_ADDR 0 x3043
#define mmCP_RB_RPTR_ADDR 0 x3043
#define mmCP_RB1_RPTR_ADDR 0 x3062
#define mmCP_RB2_RPTR_ADDR 0 x3067
#define mmCP_RB0_RPTR_ADDR_HI 0 x3044
#define mmCP_RB_RPTR_ADDR_HI 0 x3044
#define mmCP_RB1_RPTR_ADDR_HI 0 x3063
#define mmCP_RB2_RPTR_ADDR_HI 0 x3068
#define mmCP_RB0_WPTR 0 x3045
#define mmCP_RB_WPTR 0 x3045
#define mmCP_RB1_WPTR 0 x3064
#define mmCP_RB2_WPTR 0 x3069
#define mmCP_RB_WPTR_POLL_ADDR_LO 0 x3046
#define mmCP_RB_WPTR_POLL_ADDR_HI 0 x3047
#define mmGC_PRIV_MODE 0 x3048
#define mmCP_INT_CNTL 0 x3049
#define mmCP_INT_CNTL_RING0 0 x306a
#define mmCP_INT_CNTL_RING1 0 x306b
#define mmCP_INT_CNTL_RING2 0 x306c
#define mmCP_INT_STATUS 0 x304a
#define mmCP_INT_STATUS_RING0 0 x306d
#define mmCP_INT_STATUS_RING1 0 x306e
#define mmCP_INT_STATUS_RING2 0 x306f
#define mmCP_DEVICE_ID 0 x304b
#define mmCP_RING_PRIORITY_CNTS 0 x304c
#define mmCP_ME0_PIPE_PRIORITY_CNTS 0 x304c
#define mmCP_RING0_PRIORITY 0 x304d
#define mmCP_ME0_PIPE0_PRIORITY 0 x304d
#define mmCP_RING1_PRIORITY 0 x304e
#define mmCP_ME0_PIPE1_PRIORITY 0 x304e
#define mmCP_RING2_PRIORITY 0 x304f
#define mmCP_ME0_PIPE2_PRIORITY 0 x304f
#define mmCP_ENDIAN_SWAP 0 x3050
#define mmCP_RB_VMID 0 x3051
#define mmCP_ME0_PIPE0_VMID 0 x3052
#define mmCP_ME0_PIPE1_VMID 0 x3053
#define mmCP_RB_DOORBELL_CONTROL 0 x3059
#define mmCP_RB_DOORBELL_RANGE_LOWER 0 x305a
#define mmCP_RB_DOORBELL_RANGE_UPPER 0 x305b
#define mmCP_MEC_DOORBELL_RANGE_LOWER 0 x305c
#define mmCP_MEC_DOORBELL_RANGE_UPPER 0 x305d
#define mmCP_PFP_UCODE_ADDR 0 xf814
#define mmCP_PFP_UCODE_DATA 0 xf815
#define mmCP_ME_RAM_RADDR 0 xf816
#define mmCP_ME_RAM_WADDR 0 xf816
#define mmCP_ME_RAM_DATA 0 xf817
#define mmCGTT_CPC_CLK_CTRL 0 xf0b2
#define mmCGTT_CPF_CLK_CTRL 0 xf0b1
#define mmCGTT_CP_CLK_CTRL 0 xf0b0
#define mmCP_CE_UCODE_ADDR 0 xf818
#define mmCP_CE_UCODE_DATA 0 xf819
#define mmCP_MEC_ME1_UCODE_ADDR 0 xf81a
#define mmCP_MEC_ME1_UCODE_DATA 0 xf81b
#define mmCP_MEC_ME2_UCODE_ADDR 0 xf81c
#define mmCP_MEC_ME2_UCODE_DATA 0 xf81d
#define mmCP_MEC1_F32_INT_DIS 0 x30bd
#define mmCP_MEC2_F32_INT_DIS 0 x30be
#define mmCP_PWR_CNTL 0 x3078
#define mmCP_MEM_SLP_CNTL 0 x3079
#define mmCP_ECC_FIRSTOCCURRENCE 0 x307a
#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0 x307b
#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0 x307c
#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0 x307d
#define mmCP_CPF_DEBUG 0 x3080
#define mmCP_PQ_WPTR_POLL_CNTL 0 x3083
#define mmCP_PQ_WPTR_POLL_CNTL1 0 x3084
#define mmCPC_INT_CNTL 0 x30b4
#define mmCP_ME1_PIPE0_INT_CNTL 0 x3085
#define mmCP_ME1_PIPE1_INT_CNTL 0 x3086
#define mmCP_ME1_PIPE2_INT_CNTL 0 x3087
#define mmCP_ME1_PIPE3_INT_CNTL 0 x3088
#define mmCP_ME2_PIPE0_INT_CNTL 0 x3089
#define mmCP_ME2_PIPE1_INT_CNTL 0 x308a
#define mmCP_ME2_PIPE2_INT_CNTL 0 x308b
#define mmCP_ME2_PIPE3_INT_CNTL 0 x308c
#define mmCPC_INT_STATUS 0 x30b5
#define mmCP_ME1_PIPE0_INT_STATUS 0 x308d
#define mmCP_ME1_PIPE1_INT_STATUS 0 x308e
#define mmCP_ME1_PIPE2_INT_STATUS 0 x308f
#define mmCP_ME1_PIPE3_INT_STATUS 0 x3090
#define mmCP_ME2_PIPE0_INT_STATUS 0 x3091
#define mmCP_ME2_PIPE1_INT_STATUS 0 x3092
#define mmCP_ME2_PIPE2_INT_STATUS 0 x3093
#define mmCP_ME2_PIPE3_INT_STATUS 0 x3094
#define mmCP_ME1_INT_STAT_DEBUG 0 x3095
#define mmCP_ME2_INT_STAT_DEBUG 0 x3096
#define mmCP_ME1_PIPE_PRIORITY_CNTS 0 x3099
#define mmCP_ME1_PIPE0_PRIORITY 0 x309a
#define mmCP_ME1_PIPE1_PRIORITY 0 x309b
#define mmCP_ME1_PIPE2_PRIORITY 0 x309c
#define mmCP_ME1_PIPE3_PRIORITY 0 x309d
#define mmCP_ME2_PIPE_PRIORITY_CNTS 0 x309e
#define mmCP_ME2_PIPE0_PRIORITY 0 x309f
#define mmCP_ME2_PIPE1_PRIORITY 0 x30a0
#define mmCP_ME2_PIPE2_PRIORITY 0 x30a1
#define mmCP_ME2_PIPE3_PRIORITY 0 x30a2
#define mmCP_CE_PRGRM_CNTR_START 0 x30a3
#define mmCP_PFP_PRGRM_CNTR_START 0 x30a4
#define mmCP_ME_PRGRM_CNTR_START 0 x30a5
#define mmCP_MEC1_PRGRM_CNTR_START 0 x30a6
#define mmCP_MEC2_PRGRM_CNTR_START 0 x30a7
#define mmCP_CE_INTR_ROUTINE_START 0 x30a8
#define mmCP_PFP_INTR_ROUTINE_START 0 x30a9
#define mmCP_ME_INTR_ROUTINE_START 0 x30aa
#define mmCP_MEC1_INTR_ROUTINE_START 0 x30ab
#define mmCP_MEC2_INTR_ROUTINE_START 0 x30ac
#define mmCP_CONTEXT_CNTL 0 x30ad
#define mmCP_MAX_CONTEXT 0 x30ae
#define mmCP_IQ_WAIT_TIME1 0 x30af
#define mmCP_IQ_WAIT_TIME2 0 x30b0
#define mmCP_VMID_RESET 0 x30b3
#define mmCP_VMID_PREEMPT 0 x30b6
#define mmCP_VMID_STATUS 0 x30bf
#define mmCPC_INT_CNTX_ID 0 x30b7
#define mmCP_PQ_STATUS 0 x30b8
#define mmCP_CPC_IC_BASE_LO 0 x30b9
#define mmCP_CPC_IC_BASE_HI 0 x30ba
#define mmCP_CPC_IC_BASE_CNTL 0 x30bb
#define mmCP_CPC_IC_OP_CNTL 0 x30bc
#define mmCP_CPC_STATUS 0 x2084
#define mmCP_CPC_BUSY_STAT 0 x2085
#define mmCP_CPC_STALLED_STAT1 0 x2086
#define mmCP_CPF_STATUS 0 x2087
#define mmCP_CPF_BUSY_STAT 0 x2088
#define mmCP_CPF_STALLED_STAT1 0 x2089
#define mmCP_CPC_GRBM_FREE_COUNT 0 x208b
#define mmCP_MEC_CNTL 0 x208d
#define mmCP_MEC_ME1_HEADER_DUMP 0 x208e
#define mmCP_MEC_ME2_HEADER_DUMP 0 x208f
#define mmCP_CPC_SCRATCH_INDEX 0 x2090
#define mmCP_CPC_SCRATCH_DATA 0 x2091
#define mmCPG_PERFCOUNTER1_SELECT 0 xd800
#define mmCPG_PERFCOUNTER1_LO 0 xd000
#define mmCPG_PERFCOUNTER1_HI 0 xd001
#define mmCPG_PERFCOUNTER0_SELECT1 0 xd801
#define mmCPG_PERFCOUNTER0_SELECT 0 xd802
#define mmCPG_PERFCOUNTER0_LO 0 xd002
#define mmCPG_PERFCOUNTER0_HI 0 xd003
#define mmCPC_PERFCOUNTER1_SELECT 0 xd803
#define mmCPC_PERFCOUNTER1_LO 0 xd004
#define mmCPC_PERFCOUNTER1_HI 0 xd005
#define mmCPC_PERFCOUNTER0_SELECT1 0 xd804
#define mmCPC_PERFCOUNTER0_SELECT 0 xd809
#define mmCPC_PERFCOUNTER0_LO 0 xd006
#define mmCPC_PERFCOUNTER0_HI 0 xd007
#define mmCPF_PERFCOUNTER1_SELECT 0 xd805
#define mmCPF_PERFCOUNTER1_LO 0 xd008
#define mmCPF_PERFCOUNTER1_HI 0 xd009
#define mmCPF_PERFCOUNTER0_SELECT1 0 xd806
#define mmCPF_PERFCOUNTER0_SELECT 0 xd807
#define mmCPF_PERFCOUNTER0_LO 0 xd00a
#define mmCPF_PERFCOUNTER0_HI 0 xd00b
#define mmCP_CPC_HALT_HYST_COUNT 0 x20a7
#define mmCP_DRAW_OBJECT 0 xd810
#define mmCP_DRAW_OBJECT_COUNTER 0 xd811
#define mmCP_DRAW_WINDOW_MASK_HI 0 xd812
#define mmCP_DRAW_WINDOW_HI 0 xd813
#define mmCP_DRAW_WINDOW_LO 0 xd814
#define mmCP_DRAW_WINDOW_CNTL 0 xd815
#define mmCP_PRT_LOD_STATS_CNTL0 0 x20ad
#define mmCP_PRT_LOD_STATS_CNTL1 0 x20ae
#define mmCP_PRT_LOD_STATS_CNTL2 0 x20af
#define mmCP_CE_COMPARE_COUNT 0 x20c0
#define mmCP_CE_DE_COUNT 0 x20c1
#define mmCP_DE_CE_COUNT 0 x20c2
#define mmCP_DE_LAST_INVAL_COUNT 0 x20c3
#define mmCP_DE_DE_COUNT 0 x20c4
#define mmCP_EOP_DONE_EVENT_CNTL 0 xc0d5
#define mmCP_EOP_DONE_DATA_CNTL 0 xc0d6
#define mmCP_EOP_DONE_CNTX_ID 0 xc0d7
#define mmCP_EOP_DONE_ADDR_LO 0 xc000
#define mmCP_EOP_DONE_ADDR_HI 0 xc001
#define mmCP_EOP_DONE_DATA_LO 0 xc002
#define mmCP_EOP_DONE_DATA_HI 0 xc003
#define mmCP_EOP_LAST_FENCE_LO 0 xc004
#define mmCP_EOP_LAST_FENCE_HI 0 xc005
#define mmCP_STREAM_OUT_ADDR_LO 0 xc006
#define mmCP_STREAM_OUT_ADDR_HI 0 xc007
#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0 xc008
#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0 xc009
#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0 xc00a
#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0 xc00b
#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0 xc00c
#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0 xc00d
#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0 xc00e
#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0 xc00f
#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0 xc010
#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0 xc011
#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0 xc012
#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0 xc013
#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0 xc014
#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0 xc015
#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0 xc016
#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0 xc017
#define mmCP_PIPE_STATS_ADDR_LO 0 xc018
#define mmCP_PIPE_STATS_ADDR_HI 0 xc019
#define mmCP_VGT_IAVERT_COUNT_LO 0 xc01a
#define mmCP_VGT_IAVERT_COUNT_HI 0 xc01b
#define mmCP_VGT_IAPRIM_COUNT_LO 0 xc01c
#define mmCP_VGT_IAPRIM_COUNT_HI 0 xc01d
#define mmCP_VGT_GSPRIM_COUNT_LO 0 xc01e
#define mmCP_VGT_GSPRIM_COUNT_HI 0 xc01f
#define mmCP_VGT_VSINVOC_COUNT_LO 0 xc020
#define mmCP_VGT_VSINVOC_COUNT_HI 0 xc021
#define mmCP_VGT_GSINVOC_COUNT_LO 0 xc022
#define mmCP_VGT_GSINVOC_COUNT_HI 0 xc023
#define mmCP_VGT_HSINVOC_COUNT_LO 0 xc024
#define mmCP_VGT_HSINVOC_COUNT_HI 0 xc025
#define mmCP_VGT_DSINVOC_COUNT_LO 0 xc026
#define mmCP_VGT_DSINVOC_COUNT_HI 0 xc027
#define mmCP_PA_CINVOC_COUNT_LO 0 xc028
#define mmCP_PA_CINVOC_COUNT_HI 0 xc029
#define mmCP_PA_CPRIM_COUNT_LO 0 xc02a
#define mmCP_PA_CPRIM_COUNT_HI 0 xc02b
#define mmCP_SC_PSINVOC_COUNT0_LO 0 xc02c
#define mmCP_SC_PSINVOC_COUNT0_HI 0 xc02d
#define mmCP_SC_PSINVOC_COUNT1_LO 0 xc02e
#define mmCP_SC_PSINVOC_COUNT1_HI 0 xc02f
#define mmCP_VGT_CSINVOC_COUNT_LO 0 xc030
#define mmCP_VGT_CSINVOC_COUNT_HI 0 xc031
#define mmCP_PIPE_STATS_CONTROL 0 xc03d
#define mmCP_STREAM_OUT_CONTROL 0 xc03e
#define mmCP_STRMOUT_CNTL 0 xc03f
#define mmSCRATCH_REG0 0 xc040
#define mmSCRATCH_REG1 0 xc041
#define mmSCRATCH_REG2 0 xc042
#define mmSCRATCH_REG3 0 xc043
#define mmSCRATCH_REG4 0 xc044
#define mmSCRATCH_REG5 0 xc045
#define mmSCRATCH_REG6 0 xc046
#define mmSCRATCH_REG7 0 xc047
#define mmSCRATCH_UMSK 0 xc050
#define mmSCRATCH_ADDR 0 xc051
#define mmCP_PFP_ATOMIC_PREOP_LO 0 xc052
#define mmCP_PFP_ATOMIC_PREOP_HI 0 xc053
#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0 xc054
#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0 xc055
#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0 xc056
#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0 xc057
#define mmCP_APPEND_ADDR_LO 0 xc058
#define mmCP_APPEND_ADDR_HI 0 xc059
#define mmCP_APPEND_DATA 0 xc05a
#define mmCP_APPEND_LAST_CS_FENCE 0 xc05b
#define mmCP_APPEND_LAST_PS_FENCE 0 xc05c
#define mmCP_ATOMIC_PREOP_LO 0 xc05d
#define mmCP_ME_ATOMIC_PREOP_LO 0 xc05d
#define mmCP_ATOMIC_PREOP_HI 0 xc05e
#define mmCP_ME_ATOMIC_PREOP_HI 0 xc05e
#define mmCP_GDS_ATOMIC0_PREOP_LO 0 xc05f
#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0 xc05f
#define mmCP_GDS_ATOMIC0_PREOP_HI 0 xc060
#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0 xc060
#define mmCP_GDS_ATOMIC1_PREOP_LO 0 xc061
#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0 xc061
#define mmCP_GDS_ATOMIC1_PREOP_HI 0 xc062
#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0 xc062
#define mmCP_ME_MC_WADDR_LO 0 xc069
#define mmCP_ME_MC_WADDR_HI 0 xc06a
#define mmCP_ME_MC_WDATA_LO 0 xc06b
#define mmCP_ME_MC_WDATA_HI 0 xc06c
#define mmCP_ME_MC_RADDR_LO 0 xc06d
#define mmCP_ME_MC_RADDR_HI 0 xc06e
#define mmCP_SEM_WAIT_TIMER 0 xc06f
#define mmCP_SIG_SEM_ADDR_LO 0 xc070
#define mmCP_SIG_SEM_ADDR_HI 0 xc071
#define mmCP_WAIT_SEM_ADDR_LO 0 xc075
#define mmCP_WAIT_SEM_ADDR_HI 0 xc076
#define mmCP_WAIT_REG_MEM_TIMEOUT 0 xc074
#define mmCP_COHER_START_DELAY 0 xc07b
#define mmCP_COHER_CNTL 0 xc07c
#define mmCP_COHER_SIZE 0 xc07d
#define mmCP_COHER_SIZE_HI 0 xc08c
#define mmCP_COHER_BASE 0 xc07e
#define mmCP_COHER_BASE_HI 0 xc079
#define mmCP_COHER_STATUS 0 xc07f
#define mmCOHER_DEST_BASE_0 0 xa092
#define mmCOHER_DEST_BASE_1 0 xa093
#define mmCOHER_DEST_BASE_2 0 xa07e
#define mmCOHER_DEST_BASE_3 0 xa07f
#define mmCOHER_DEST_BASE_HI_0 0 xa07a
#define mmCOHER_DEST_BASE_HI_1 0 xa07b
#define mmCOHER_DEST_BASE_HI_2 0 xa07c
#define mmCOHER_DEST_BASE_HI_3 0 xa07d
#define mmCP_DMA_ME_SRC_ADDR 0 xc080
#define mmCP_DMA_ME_SRC_ADDR_HI 0 xc081
#define mmCP_DMA_ME_DST_ADDR 0 xc082
#define mmCP_DMA_ME_DST_ADDR_HI 0 xc083
#define mmCP_DMA_ME_CONTROL 0 xc078
#define mmCP_DMA_ME_COMMAND 0 xc084
#define mmCP_DMA_PFP_SRC_ADDR 0 xc085
#define mmCP_DMA_PFP_SRC_ADDR_HI 0 xc086
#define mmCP_DMA_PFP_DST_ADDR 0 xc087
#define mmCP_DMA_PFP_DST_ADDR_HI 0 xc088
#define mmCP_DMA_PFP_CONTROL 0 xc077
#define mmCP_DMA_PFP_COMMAND 0 xc089
#define mmCP_DMA_CNTL 0 xc08a
#define mmCP_DMA_READ_TAGS 0 xc08b
#define mmCP_PFP_IB_CONTROL 0 xc08d
#define mmCP_PFP_LOAD_CONTROL 0 xc08e
#define mmCP_SCRATCH_INDEX 0 xc08f
#define mmCP_SCRATCH_DATA 0 xc090
#define mmCP_RB_OFFSET 0 xc091
#define mmCP_IB1_OFFSET 0 xc092
#define mmCP_IB2_OFFSET 0 xc093
#define mmCP_IB1_PREAMBLE_BEGIN 0 xc094
#define mmCP_IB1_PREAMBLE_END 0 xc095
#define mmCP_IB2_PREAMBLE_BEGIN 0 xc096
#define mmCP_IB2_PREAMBLE_END 0 xc097
#define mmCP_CE_IB1_OFFSET 0 xc098
#define mmCP_CE_IB2_OFFSET 0 xc099
#define mmCP_CE_COUNTER 0 xc09a
#define mmCP_CE_RB_OFFSET 0 xc09b
#define mmCP_PFP_COMPLETION_STATUS 0 xc0ec
#define mmCP_CE_COMPLETION_STATUS 0 xc0ed
#define mmCP_PRED_NOT_VISIBLE 0 xc0ee
#define mmCP_PFP_METADATA_BASE_ADDR 0 xc0f0
#define mmCP_PFP_METADATA_BASE_ADDR_HI 0 xc0f1
#define mmCP_CE_METADATA_BASE_ADDR 0 xc0f2
#define mmCP_CE_METADATA_BASE_ADDR_HI 0 xc0f3
#define mmCP_DRAW_INDX_INDR_ADDR 0 xc0f4
#define mmCP_DRAW_INDX_INDR_ADDR_HI 0 xc0f5
#define mmCP_DISPATCH_INDR_ADDR 0 xc0f6
#define mmCP_DISPATCH_INDR_ADDR_HI 0 xc0f7
#define mmCP_INDEX_BASE_ADDR 0 xc0f8
#define mmCP_INDEX_BASE_ADDR_HI 0 xc0f9
#define mmCP_INDEX_TYPE 0 xc0fa
#define mmCP_GDS_BKUP_ADDR 0 xc0fb
#define mmCP_GDS_BKUP_ADDR_HI 0 xc0fc
#define mmCP_SAMPLE_STATUS 0 xc0fd
#define mmCP_STALLED_STAT1 0 x219d
#define mmCP_STALLED_STAT2 0 x219e
#define mmCP_STALLED_STAT3 0 x219c
#define mmCP_BUSY_STAT 0 x219f
#define mmCP_STAT 0 x21a0
#define mmCP_ME_HEADER_DUMP 0 x21a1
#define mmCP_PFP_HEADER_DUMP 0 x21a2
#define mmCP_GRBM_FREE_COUNT 0 x21a3
#define mmCP_CE_HEADER_DUMP 0 x21a4
#define mmCP_CSF_STAT 0 x21b4
#define mmCP_CSF_CNTL 0 x21b5
#define mmCP_ME_CNTL 0 x21b6
#define mmCP_CNTX_STAT 0 x21b8
#define mmCP_ME_PREEMPTION 0 x21b9
#define mmCP_RB0_RPTR 0 x21c0
#define mmCP_RB_RPTR 0 x21c0
#define mmCP_RB1_RPTR 0 x21bf
#define mmCP_RB2_RPTR 0 x21be
#define mmCP_RB_WPTR_DELAY 0 x21c1
#define mmCP_RB_WPTR_POLL_CNTL 0 x21c2
#define mmCP_CE_INIT_BASE_LO 0 xc0c3
#define mmCP_CE_INIT_BASE_HI 0 xc0c4
#define mmCP_CE_INIT_BUFSZ 0 xc0c5
#define mmCP_CE_IB1_BASE_LO 0 xc0c6
#define mmCP_CE_IB1_BASE_HI 0 xc0c7
#define mmCP_CE_IB1_BUFSZ 0 xc0c8
#define mmCP_CE_IB2_BASE_LO 0 xc0c9
#define mmCP_CE_IB2_BASE_HI 0 xc0ca
#define mmCP_CE_IB2_BUFSZ 0 xc0cb
#define mmCP_IB1_BASE_LO 0 xc0cc
#define mmCP_IB1_BASE_HI 0 xc0cd
#define mmCP_IB1_BUFSZ 0 xc0ce
#define mmCP_IB2_BASE_LO 0 xc0cf
#define mmCP_IB2_BASE_HI 0 xc0d0
#define mmCP_IB2_BUFSZ 0 xc0d1
#define mmCP_ST_BASE_LO 0 xc0d2
#define mmCP_ST_BASE_HI 0 xc0d3
#define mmCP_ST_BUFSZ 0 xc0d4
#define mmCP_ROQ_THRESHOLDS 0 x21bc
#define mmCP_MEQ_STQ_THRESHOLD 0 x21bd
#define mmCP_ROQ1_THRESHOLDS 0 x21d5
#define mmCP_ROQ2_THRESHOLDS 0 x21d6
#define mmCP_STQ_THRESHOLDS 0 x21d7
#define mmCP_QUEUE_THRESHOLDS 0 x21d8
#define mmCP_MEQ_THRESHOLDS 0 x21d9
#define mmCP_ROQ_AVAIL 0 x21da
#define mmCP_STQ_AVAIL 0 x21db
#define mmCP_ROQ2_AVAIL 0 x21dc
#define mmCP_MEQ_AVAIL 0 x21dd
#define mmCP_CMD_INDEX 0 x21de
#define mmCP_CMD_DATA 0 x21df
#define mmCP_ROQ_RB_STAT 0 x21e0
#define mmCP_ROQ_IB1_STAT 0 x21e1
#define mmCP_ROQ_IB2_STAT 0 x21e2
#define mmCP_STQ_STAT 0 x21e3
#define mmCP_STQ_WR_STAT 0 x21e4
#define mmCP_MEQ_STAT 0 x21e5
#define mmCP_CEQ1_AVAIL 0 x21e6
#define mmCP_CEQ2_AVAIL 0 x21e7
#define mmCP_CE_ROQ_RB_STAT 0 x21e8
#define mmCP_CE_ROQ_IB1_STAT 0 x21e9
#define mmCP_CE_ROQ_IB2_STAT 0 x21ea
#define mmCP_INT_STAT_DEBUG 0 x21f7
#define mmCP_PERFMON_CNTL 0 xd808
#define mmCP_PERFMON_CNTX_CNTL 0 xa0d8
#define mmCP_RINGID 0 xa0d9
#define mmCP_PIPEID 0 xa0d9
#define mmCP_VMID 0 xa0da
#define mmCP_HPD_ROQ_OFFSETS 0 x3240
#define mmCP_HPD_STATUS0 0 x3241
#define mmCP_MQD_BASE_ADDR 0 x3245
#define mmCP_MQD_BASE_ADDR_HI 0 x3246
#define mmCP_HQD_ACTIVE 0 x3247
#define mmCP_HQD_VMID 0 x3248
#define mmCP_HQD_PERSISTENT_STATE 0 x3249
#define mmCP_HQD_PIPE_PRIORITY 0 x324a
#define mmCP_HQD_QUEUE_PRIORITY 0 x324b
#define mmCP_HQD_QUANTUM 0 x324c
#define mmCP_HQD_PQ_BASE 0 x324d
#define mmCP_HQD_PQ_BASE_HI 0 x324e
#define mmCP_HQD_PQ_RPTR 0 x324f
#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0 x3250
#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0 x3251
#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0 x3252
#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0 x3253
#define mmCP_HQD_PQ_DOORBELL_CONTROL 0 x3254
#define mmCP_HQD_PQ_WPTR 0 x3255
#define mmCP_HQD_PQ_CONTROL 0 x3256
#define mmCP_HQD_IB_BASE_ADDR 0 x3257
#define mmCP_HQD_IB_BASE_ADDR_HI 0 x3258
#define mmCP_HQD_IB_RPTR 0 x3259
#define mmCP_HQD_IB_CONTROL 0 x325a
#define mmCP_HQD_IQ_TIMER 0 x325b
#define mmCP_HQD_IQ_RPTR 0 x325c
#define mmCP_HQD_DEQUEUE_REQUEST 0 x325d
#define mmCP_HQD_DMA_OFFLOAD 0 x325e
#define mmCP_HQD_OFFLOAD 0 x325e
#define mmCP_HQD_SEMA_CMD 0 x325f
#define mmCP_HQD_MSG_TYPE 0 x3260
#define mmCP_HQD_ATOMIC0_PREOP_LO 0 x3261
#define mmCP_HQD_ATOMIC0_PREOP_HI 0 x3262
#define mmCP_HQD_ATOMIC1_PREOP_LO 0 x3263
#define mmCP_HQD_ATOMIC1_PREOP_HI 0 x3264
#define mmCP_HQD_HQ_SCHEDULER0 0 x3265
#define mmCP_HQD_HQ_STATUS0 0 x3265
#define mmCP_HQD_HQ_SCHEDULER1 0 x3266
#define mmCP_HQD_HQ_CONTROL0 0 x3266
#define mmCP_MQD_CONTROL 0 x3267
#define mmCP_HQD_HQ_STATUS1 0 x3268
#define mmCP_HQD_HQ_CONTROL1 0 x3269
#define mmCP_HQD_EOP_BASE_ADDR 0 x326a
#define mmCP_HQD_EOP_BASE_ADDR_HI 0 x326b
#define mmCP_HQD_EOP_CONTROL 0 x326c
#define mmCP_HQD_EOP_RPTR 0 x326d
#define mmCP_HQD_EOP_WPTR 0 x326e
#define mmCP_HQD_EOP_EVENTS 0 x326f
#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0 x3270
#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0 x3271
#define mmCP_HQD_CTX_SAVE_CONTROL 0 x3272
#define mmCP_HQD_CNTL_STACK_OFFSET 0 x3273
#define mmCP_HQD_CNTL_STACK_SIZE 0 x3274
#define mmCP_HQD_WG_STATE_OFFSET 0 x3275
#define mmCP_HQD_CTX_SAVE_SIZE 0 x3276
#define mmCP_HQD_GDS_RESOURCE_STATE 0 x3277
#define mmCP_HQD_ERROR 0 x3278
#define mmCP_HQD_EOP_WPTR_MEM 0 x3279
#define mmCP_HQD_EOP_DONES 0 x327a
#define mmDB_Z_READ_BASE 0 xa012
#define mmDB_STENCIL_READ_BASE 0 xa013
#define mmDB_Z_WRITE_BASE 0 xa014
#define mmDB_STENCIL_WRITE_BASE 0 xa015
#define mmDB_DEPTH_INFO 0 xa00f
#define mmDB_Z_INFO 0 xa010
#define mmDB_STENCIL_INFO 0 xa011
#define mmDB_DEPTH_SIZE 0 xa016
#define mmDB_DEPTH_SLICE 0 xa017
#define mmDB_DEPTH_VIEW 0 xa002
#define mmDB_RENDER_CONTROL 0 xa000
#define mmDB_COUNT_CONTROL 0 xa001
#define mmDB_RENDER_OVERRIDE 0 xa003
#define mmDB_RENDER_OVERRIDE2 0 xa004
#define mmDB_EQAA 0 xa201
#define mmDB_SHADER_CONTROL 0 xa203
#define mmDB_DEPTH_BOUNDS_MIN 0 xa008
#define mmDB_DEPTH_BOUNDS_MAX 0 xa009
#define mmDB_STENCIL_CLEAR 0 xa00a
#define mmDB_DEPTH_CLEAR 0 xa00b
#define mmDB_HTILE_DATA_BASE 0 xa005
#define mmDB_HTILE_SURFACE 0 xa2af
#define mmDB_PRELOAD_CONTROL 0 xa2b2
#define mmDB_STENCILREFMASK 0 xa10c
#define mmDB_STENCILREFMASK_BF 0 xa10d
#define mmDB_SRESULTS_COMPARE_STATE0 0 xa2b0
#define mmDB_SRESULTS_COMPARE_STATE1 0 xa2b1
#define mmDB_DEPTH_CONTROL 0 xa200
#define mmDB_STENCIL_CONTROL 0 xa10b
#define mmDB_ALPHA_TO_MASK 0 xa2dc
#define mmDB_PERFCOUNTER0_SELECT 0 xdc40
#define mmDB_PERFCOUNTER1_SELECT 0 xdc42
#define mmDB_PERFCOUNTER2_SELECT 0 xdc44
#define mmDB_PERFCOUNTER3_SELECT 0 xdc46
#define mmDB_PERFCOUNTER0_SELECT1 0 xdc41
#define mmDB_PERFCOUNTER1_SELECT1 0 xdc43
#define mmDB_PERFCOUNTER0_LO 0 xd440
#define mmDB_PERFCOUNTER1_LO 0 xd442
#define mmDB_PERFCOUNTER2_LO 0 xd444
#define mmDB_PERFCOUNTER3_LO 0 xd446
#define mmDB_PERFCOUNTER0_HI 0 xd441
#define mmDB_PERFCOUNTER1_HI 0 xd443
#define mmDB_PERFCOUNTER2_HI 0 xd445
#define mmDB_PERFCOUNTER3_HI 0 xd447
#define mmDB_DEBUG 0 x260c
#define mmDB_DEBUG2 0 x260d
#define mmDB_DEBUG3 0 x260e
#define mmDB_DEBUG4 0 x260f
#define mmDB_CREDIT_LIMIT 0 x2614
#define mmDB_WATERMARKS 0 x2615
#define mmDB_SUBTILE_CONTROL 0 x2616
#define mmDB_FREE_CACHELINES 0 x2617
#define mmDB_FIFO_DEPTH1 0 x2618
#define mmDB_FIFO_DEPTH2 0 x2619
#define mmDB_CGTT_CLK_CTRL_0 0 xf0a4
#define mmDB_ZPASS_COUNT_LOW 0 xc3fe
#define mmDB_ZPASS_COUNT_HI 0 xc3ff
#define mmDB_RING_CONTROL 0 x261b
#define mmDB_READ_DEBUG_0 0 x2620
#define mmDB_READ_DEBUG_1 0 x2621
#define mmDB_READ_DEBUG_2 0 x2622
#define mmDB_READ_DEBUG_3 0 x2623
#define mmDB_READ_DEBUG_4 0 x2624
#define mmDB_READ_DEBUG_5 0 x2625
#define mmDB_READ_DEBUG_6 0 x2626
#define mmDB_READ_DEBUG_7 0 x2627
#define mmDB_READ_DEBUG_8 0 x2628
#define mmDB_READ_DEBUG_9 0 x2629
#define mmDB_READ_DEBUG_A 0 x262a
#define mmDB_READ_DEBUG_B 0 x262b
#define mmDB_READ_DEBUG_C 0 x262c
#define mmDB_READ_DEBUG_D 0 x262d
#define mmDB_READ_DEBUG_E 0 x262e
#define mmDB_READ_DEBUG_F 0 x262f
#define mmDB_OCCLUSION_COUNT0_LOW 0 xc3c0
#define mmDB_OCCLUSION_COUNT0_HI 0 xc3c1
#define mmDB_OCCLUSION_COUNT1_LOW 0 xc3c2
#define mmDB_OCCLUSION_COUNT1_HI 0 xc3c3
#define mmDB_OCCLUSION_COUNT2_LOW 0 xc3c4
#define mmDB_OCCLUSION_COUNT2_HI 0 xc3c5
#define mmDB_OCCLUSION_COUNT3_LOW 0 xc3c6
#define mmDB_OCCLUSION_COUNT3_HI 0 xc3c7
#define mmCC_RB_REDUNDANCY 0 x263c
#define mmCC_RB_BACKEND_DISABLE 0 x263d
#define mmGC_USER_RB_REDUNDANCY 0 x26de
#define mmGC_USER_RB_BACKEND_DISABLE 0 x26df
#define mmGB_ADDR_CONFIG 0 x263e
#define mmGB_BACKEND_MAP 0 x263f
#define mmGB_GPU_ID 0 x2640
#define mmCC_RB_DAISY_CHAIN 0 x2641
#define mmGB_TILE_MODE0 0 x2644
#define mmGB_TILE_MODE1 0 x2645
#define mmGB_TILE_MODE2 0 x2646
#define mmGB_TILE_MODE3 0 x2647
#define mmGB_TILE_MODE4 0 x2648
#define mmGB_TILE_MODE5 0 x2649
#define mmGB_TILE_MODE6 0 x264a
#define mmGB_TILE_MODE7 0 x264b
#define mmGB_TILE_MODE8 0 x264c
#define mmGB_TILE_MODE9 0 x264d
#define mmGB_TILE_MODE10 0 x264e
#define mmGB_TILE_MODE11 0 x264f
#define mmGB_TILE_MODE12 0 x2650
#define mmGB_TILE_MODE13 0 x2651
#define mmGB_TILE_MODE14 0 x2652
#define mmGB_TILE_MODE15 0 x2653
#define mmGB_TILE_MODE16 0 x2654
#define mmGB_TILE_MODE17 0 x2655
#define mmGB_TILE_MODE18 0 x2656
#define mmGB_TILE_MODE19 0 x2657
#define mmGB_TILE_MODE20 0 x2658
#define mmGB_TILE_MODE21 0 x2659
#define mmGB_TILE_MODE22 0 x265a
#define mmGB_TILE_MODE23 0 x265b
#define mmGB_TILE_MODE24 0 x265c
#define mmGB_TILE_MODE25 0 x265d
#define mmGB_TILE_MODE26 0 x265e
#define mmGB_TILE_MODE27 0 x265f
#define mmGB_TILE_MODE28 0 x2660
#define mmGB_TILE_MODE29 0 x2661
#define mmGB_TILE_MODE30 0 x2662
#define mmGB_TILE_MODE31 0 x2663
#define mmGB_MACROTILE_MODE0 0 x2664
#define mmGB_MACROTILE_MODE1 0 x2665
#define mmGB_MACROTILE_MODE2 0 x2666
#define mmGB_MACROTILE_MODE3 0 x2667
#define mmGB_MACROTILE_MODE4 0 x2668
#define mmGB_MACROTILE_MODE5 0 x2669
#define mmGB_MACROTILE_MODE6 0 x266a
#define mmGB_MACROTILE_MODE7 0 x266b
#define mmGB_MACROTILE_MODE8 0 x266c
#define mmGB_MACROTILE_MODE9 0 x266d
#define mmGB_MACROTILE_MODE10 0 x266e
#define mmGB_MACROTILE_MODE11 0 x266f
#define mmGB_MACROTILE_MODE12 0 x2670
#define mmGB_MACROTILE_MODE13 0 x2671
#define mmGB_MACROTILE_MODE14 0 x2672
#define mmGB_MACROTILE_MODE15 0 x2673
#define mmGB_EDC_MODE 0 x307e
#define mmCC_GC_EDC_CONFIG 0 x3098
#define mmRAS_SIGNATURE_CONTROL 0 x3380
#define mmRAS_SIGNATURE_MASK 0 x3381
#define mmRAS_SX_SIGNATURE0 0 x3382
#define mmRAS_SX_SIGNATURE1 0 x3383
#define mmRAS_SX_SIGNATURE2 0 x3384
#define mmRAS_SX_SIGNATURE3 0 x3385
#define mmRAS_DB_SIGNATURE0 0 x338b
#define mmRAS_PA_SIGNATURE0 0 x338c
#define mmRAS_VGT_SIGNATURE0 0 x338d
#define mmRAS_SC_SIGNATURE0 0 x338f
#define mmRAS_SC_SIGNATURE1 0 x3390
#define mmRAS_SC_SIGNATURE2 0 x3391
#define mmRAS_SC_SIGNATURE3 0 x3392
#define mmRAS_SC_SIGNATURE4 0 x3393
#define mmRAS_SC_SIGNATURE5 0 x3394
#define mmRAS_SC_SIGNATURE6 0 x3395
#define mmRAS_SC_SIGNATURE7 0 x3396
#define mmRAS_IA_SIGNATURE0 0 x3397
#define mmRAS_IA_SIGNATURE1 0 x3398
#define mmRAS_SPI_SIGNATURE0 0 x3399
#define mmRAS_SPI_SIGNATURE1 0 x339a
#define mmRAS_TA_SIGNATURE0 0 x339b
#define mmRAS_TD_SIGNATURE0 0 x339c
#define mmRAS_CB_SIGNATURE0 0 x339d
#define mmRAS_BCI_SIGNATURE0 0 x339e
#define mmRAS_BCI_SIGNATURE1 0 x339f
#define mmRAS_TA_SIGNATURE1 0 x33a0
#define mmGRBM_HYP_CAM_INDEX 0 xf83e
#define mmGRBM_CAM_INDEX 0 xf83e
#define mmGRBM_HYP_CAM_DATA 0 xf83f
#define mmGRBM_CAM_DATA 0 xf83f
#define mmGRBM_CNTL 0 x2000
#define mmGRBM_SKEW_CNTL 0 x2001
#define mmGRBM_PWR_CNTL 0 x2003
#define mmGRBM_STATUS 0 x2004
#define mmGRBM_STATUS2 0 x2002
#define mmGRBM_STATUS_SE0 0 x2005
#define mmGRBM_STATUS_SE1 0 x2006
#define mmGRBM_STATUS_SE2 0 x200e
#define mmGRBM_STATUS_SE3 0 x200f
#define mmGRBM_SOFT_RESET 0 x2008
#define mmGRBM_DEBUG_CNTL 0 x2009
#define mmGRBM_DEBUG_DATA 0 x200a
#define mmGRBM_CGTT_CLK_CNTL 0 x200b
#define mmGRBM_GFX_INDEX 0 xc200
#define mmGRBM_GFX_CLKEN_CNTL 0 x200c
#define mmGRBM_WAIT_IDLE_CLOCKS 0 x200d
#define mmGRBM_DEBUG 0 x2014
#define mmGRBM_DEBUG_SNAPSHOT 0 x2015
#define mmGRBM_READ_ERROR 0 x2016
#define mmGRBM_READ_ERROR2 0 x2017
#define mmGRBM_INT_CNTL 0 x2018
#define mmGRBM_TRAP_OP 0 x2019
#define mmGRBM_TRAP_ADDR 0 x201a
#define mmGRBM_TRAP_ADDR_MSK 0 x201b
#define mmGRBM_TRAP_WD 0 x201c
#define mmGRBM_TRAP_WD_MSK 0 x201d
#define mmGRBM_DSM_BYPASS 0 x201e
#define mmGRBM_WRITE_ERROR 0 x201f
#define mmGRBM_PERFCOUNTER0_SELECT 0 xd840
#define mmGRBM_PERFCOUNTER1_SELECT 0 xd841
#define mmGRBM_SE0_PERFCOUNTER_SELECT 0 xd842
#define mmGRBM_SE1_PERFCOUNTER_SELECT 0 xd843
#define mmGRBM_SE2_PERFCOUNTER_SELECT 0 xd844
#define mmGRBM_SE3_PERFCOUNTER_SELECT 0 xd845
#define mmGRBM_PERFCOUNTER0_LO 0 xd040
#define mmGRBM_PERFCOUNTER0_HI 0 xd041
#define mmGRBM_PERFCOUNTER1_LO 0 xd043
#define mmGRBM_PERFCOUNTER1_HI 0 xd044
#define mmGRBM_SE0_PERFCOUNTER_LO 0 xd045
#define mmGRBM_SE0_PERFCOUNTER_HI 0 xd046
#define mmGRBM_SE1_PERFCOUNTER_LO 0 xd047
#define mmGRBM_SE1_PERFCOUNTER_HI 0 xd048
#define mmGRBM_SE2_PERFCOUNTER_LO 0 xd049
#define mmGRBM_SE2_PERFCOUNTER_HI 0 xd04a
#define mmGRBM_SE3_PERFCOUNTER_LO 0 xd04b
#define mmGRBM_SE3_PERFCOUNTER_HI 0 xd04c
#define mmGRBM_SCRATCH_REG0 0 x2040
#define mmGRBM_SCRATCH_REG1 0 x2041
#define mmGRBM_SCRATCH_REG2 0 x2042
#define mmGRBM_SCRATCH_REG3 0 x2043
#define mmGRBM_SCRATCH_REG4 0 x2044
#define mmGRBM_SCRATCH_REG5 0 x2045
#define mmGRBM_SCRATCH_REG6 0 x2046
#define mmGRBM_SCRATCH_REG7 0 x2047
#define mmDEBUG_INDEX 0 x203c
#define mmDEBUG_DATA 0 x203d
#define mmGRBM_NOWHERE 0 x203f
#define mmPA_CL_VPORT_XSCALE 0 xa10f
#define mmPA_CL_VPORT_XOFFSET 0 xa110
#define mmPA_CL_VPORT_YSCALE 0 xa111
#define mmPA_CL_VPORT_YOFFSET 0 xa112
#define mmPA_CL_VPORT_ZSCALE 0 xa113
#define mmPA_CL_VPORT_ZOFFSET 0 xa114
#define mmPA_CL_VPORT_XSCALE_1 0 xa115
#define mmPA_CL_VPORT_XSCALE_2 0 xa11b
#define mmPA_CL_VPORT_XSCALE_3 0 xa121
#define mmPA_CL_VPORT_XSCALE_4 0 xa127
#define mmPA_CL_VPORT_XSCALE_5 0 xa12d
#define mmPA_CL_VPORT_XSCALE_6 0 xa133
#define mmPA_CL_VPORT_XSCALE_7 0 xa139
#define mmPA_CL_VPORT_XSCALE_8 0 xa13f
#define mmPA_CL_VPORT_XSCALE_9 0 xa145
#define mmPA_CL_VPORT_XSCALE_10 0 xa14b
#define mmPA_CL_VPORT_XSCALE_11 0 xa151
#define mmPA_CL_VPORT_XSCALE_12 0 xa157
#define mmPA_CL_VPORT_XSCALE_13 0 xa15d
#define mmPA_CL_VPORT_XSCALE_14 0 xa163
#define mmPA_CL_VPORT_XSCALE_15 0 xa169
#define mmPA_CL_VPORT_XOFFSET_1 0 xa116
#define mmPA_CL_VPORT_XOFFSET_2 0 xa11c
#define mmPA_CL_VPORT_XOFFSET_3 0 xa122
#define mmPA_CL_VPORT_XOFFSET_4 0 xa128
#define mmPA_CL_VPORT_XOFFSET_5 0 xa12e
#define mmPA_CL_VPORT_XOFFSET_6 0 xa134
#define mmPA_CL_VPORT_XOFFSET_7 0 xa13a
#define mmPA_CL_VPORT_XOFFSET_8 0 xa140
#define mmPA_CL_VPORT_XOFFSET_9 0 xa146
#define mmPA_CL_VPORT_XOFFSET_10 0 xa14c
#define mmPA_CL_VPORT_XOFFSET_11 0 xa152
#define mmPA_CL_VPORT_XOFFSET_12 0 xa158
#define mmPA_CL_VPORT_XOFFSET_13 0 xa15e
#define mmPA_CL_VPORT_XOFFSET_14 0 xa164
#define mmPA_CL_VPORT_XOFFSET_15 0 xa16a
#define mmPA_CL_VPORT_YSCALE_1 0 xa117
#define mmPA_CL_VPORT_YSCALE_2 0 xa11d
#define mmPA_CL_VPORT_YSCALE_3 0 xa123
#define mmPA_CL_VPORT_YSCALE_4 0 xa129
#define mmPA_CL_VPORT_YSCALE_5 0 xa12f
#define mmPA_CL_VPORT_YSCALE_6 0 xa135
#define mmPA_CL_VPORT_YSCALE_7 0 xa13b
#define mmPA_CL_VPORT_YSCALE_8 0 xa141
#define mmPA_CL_VPORT_YSCALE_9 0 xa147
#define mmPA_CL_VPORT_YSCALE_10 0 xa14d
#define mmPA_CL_VPORT_YSCALE_11 0 xa153
#define mmPA_CL_VPORT_YSCALE_12 0 xa159
#define mmPA_CL_VPORT_YSCALE_13 0 xa15f
#define mmPA_CL_VPORT_YSCALE_14 0 xa165
#define mmPA_CL_VPORT_YSCALE_15 0 xa16b
#define mmPA_CL_VPORT_YOFFSET_1 0 xa118
#define mmPA_CL_VPORT_YOFFSET_2 0 xa11e
#define mmPA_CL_VPORT_YOFFSET_3 0 xa124
#define mmPA_CL_VPORT_YOFFSET_4 0 xa12a
#define mmPA_CL_VPORT_YOFFSET_5 0 xa130
#define mmPA_CL_VPORT_YOFFSET_6 0 xa136
#define mmPA_CL_VPORT_YOFFSET_7 0 xa13c
#define mmPA_CL_VPORT_YOFFSET_8 0 xa142
#define mmPA_CL_VPORT_YOFFSET_9 0 xa148
#define mmPA_CL_VPORT_YOFFSET_10 0 xa14e
#define mmPA_CL_VPORT_YOFFSET_11 0 xa154
#define mmPA_CL_VPORT_YOFFSET_12 0 xa15a
#define mmPA_CL_VPORT_YOFFSET_13 0 xa160
#define mmPA_CL_VPORT_YOFFSET_14 0 xa166
#define mmPA_CL_VPORT_YOFFSET_15 0 xa16c
#define mmPA_CL_VPORT_ZSCALE_1 0 xa119
#define mmPA_CL_VPORT_ZSCALE_2 0 xa11f
#define mmPA_CL_VPORT_ZSCALE_3 0 xa125
#define mmPA_CL_VPORT_ZSCALE_4 0 xa12b
#define mmPA_CL_VPORT_ZSCALE_5 0 xa131
#define mmPA_CL_VPORT_ZSCALE_6 0 xa137
#define mmPA_CL_VPORT_ZSCALE_7 0 xa13d
#define mmPA_CL_VPORT_ZSCALE_8 0 xa143
#define mmPA_CL_VPORT_ZSCALE_9 0 xa149
#define mmPA_CL_VPORT_ZSCALE_10 0 xa14f
#define mmPA_CL_VPORT_ZSCALE_11 0 xa155
#define mmPA_CL_VPORT_ZSCALE_12 0 xa15b
#define mmPA_CL_VPORT_ZSCALE_13 0 xa161
#define mmPA_CL_VPORT_ZSCALE_14 0 xa167
#define mmPA_CL_VPORT_ZSCALE_15 0 xa16d
#define mmPA_CL_VPORT_ZOFFSET_1 0 xa11a
#define mmPA_CL_VPORT_ZOFFSET_2 0 xa120
#define mmPA_CL_VPORT_ZOFFSET_3 0 xa126
#define mmPA_CL_VPORT_ZOFFSET_4 0 xa12c
#define mmPA_CL_VPORT_ZOFFSET_5 0 xa132
#define mmPA_CL_VPORT_ZOFFSET_6 0 xa138
#define mmPA_CL_VPORT_ZOFFSET_7 0 xa13e
#define mmPA_CL_VPORT_ZOFFSET_8 0 xa144
#define mmPA_CL_VPORT_ZOFFSET_9 0 xa14a
#define mmPA_CL_VPORT_ZOFFSET_10 0 xa150
#define mmPA_CL_VPORT_ZOFFSET_11 0 xa156
#define mmPA_CL_VPORT_ZOFFSET_12 0 xa15c
#define mmPA_CL_VPORT_ZOFFSET_13 0 xa162
#define mmPA_CL_VPORT_ZOFFSET_14 0 xa168
#define mmPA_CL_VPORT_ZOFFSET_15 0 xa16e
#define mmPA_CL_VTE_CNTL 0 xa206
#define mmPA_CL_VS_OUT_CNTL 0 xa207
#define mmPA_CL_NANINF_CNTL 0 xa208
#define mmPA_CL_CLIP_CNTL 0 xa204
#define mmPA_CL_GB_VERT_CLIP_ADJ 0 xa2fa
#define mmPA_CL_GB_VERT_DISC_ADJ 0 xa2fb
#define mmPA_CL_GB_HORZ_CLIP_ADJ 0 xa2fc
#define mmPA_CL_GB_HORZ_DISC_ADJ 0 xa2fd
#define mmPA_CL_UCP_0_X 0 xa16f
#define mmPA_CL_UCP_0_Y 0 xa170
#define mmPA_CL_UCP_0_Z 0 xa171
#define mmPA_CL_UCP_0_W 0 xa172
#define mmPA_CL_UCP_1_X 0 xa173
#define mmPA_CL_UCP_1_Y 0 xa174
#define mmPA_CL_UCP_1_Z 0 xa175
#define mmPA_CL_UCP_1_W 0 xa176
#define mmPA_CL_UCP_2_X 0 xa177
#define mmPA_CL_UCP_2_Y 0 xa178
#define mmPA_CL_UCP_2_Z 0 xa179
#define mmPA_CL_UCP_2_W 0 xa17a
#define mmPA_CL_UCP_3_X 0 xa17b
#define mmPA_CL_UCP_3_Y 0 xa17c
#define mmPA_CL_UCP_3_Z 0 xa17d
#define mmPA_CL_UCP_3_W 0 xa17e
#define mmPA_CL_UCP_4_X 0 xa17f
#define mmPA_CL_UCP_4_Y 0 xa180
#define mmPA_CL_UCP_4_Z 0 xa181
#define mmPA_CL_UCP_4_W 0 xa182
#define mmPA_CL_UCP_5_X 0 xa183
#define mmPA_CL_UCP_5_Y 0 xa184
#define mmPA_CL_UCP_5_Z 0 xa185
#define mmPA_CL_UCP_5_W 0 xa186
#define mmPA_CL_POINT_X_RAD 0 xa1f5
#define mmPA_CL_POINT_Y_RAD 0 xa1f6
#define mmPA_CL_POINT_SIZE 0 xa1f7
#define mmPA_CL_POINT_CULL_RAD 0 xa1f8
#define mmPA_CL_ENHANCE 0 x2285
#define mmPA_CL_RESET_DEBUG 0 x2286
#define mmPA_SU_VTX_CNTL 0 xa2f9
#define mmPA_SU_POINT_SIZE 0 xa280
#define mmPA_SU_POINT_MINMAX 0 xa281
#define mmPA_SU_LINE_CNTL 0 xa282
#define mmPA_SU_LINE_STIPPLE_CNTL 0 xa209
#define mmPA_SU_LINE_STIPPLE_SCALE 0 xa20a
#define mmPA_SU_PRIM_FILTER_CNTL 0 xa20b
#define mmPA_SU_SC_MODE_CNTL 0 xa205
#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0 xa2de
#define mmPA_SU_POLY_OFFSET_CLAMP 0 xa2df
#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0 xa2e0
#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0 xa2e1
#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0 xa2e2
#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0 xa2e3
#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0 xa08d
#define mmPA_SU_LINE_STIPPLE_VALUE 0 xc280
#define mmPA_SU_PERFCOUNTER0_SELECT 0 xd900
#define mmPA_SU_PERFCOUNTER0_SELECT1 0 xd901
#define mmPA_SU_PERFCOUNTER1_SELECT 0 xd902
#define mmPA_SU_PERFCOUNTER1_SELECT1 0 xd903
#define mmPA_SU_PERFCOUNTER2_SELECT 0 xd904
#define mmPA_SU_PERFCOUNTER3_SELECT 0 xd905
#define mmPA_SU_PERFCOUNTER0_LO 0 xd100
#define mmPA_SU_PERFCOUNTER0_HI 0 xd101
#define mmPA_SU_PERFCOUNTER1_LO 0 xd102
#define mmPA_SU_PERFCOUNTER1_HI 0 xd103
#define mmPA_SU_PERFCOUNTER2_LO 0 xd104
#define mmPA_SU_PERFCOUNTER2_HI 0 xd105
#define mmPA_SU_PERFCOUNTER3_LO 0 xd106
#define mmPA_SU_PERFCOUNTER3_HI 0 xd107
#define mmPA_SC_AA_CONFIG 0 xa2f8
#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0 xa30e
#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0 xa30f
#define mmPA_SC_SHADER_CONTROL 0 xa310
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0 xa2fe
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0 xa2ff
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0 xa300
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0 xa301
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0 xa302
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0 xa303
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0 xa304
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0 xa305
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0 xa306
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0 xa307
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0 xa308
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0 xa309
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0 xa30a
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0 xa30b
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0 xa30c
#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0 xa30d
#define mmPA_SC_CENTROID_PRIORITY_0 0 xa2f5
#define mmPA_SC_CENTROID_PRIORITY_1 0 xa2f6
#define mmPA_SC_CLIPRECT_0_TL 0 xa084
#define mmPA_SC_CLIPRECT_0_BR 0 xa085
#define mmPA_SC_CLIPRECT_1_TL 0 xa086
#define mmPA_SC_CLIPRECT_1_BR 0 xa087
#define mmPA_SC_CLIPRECT_2_TL 0 xa088
#define mmPA_SC_CLIPRECT_2_BR 0 xa089
#define mmPA_SC_CLIPRECT_3_TL 0 xa08a
#define mmPA_SC_CLIPRECT_3_BR 0 xa08b
#define mmPA_SC_CLIPRECT_RULE 0 xa083
#define mmPA_SC_EDGERULE 0 xa08c
#define mmPA_SC_LINE_CNTL 0 xa2f7
#define mmPA_SC_LINE_STIPPLE 0 xa283
#define mmPA_SC_MODE_CNTL_0 0 xa292
#define mmPA_SC_MODE_CNTL_1 0 xa293
#define mmPA_SC_RASTER_CONFIG 0 xa0d4
#define mmPA_SC_RASTER_CONFIG_1 0 xa0d5
#define mmPA_SC_SCREEN_EXTENT_CONTROL 0 xa0d6
#define mmPA_SC_GENERIC_SCISSOR_TL 0 xa090
#define mmPA_SC_GENERIC_SCISSOR_BR 0 xa091
#define mmPA_SC_SCREEN_SCISSOR_TL 0 xa00c
#define mmPA_SC_SCREEN_SCISSOR_BR 0 xa00d
#define mmPA_SC_WINDOW_OFFSET 0 xa080
#define mmPA_SC_WINDOW_SCISSOR_TL 0 xa081
#define mmPA_SC_WINDOW_SCISSOR_BR 0 xa082
#define mmPA_SC_VPORT_SCISSOR_0_TL 0 xa094
#define mmPA_SC_VPORT_SCISSOR_1_TL 0 xa096
#define mmPA_SC_VPORT_SCISSOR_2_TL 0 xa098
#define mmPA_SC_VPORT_SCISSOR_3_TL 0 xa09a
#define mmPA_SC_VPORT_SCISSOR_4_TL 0 xa09c
#define mmPA_SC_VPORT_SCISSOR_5_TL 0 xa09e
#define mmPA_SC_VPORT_SCISSOR_6_TL 0 xa0a0
#define mmPA_SC_VPORT_SCISSOR_7_TL 0 xa0a2
#define mmPA_SC_VPORT_SCISSOR_8_TL 0 xa0a4
#define mmPA_SC_VPORT_SCISSOR_9_TL 0 xa0a6
#define mmPA_SC_VPORT_SCISSOR_10_TL 0 xa0a8
#define mmPA_SC_VPORT_SCISSOR_11_TL 0 xa0aa
#define mmPA_SC_VPORT_SCISSOR_12_TL 0 xa0ac
#define mmPA_SC_VPORT_SCISSOR_13_TL 0 xa0ae
#define mmPA_SC_VPORT_SCISSOR_14_TL 0 xa0b0
#define mmPA_SC_VPORT_SCISSOR_15_TL 0 xa0b2
#define mmPA_SC_VPORT_SCISSOR_0_BR 0 xa095
#define mmPA_SC_VPORT_SCISSOR_1_BR 0 xa097
#define mmPA_SC_VPORT_SCISSOR_2_BR 0 xa099
#define mmPA_SC_VPORT_SCISSOR_3_BR 0 xa09b
#define mmPA_SC_VPORT_SCISSOR_4_BR 0 xa09d
#define mmPA_SC_VPORT_SCISSOR_5_BR 0 xa09f
#define mmPA_SC_VPORT_SCISSOR_6_BR 0 xa0a1
#define mmPA_SC_VPORT_SCISSOR_7_BR 0 xa0a3
#define mmPA_SC_VPORT_SCISSOR_8_BR 0 xa0a5
#define mmPA_SC_VPORT_SCISSOR_9_BR 0 xa0a7
#define mmPA_SC_VPORT_SCISSOR_10_BR 0 xa0a9
#define mmPA_SC_VPORT_SCISSOR_11_BR 0 xa0ab
#define mmPA_SC_VPORT_SCISSOR_12_BR 0 xa0ad
#define mmPA_SC_VPORT_SCISSOR_13_BR 0 xa0af
#define mmPA_SC_VPORT_SCISSOR_14_BR 0 xa0b1
#define mmPA_SC_VPORT_SCISSOR_15_BR 0 xa0b3
#define mmPA_SC_VPORT_ZMIN_0 0 xa0b4
#define mmPA_SC_VPORT_ZMIN_1 0 xa0b6
#define mmPA_SC_VPORT_ZMIN_2 0 xa0b8
#define mmPA_SC_VPORT_ZMIN_3 0 xa0ba
#define mmPA_SC_VPORT_ZMIN_4 0 xa0bc
#define mmPA_SC_VPORT_ZMIN_5 0 xa0be
#define mmPA_SC_VPORT_ZMIN_6 0 xa0c0
#define mmPA_SC_VPORT_ZMIN_7 0 xa0c2
#define mmPA_SC_VPORT_ZMIN_8 0 xa0c4
#define mmPA_SC_VPORT_ZMIN_9 0 xa0c6
#define mmPA_SC_VPORT_ZMIN_10 0 xa0c8
#define mmPA_SC_VPORT_ZMIN_11 0 xa0ca
#define mmPA_SC_VPORT_ZMIN_12 0 xa0cc
#define mmPA_SC_VPORT_ZMIN_13 0 xa0ce
#define mmPA_SC_VPORT_ZMIN_14 0 xa0d0
#define mmPA_SC_VPORT_ZMIN_15 0 xa0d2
#define mmPA_SC_VPORT_ZMAX_0 0 xa0b5
#define mmPA_SC_VPORT_ZMAX_1 0 xa0b7
#define mmPA_SC_VPORT_ZMAX_2 0 xa0b9
#define mmPA_SC_VPORT_ZMAX_3 0 xa0bb
#define mmPA_SC_VPORT_ZMAX_4 0 xa0bd
#define mmPA_SC_VPORT_ZMAX_5 0 xa0bf
#define mmPA_SC_VPORT_ZMAX_6 0 xa0c1
#define mmPA_SC_VPORT_ZMAX_7 0 xa0c3
#define mmPA_SC_VPORT_ZMAX_8 0 xa0c5
#define mmPA_SC_VPORT_ZMAX_9 0 xa0c7
#define mmPA_SC_VPORT_ZMAX_10 0 xa0c9
#define mmPA_SC_VPORT_ZMAX_11 0 xa0cb
#define mmPA_SC_VPORT_ZMAX_12 0 xa0cd
#define mmPA_SC_VPORT_ZMAX_13 0 xa0cf
#define mmPA_SC_VPORT_ZMAX_14 0 xa0d1
#define mmPA_SC_VPORT_ZMAX_15 0 xa0d3
#define mmPA_SC_ENHANCE 0 x22fc
#define mmPA_SC_ENHANCE_1 0 x22fd
#define mmPA_SC_DSM_CNTL 0 x22fe
#define mmPA_SC_FIFO_SIZE 0 x22f3
#define mmPA_SC_IF_FIFO_SIZE 0 x22f5
#define mmPA_SC_FORCE_EOV_MAX_CNTS 0 x22c9
#define mmPA_SC_LINE_STIPPLE_STATE 0 xc281
#define mmPA_SC_SCREEN_EXTENT_MIN_0 0 xc284
#define mmPA_SC_SCREEN_EXTENT_MAX_0 0 xc285
#define mmPA_SC_SCREEN_EXTENT_MIN_1 0 xc286
#define mmPA_SC_SCREEN_EXTENT_MAX_1 0 xc28b
#define mmPA_SC_PERFCOUNTER0_SELECT 0 xd940
#define mmPA_SC_PERFCOUNTER0_SELECT1 0 xd941
#define mmPA_SC_PERFCOUNTER1_SELECT 0 xd942
#define mmPA_SC_PERFCOUNTER2_SELECT 0 xd943
#define mmPA_SC_PERFCOUNTER3_SELECT 0 xd944
#define mmPA_SC_PERFCOUNTER4_SELECT 0 xd945
#define mmPA_SC_PERFCOUNTER5_SELECT 0 xd946
#define mmPA_SC_PERFCOUNTER6_SELECT 0 xd947
#define mmPA_SC_PERFCOUNTER7_SELECT 0 xd948
#define mmPA_SC_PERFCOUNTER0_LO 0 xd140
#define mmPA_SC_PERFCOUNTER0_HI 0 xd141
#define mmPA_SC_PERFCOUNTER1_LO 0 xd142
#define mmPA_SC_PERFCOUNTER1_HI 0 xd143
#define mmPA_SC_PERFCOUNTER2_LO 0 xd144
#define mmPA_SC_PERFCOUNTER2_HI 0 xd145
#define mmPA_SC_PERFCOUNTER3_LO 0 xd146
#define mmPA_SC_PERFCOUNTER3_HI 0 xd147
#define mmPA_SC_PERFCOUNTER4_LO 0 xd148
#define mmPA_SC_PERFCOUNTER4_HI 0 xd149
#define mmPA_SC_PERFCOUNTER5_LO 0 xd14a
#define mmPA_SC_PERFCOUNTER5_HI 0 xd14b
#define mmPA_SC_PERFCOUNTER6_LO 0 xd14c
#define mmPA_SC_PERFCOUNTER6_HI 0 xd14d
#define mmPA_SC_PERFCOUNTER7_LO 0 xd14e
#define mmPA_SC_PERFCOUNTER7_HI 0 xd14f
#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0 xc2a0
#define mmPA_SC_P3D_TRAP_SCREEN_H 0 xc2a1
#define mmPA_SC_P3D_TRAP_SCREEN_V 0 xc2a2
#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0 xc2a3
#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0 xc2a4
#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0 xc2a8
#define mmPA_SC_HP3D_TRAP_SCREEN_H 0 xc2a9
#define mmPA_SC_HP3D_TRAP_SCREEN_V 0 xc2aa
#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0 xc2ab
#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0 xc2ac
#define mmPA_SC_TRAP_SCREEN_HV_EN 0 xc2b0
#define mmPA_SC_TRAP_SCREEN_H 0 xc2b1
#define mmPA_SC_TRAP_SCREEN_V 0 xc2b2
#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0 xc2b3
#define mmPA_SC_TRAP_SCREEN_COUNT 0 xc2b4
#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0 x22c0
#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0 x22c1
#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0 x22c2
#define mmPA_CL_CNTL_STATUS 0 x2284
#define mmPA_SU_CNTL_STATUS 0 x2294
#define mmPA_SC_FIFO_DEPTH_CNTL 0 x2295
#define mmCGTT_PA_CLK_CTRL 0 xf088
#define mmCGTT_SC_CLK_CTRL 0 xf089
#define mmPA_SU_DEBUG_CNTL 0 x2280
#define mmPA_SU_DEBUG_DATA 0 x2281
#define mmPA_SC_DEBUG_CNTL 0 x22f6
#define mmPA_SC_DEBUG_DATA 0 x22f7
#define ixCLIPPER_DEBUG_REG00 0 x0
#define ixCLIPPER_DEBUG_REG01 0 x1
#define ixCLIPPER_DEBUG_REG02 0 x2
#define ixCLIPPER_DEBUG_REG03 0 x3
#define ixCLIPPER_DEBUG_REG04 0 x4
#define ixCLIPPER_DEBUG_REG05 0 x5
#define ixCLIPPER_DEBUG_REG06 0 x6
#define ixCLIPPER_DEBUG_REG07 0 x7
#define ixCLIPPER_DEBUG_REG08 0 x8
#define ixCLIPPER_DEBUG_REG09 0 x9
#define ixCLIPPER_DEBUG_REG10 0 xa
#define ixCLIPPER_DEBUG_REG11 0 xb
#define ixCLIPPER_DEBUG_REG12 0 xc
#define ixCLIPPER_DEBUG_REG13 0 xd
#define ixCLIPPER_DEBUG_REG14 0 xe
#define ixCLIPPER_DEBUG_REG15 0 xf
#define ixCLIPPER_DEBUG_REG16 0 x10
#define ixCLIPPER_DEBUG_REG17 0 x11
#define ixCLIPPER_DEBUG_REG18 0 x12
#define ixCLIPPER_DEBUG_REG19 0 x13
#define ixSXIFCCG_DEBUG_REG0 0 x14
#define ixSXIFCCG_DEBUG_REG1 0 x15
#define ixSXIFCCG_DEBUG_REG2 0 x16
#define ixSXIFCCG_DEBUG_REG3 0 x17
#define ixSETUP_DEBUG_REG0 0 x18
#define ixSETUP_DEBUG_REG1 0 x19
#define ixSETUP_DEBUG_REG2 0 x1a
#define ixSETUP_DEBUG_REG3 0 x1b
#define ixSETUP_DEBUG_REG4 0 x1c
#define ixSETUP_DEBUG_REG5 0 x1d
#define ixPA_SC_DEBUG_REG0 0 x0
#define ixPA_SC_DEBUG_REG1 0 x1
#define mmCOMPUTE_DISPATCH_INITIATOR 0 x2e00
#define mmCOMPUTE_DIM_X 0 x2e01
#define mmCOMPUTE_DIM_Y 0 x2e02
#define mmCOMPUTE_DIM_Z 0 x2e03
#define mmCOMPUTE_START_X 0 x2e04
#define mmCOMPUTE_START_Y 0 x2e05
#define mmCOMPUTE_START_Z 0 x2e06
#define mmCOMPUTE_NUM_THREAD_X 0 x2e07
#define mmCOMPUTE_NUM_THREAD_Y 0 x2e08
#define mmCOMPUTE_NUM_THREAD_Z 0 x2e09
#define mmCOMPUTE_PIPELINESTAT_ENABLE 0 x2e0a
#define mmCOMPUTE_PERFCOUNT_ENABLE 0 x2e0b
#define mmCOMPUTE_PGM_LO 0 x2e0c
#define mmCOMPUTE_PGM_HI 0 x2e0d
#define mmCOMPUTE_TBA_LO 0 x2e0e
#define mmCOMPUTE_TBA_HI 0 x2e0f
#define mmCOMPUTE_TMA_LO 0 x2e10
#define mmCOMPUTE_TMA_HI 0 x2e11
#define mmCOMPUTE_PGM_RSRC1 0 x2e12
#define mmCOMPUTE_PGM_RSRC2 0 x2e13
#define mmCOMPUTE_VMID 0 x2e14
#define mmCOMPUTE_RESOURCE_LIMITS 0 x2e15
#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0 x2e16
#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0 x2e17
#define mmCOMPUTE_TMPRING_SIZE 0 x2e18
#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0 x2e19
#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0 x2e1a
#define mmCOMPUTE_RESTART_X 0 x2e1b
#define mmCOMPUTE_RESTART_Y 0 x2e1c
#define mmCOMPUTE_RESTART_Z 0 x2e1d
#define mmCOMPUTE_THREAD_TRACE_ENABLE 0 x2e1e
#define mmCOMPUTE_MISC_RESERVED 0 x2e1f
#define mmCOMPUTE_DISPATCH_ID 0 x2e20
#define mmCOMPUTE_THREADGROUP_ID 0 x2e21
#define mmCOMPUTE_RELAUNCH 0 x2e22
#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0 x2e23
#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0 x2e24
#define mmCOMPUTE_WAVE_RESTORE_CONTROL 0 x2e25
#define mmCOMPUTE_USER_DATA_0 0 x2e40
#define mmCOMPUTE_USER_DATA_1 0 x2e41
#define mmCOMPUTE_USER_DATA_2 0 x2e42
#define mmCOMPUTE_USER_DATA_3 0 x2e43
#define mmCOMPUTE_USER_DATA_4 0 x2e44
#define mmCOMPUTE_USER_DATA_5 0 x2e45
#define mmCOMPUTE_USER_DATA_6 0 x2e46
#define mmCOMPUTE_USER_DATA_7 0 x2e47
#define mmCOMPUTE_USER_DATA_8 0 x2e48
#define mmCOMPUTE_USER_DATA_9 0 x2e49
#define mmCOMPUTE_USER_DATA_10 0 x2e4a
#define mmCOMPUTE_USER_DATA_11 0 x2e4b
#define mmCOMPUTE_USER_DATA_12 0 x2e4c
#define mmCOMPUTE_USER_DATA_13 0 x2e4d
#define mmCOMPUTE_USER_DATA_14 0 x2e4e
#define mmCOMPUTE_USER_DATA_15 0 x2e4f
#define mmCOMPUTE_NOWHERE 0 x2e7f
#define mmCSPRIV_CONNECT 0 x0
#define mmCSPRIV_THREAD_TRACE_TG0 0 x1e
#define mmCSPRIV_THREAD_TRACE_TG1 0 x1e
#define mmCSPRIV_THREAD_TRACE_TG2 0 x1e
#define mmCSPRIV_THREAD_TRACE_TG3 0 x1e
#define mmCSPRIV_THREAD_TRACE_EVENT 0 x1f
#define mmRLC_CNTL 0 xec00
#define mmRLC_DEBUG_SELECT 0 xec01
#define mmRLC_DEBUG 0 xec02
#define mmRLC_MC_CNTL 0 xec03
#define mmRLC_STAT 0 xec04
#define mmRLC_SAFE_MODE 0 xec05
#define mmRLC_MEM_SLP_CNTL 0 xec06
#define mmSMU_RLC_RESPONSE 0 xec07
#define mmRLC_RLCV_SAFE_MODE 0 xec08
#define mmRLC_SMU_SAFE_MODE 0 xec09
#define mmRLC_RLCV_COMMAND 0 xec0a
#define mmRLC_CLK_CNTL 0 xec0b
#define mmRLC_PERFMON_CLK_CNTL 0 xdcbf
#define mmRLC_PERFMON_CNTL 0 xdcc0
#define mmRLC_PERFCOUNTER0_SELECT 0 xdcc1
#define mmRLC_PERFCOUNTER1_SELECT 0 xdcc2
#define mmRLC_PERFCOUNTER0_LO 0 xd480
#define mmRLC_PERFCOUNTER1_LO 0 xd482
#define mmRLC_PERFCOUNTER0_HI 0 xd481
#define mmRLC_PERFCOUNTER1_HI 0 xd483
#define mmCGTT_RLC_CLK_CTRL 0 xf0b8
#define mmRLC_LB_CNTL 0 xec19
#define mmRLC_LB_CNTR_MAX 0 xec12
#define mmRLC_LB_CNTR_INIT 0 xec1b
#define mmRLC_LOAD_BALANCE_CNTR 0 xec1c
#define mmRLC_JUMP_TABLE_RESTORE 0 xec1e
#define mmRLC_PG_DELAY_2 0 xec1f
#define mmRLC_GPM_DEBUG_SELECT 0 xec20
#define mmRLC_GPM_DEBUG 0 xec21
#define mmRLC_GPM_DEBUG_INST_A 0 xec22
#define mmRLC_GPM_DEBUG_INST_B 0 xec23
#define mmRLC_GPM_DEBUG_INST_ADDR 0 xec1d
#define mmRLC_GPM_UCODE_ADDR 0 xf83c
#define mmRLC_GPM_UCODE_DATA 0 xf83d
#define mmGPU_BIST_CONTROL 0 xf835
#define mmRLC_ROM_CNTL 0 xf836
#define mmRLC_GPU_CLOCK_COUNT_LSB 0 xec24
#define mmRLC_GPU_CLOCK_COUNT_MSB 0 xec25
#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0 xec26
#define mmRLC_UCODE_CNTL 0 xec27
#define mmRLC_GPM_STAT 0 xec40
#define mmRLC_GPU_CLOCK_32_RES_SEL 0 xec41
#define mmRLC_GPU_CLOCK_32 0 xec42
#define mmRLC_PG_CNTL 0 xec43
#define mmRLC_GPM_THREAD_PRIORITY 0 xec44
#define mmRLC_GPM_THREAD_ENABLE 0 xec45
#define mmRLC_GPM_VMID_THREAD0 0 xec46
#define mmRLC_GPM_VMID_THREAD1 0 xec47
#define mmRLC_CGTT_MGCG_OVERRIDE 0 xec48
#define mmRLC_CGCG_CGLS_CTRL 0 xec49
#define mmRLC_CGCG_RAMP_CTRL 0 xec4a
#define mmRLC_DYN_PG_STATUS 0 xec4b
#define mmRLC_DYN_PG_REQUEST 0 xec4c
#define mmRLC_PG_DELAY 0 xec4d
#define mmRLC_CU_STATUS 0 xec4e
#define mmRLC_LB_INIT_CU_MASK 0 xec4f
#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0 xec50
#define mmRLC_LB_PARAMS 0 xec51
#define mmRLC_THREAD1_DELAY 0 xec52
#define mmRLC_PG_ALWAYS_ON_CU_MASK 0 xec53
#define mmRLC_MAX_PG_CU 0 xec54
#define mmRLC_AUTO_PG_CTRL 0 xec55
#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0 xec56
#define mmRLC_SERDES_RD_MASTER_INDEX 0 xec59
#define mmRLC_SERDES_RD_DATA_0 0 xec5a
#define mmRLC_SERDES_RD_DATA_1 0 xec5b
#define mmRLC_SERDES_RD_DATA_2 0 xec5c
#define mmRLC_SERDES_WR_CU_MASTER_MASK 0 xec5d
#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0 xec5e
#define mmRLC_SERDES_WR_CTRL 0 xec5f
#define mmRLC_SERDES_WR_DATA 0 xec60
#define mmRLC_SERDES_CU_MASTER_BUSY 0 xec61
#define mmRLC_SERDES_NONCU_MASTER_BUSY 0 xec62
#define mmRLC_GPM_GENERAL_0 0 xec63
#define mmRLC_GPM_GENERAL_1 0 xec64
#define mmRLC_GPM_GENERAL_2 0 xec65
#define mmRLC_GPM_GENERAL_3 0 xec66
#define mmRLC_GPM_GENERAL_4 0 xec67
#define mmRLC_GPM_GENERAL_5 0 xec68
#define mmRLC_GPM_GENERAL_6 0 xec69
#define mmRLC_GPM_GENERAL_7 0 xec6a
#define mmRLC_GPM_SCRATCH_ADDR 0 xec6c
#define mmRLC_GPM_SCRATCH_DATA 0 xec6d
#define mmRLC_STATIC_PG_STATUS 0 xec6e
#define mmRLC_GPM_PERF_COUNT_0 0 xec6f
#define mmRLC_GPM_PERF_COUNT_1 0 xec70
#define mmRLC_GPR_REG1 0 xec79
#define mmRLC_GPR_REG2 0 xec7a
#define mmRLC_MGCG_CTRL 0 xec1a
#define mmRLC_GPM_THREAD_RESET 0 xec28
#define mmRLC_SPM_VMID 0 xec71
#define mmRLC_SPM_INT_CNTL 0 xec72
#define mmRLC_SPM_INT_STATUS 0 xec73
#define mmRLC_SPM_DEBUG_SELECT 0 xec74
#define mmRLC_SPM_DEBUG 0 xec75
#define mmRLC_SMU_MESSAGE 0 xec76
#define mmRLC_GPM_LOG_SIZE 0 xec77
#define mmRLC_GPM_LOG_CONT 0 xec7b
#define mmRLC_PG_DELAY_3 0 xec78
#define mmRLC_GPM_INT_DISABLE_TH0 0 xec7c
#define mmRLC_GPM_INT_DISABLE_TH1 0 xec7d
#define mmRLC_GPM_INT_FORCE_TH0 0 xec7e
#define mmRLC_GPM_INT_FORCE_TH1 0 xec7f
#define mmRLC_SRM_CNTL 0 xec80
#define mmRLC_SRM_DEBUG_SELECT 0 xec81
#define mmRLC_SRM_DEBUG 0 xec82
#define mmRLC_SRM_ARAM_ADDR 0 xec83
#define mmRLC_SRM_ARAM_DATA 0 xec84
#define mmRLC_SRM_DRAM_ADDR 0 xec85
#define mmRLC_SRM_DRAM_DATA 0 xec86
#define mmRLC_SRM_GPM_COMMAND 0 xec87
#define mmRLC_SRM_GPM_COMMAND_STATUS 0 xec88
#define mmRLC_SRM_RLCV_COMMAND 0 xec89
#define mmRLC_SRM_RLCV_COMMAND_STATUS 0 xec8a
#define mmRLC_SRM_INDEX_CNTL_ADDR_0 0 xec8b
#define mmRLC_SRM_INDEX_CNTL_ADDR_1 0 xec8c
#define mmRLC_SRM_INDEX_CNTL_ADDR_2 0 xec8d
#define mmRLC_SRM_INDEX_CNTL_ADDR_3 0 xec8e
#define mmRLC_SRM_INDEX_CNTL_ADDR_4 0 xec8f
#define mmRLC_SRM_INDEX_CNTL_ADDR_5 0 xec90
#define mmRLC_SRM_INDEX_CNTL_ADDR_6 0 xec91
#define mmRLC_SRM_INDEX_CNTL_ADDR_7 0 xec92
#define mmRLC_SRM_INDEX_CNTL_DATA_0 0 xec93
#define mmRLC_SRM_INDEX_CNTL_DATA_1 0 xec94
#define mmRLC_SRM_INDEX_CNTL_DATA_2 0 xec95
#define mmRLC_SRM_INDEX_CNTL_DATA_3 0 xec96
#define mmRLC_SRM_INDEX_CNTL_DATA_4 0 xec97
#define mmRLC_SRM_INDEX_CNTL_DATA_5 0 xec98
#define mmRLC_SRM_INDEX_CNTL_DATA_6 0 xec99
#define mmRLC_SRM_INDEX_CNTL_DATA_7 0 xec9a
#define mmRLC_SRM_STAT 0 xec9b
#define mmRLC_SRM_GPM_ABORT 0 xec9c
#define mmRLC_CSIB_ADDR_LO 0 xeca2
#define mmRLC_CSIB_ADDR_HI 0 xeca3
#define mmRLC_CSIB_LENGTH 0 xeca4
#define mmRLC_CP_RESPONSE0 0 xeca5
#define mmRLC_CP_RESPONSE1 0 xeca6
#define mmRLC_CP_RESPONSE2 0 xeca7
#define mmRLC_CP_RESPONSE3 0 xeca8
#define mmRLC_SMU_COMMAND 0 xeca9
#define mmRLC_CP_SCHEDULERS 0 xecaa
#define mmRLC_SMU_ARGUMENT_1 0 xecab
#define mmRLC_SMU_ARGUMENT_2 0 xecac
#define mmRLC_GPM_GENERAL_8 0 xecad
#define mmRLC_GPM_GENERAL_9 0 xecae
#define mmRLC_GPM_GENERAL_10 0 xecaf
#define mmRLC_GPM_GENERAL_11 0 xecb0
#define mmRLC_GPM_GENERAL_12 0 xecb1
#define mmRLC_SPM_PERFMON_CNTL 0 xdc80
#define mmRLC_SPM_PERFMON_RING_BASE_LO 0 xdc81
#define mmRLC_SPM_PERFMON_RING_BASE_HI 0 xdc82
#define mmRLC_SPM_PERFMON_RING_SIZE 0 xdc83
#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0 xdc84
#define mmRLC_SPM_SE_MUXSEL_ADDR 0 xdc85
#define mmRLC_SPM_SE_MUXSEL_DATA 0 xdc86
#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0 xdc87
#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0 xdc88
#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0 xdc89
#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0 xdc8a
#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0 xdc8b
#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0 xdc8c
#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0 xdc8d
#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0 xdc8e
#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0 xdc90
#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0 xdc91
#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0 xdc92
#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0 xdc93
#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0 xdc94
#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0 xdc95
#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0 xdc96
#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0 xdc97
#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0 xdc98
#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0 xdc9a
#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0 xdc9b
#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0 xdc9c
#define mmRLC_SPM_RING_RDPTR 0 xdc9d
#define mmRLC_SPM_SEGMENT_THRESHOLD 0 xdc9e
#define mmRLC_GPU_IOV_VF_ENABLE 0 xfb00
#define mmRLC_GPU_IOV_RLC_RESPONSE 0 xfb4d
#define mmRLC_GPU_IOV_ACTIVE_FCN_ID 0 xfb40
#define mmSPI_PS_INPUT_CNTL_0 0 xa191
#define mmSPI_PS_INPUT_CNTL_1 0 xa192
#define mmSPI_PS_INPUT_CNTL_2 0 xa193
#define mmSPI_PS_INPUT_CNTL_3 0 xa194
#define mmSPI_PS_INPUT_CNTL_4 0 xa195
#define mmSPI_PS_INPUT_CNTL_5 0 xa196
#define mmSPI_PS_INPUT_CNTL_6 0 xa197
#define mmSPI_PS_INPUT_CNTL_7 0 xa198
#define mmSPI_PS_INPUT_CNTL_8 0 xa199
#define mmSPI_PS_INPUT_CNTL_9 0 xa19a
#define mmSPI_PS_INPUT_CNTL_10 0 xa19b
#define mmSPI_PS_INPUT_CNTL_11 0 xa19c
#define mmSPI_PS_INPUT_CNTL_12 0 xa19d
#define mmSPI_PS_INPUT_CNTL_13 0 xa19e
#define mmSPI_PS_INPUT_CNTL_14 0 xa19f
#define mmSPI_PS_INPUT_CNTL_15 0 xa1a0
#define mmSPI_PS_INPUT_CNTL_16 0 xa1a1
#define mmSPI_PS_INPUT_CNTL_17 0 xa1a2
#define mmSPI_PS_INPUT_CNTL_18 0 xa1a3
#define mmSPI_PS_INPUT_CNTL_19 0 xa1a4
#define mmSPI_PS_INPUT_CNTL_20 0 xa1a5
#define mmSPI_PS_INPUT_CNTL_21 0 xa1a6
#define mmSPI_PS_INPUT_CNTL_22 0 xa1a7
#define mmSPI_PS_INPUT_CNTL_23 0 xa1a8
#define mmSPI_PS_INPUT_CNTL_24 0 xa1a9
#define mmSPI_PS_INPUT_CNTL_25 0 xa1aa
#define mmSPI_PS_INPUT_CNTL_26 0 xa1ab
#define mmSPI_PS_INPUT_CNTL_27 0 xa1ac
#define mmSPI_PS_INPUT_CNTL_28 0 xa1ad
#define mmSPI_PS_INPUT_CNTL_29 0 xa1ae
#define mmSPI_PS_INPUT_CNTL_30 0 xa1af
#define mmSPI_PS_INPUT_CNTL_31 0 xa1b0
#define mmSPI_VS_OUT_CONFIG 0 xa1b1
#define mmSPI_PS_INPUT_ENA 0 xa1b3
#define mmSPI_PS_INPUT_ADDR 0 xa1b4
#define mmSPI_INTERP_CONTROL_0 0 xa1b5
#define mmSPI_PS_IN_CONTROL 0 xa1b6
#define mmSPI_BARYC_CNTL 0 xa1b8
#define mmSPI_TMPRING_SIZE 0 xa1ba
#define mmSPI_SHADER_POS_FORMAT 0 xa1c3
#define mmSPI_SHADER_Z_FORMAT 0 xa1c4
#define mmSPI_SHADER_COL_FORMAT 0 xa1c5
#define mmSPI_ARB_PRIORITY 0 x31c0
#define mmSPI_ARB_CYCLES_0 0 x31c1
#define mmSPI_ARB_CYCLES_1 0 x31c2
#define mmSPI_CDBG_SYS_GFX 0 x31c3
#define mmSPI_CDBG_SYS_HP3D 0 x31c4
#define mmSPI_CDBG_SYS_CS0 0 x31c5
#define mmSPI_CDBG_SYS_CS1 0 x31c6
#define mmSPI_WCL_PIPE_PERCENT_GFX 0 x31c7
#define mmSPI_WCL_PIPE_PERCENT_HP3D 0 x31c8
#define mmSPI_WCL_PIPE_PERCENT_CS0 0 x31c9
#define mmSPI_WCL_PIPE_PERCENT_CS1 0 x31ca
#define mmSPI_WCL_PIPE_PERCENT_CS2 0 x31cb
#define mmSPI_WCL_PIPE_PERCENT_CS3 0 x31cc
#define mmSPI_WCL_PIPE_PERCENT_CS4 0 x31cd
#define mmSPI_WCL_PIPE_PERCENT_CS5 0 x31ce
#define mmSPI_WCL_PIPE_PERCENT_CS6 0 x31cf
#define mmSPI_WCL_PIPE_PERCENT_CS7 0 x31d0
#define mmSPI_GDBG_WAVE_CNTL 0 x31d1
#define mmSPI_GDBG_TRAP_CONFIG 0 x31d2
#define mmSPI_GDBG_TRAP_MASK 0 x31d3
#define mmSPI_GDBG_TBA_LO 0 x31d4
#define mmSPI_GDBG_TBA_HI 0 x31d5
#define mmSPI_GDBG_TMA_LO 0 x31d6
#define mmSPI_GDBG_TMA_HI 0 x31d7
#define mmSPI_GDBG_TRAP_DATA0 0 x31d8
#define mmSPI_GDBG_TRAP_DATA1 0 x31d9
#define mmSPI_RESET_DEBUG 0 x31da
#define mmSPI_COMPUTE_QUEUE_RESET 0 x31db
#define mmSPI_RESOURCE_RESERVE_CU_0 0 x31dc
#define mmSPI_RESOURCE_RESERVE_CU_1 0 x31dd
#define mmSPI_RESOURCE_RESERVE_CU_2 0 x31de
#define mmSPI_RESOURCE_RESERVE_CU_3 0 x31df
#define mmSPI_RESOURCE_RESERVE_CU_4 0 x31e0
#define mmSPI_RESOURCE_RESERVE_CU_5 0 x31e1
#define mmSPI_RESOURCE_RESERVE_CU_6 0 x31e2
#define mmSPI_RESOURCE_RESERVE_CU_7 0 x31e3
#define mmSPI_RESOURCE_RESERVE_CU_8 0 x31e4
#define mmSPI_RESOURCE_RESERVE_CU_9 0 x31e5
#define mmSPI_RESOURCE_RESERVE_CU_10 0 x31f0
#define mmSPI_RESOURCE_RESERVE_CU_11 0 x31f1
#define mmSPI_RESOURCE_RESERVE_CU_12 0 x31f4
#define mmSPI_RESOURCE_RESERVE_CU_13 0 x31f5
#define mmSPI_RESOURCE_RESERVE_CU_14 0 x31f6
#define mmSPI_RESOURCE_RESERVE_CU_15 0 x31f7
#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0 x31e6
#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0 x31e7
#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0 x31e8
#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0 x31e9
#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0 x31ea
#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0 x31eb
#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0 x31ec
#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0 x31ed
#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0 x31ee
#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0 x31ef
#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0 x31f2
#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0 x31f3
#define mmSPI_RESOURCE_RESERVE_EN_CU_12 0 x31f8
#define mmSPI_RESOURCE_RESERVE_EN_CU_13 0 x31f9
#define mmSPI_RESOURCE_RESERVE_EN_CU_14 0 x31fa
#define mmSPI_RESOURCE_RESERVE_EN_CU_15 0 x31fb
#define mmSPI_COMPUTE_WF_CTX_SAVE 0 x31fc
#define mmSPI_PS_MAX_WAVE_ID 0 x243a
#define mmSPI_START_PHASE 0 x243b
#define mmSPI_GFX_CNTL 0 x243c
#define mmSPI_CONFIG_CNTL 0 x2440
#define mmSPI_DEBUG_CNTL 0 x2441
#define mmSPI_DEBUG_READ 0 x2442
#define mmSPI_DSM_CNTL 0 x2443
#define mmSPI_EDC_CNT 0 x2444
#define mmSPI_PERFCOUNTER0_SELECT 0 xd980
#define mmSPI_PERFCOUNTER1_SELECT 0 xd981
#define mmSPI_PERFCOUNTER2_SELECT 0 xd982
#define mmSPI_PERFCOUNTER3_SELECT 0 xd983
#define mmSPI_PERFCOUNTER0_SELECT1 0 xd984
#define mmSPI_PERFCOUNTER1_SELECT1 0 xd985
#define mmSPI_PERFCOUNTER2_SELECT1 0 xd986
#define mmSPI_PERFCOUNTER3_SELECT1 0 xd987
#define mmSPI_PERFCOUNTER4_SELECT 0 xd988
#define mmSPI_PERFCOUNTER5_SELECT 0 xd989
#define mmSPI_PERFCOUNTER_BINS 0 xd98a
#define mmSPI_PERFCOUNTER0_HI 0 xd180
#define mmSPI_PERFCOUNTER0_LO 0 xd181
#define mmSPI_PERFCOUNTER1_HI 0 xd182
#define mmSPI_PERFCOUNTER1_LO 0 xd183
#define mmSPI_PERFCOUNTER2_HI 0 xd184
#define mmSPI_PERFCOUNTER2_LO 0 xd185
#define mmSPI_PERFCOUNTER3_HI 0 xd186
#define mmSPI_PERFCOUNTER3_LO 0 xd187
#define mmSPI_PERFCOUNTER4_HI 0 xd188
#define mmSPI_PERFCOUNTER4_LO 0 xd189
#define mmSPI_PERFCOUNTER5_HI 0 xd18a
#define mmSPI_PERFCOUNTER5_LO 0 xd18b
#define mmSPI_CONFIG_CNTL_1 0 x244f
#define mmSPI_DEBUG_BUSY 0 x2450
#define mmSPI_CONFIG_CNTL_2 0 x2451
#define mmCGTS_SM_CTRL_REG 0 xf000
#define mmCGTS_RD_CTRL_REG 0 xf001
#define mmCGTS_RD_REG 0 xf002
#define mmCGTS_TCC_DISABLE 0 xf003
#define mmCGTS_USER_TCC_DISABLE 0 xf004
#define mmCGTS_CU0_SP0_CTRL_REG 0 xf008
#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0 xf009
#define mmCGTS_CU0_TA_SQC_CTRL_REG 0 xf00a
#define mmCGTS_CU0_SP1_CTRL_REG 0 xf00b
#define mmCGTS_CU0_TD_TCP_CTRL_REG 0 xf00c
#define mmCGTS_CU1_SP0_CTRL_REG 0 xf00d
#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0 xf00e
#define mmCGTS_CU1_TA_CTRL_REG 0 xf00f
#define mmCGTS_CU1_SP1_CTRL_REG 0 xf010
#define mmCGTS_CU1_TD_TCP_CTRL_REG 0 xf011
#define mmCGTS_CU2_SP0_CTRL_REG 0 xf012
#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0 xf013
#define mmCGTS_CU2_TA_CTRL_REG 0 xf014
#define mmCGTS_CU2_SP1_CTRL_REG 0 xf015
#define mmCGTS_CU2_TD_TCP_CTRL_REG 0 xf016
#define mmCGTS_CU3_SP0_CTRL_REG 0 xf017
#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0 xf018
#define mmCGTS_CU3_TA_CTRL_REG 0 xf019
#define mmCGTS_CU3_SP1_CTRL_REG 0 xf01a
#define mmCGTS_CU3_TD_TCP_CTRL_REG 0 xf01b
#define mmCGTS_CU4_SP0_CTRL_REG 0 xf01c
#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0 xf01d
#define mmCGTS_CU4_TA_SQC_CTRL_REG 0 xf01e
#define mmCGTS_CU4_SP1_CTRL_REG 0 xf01f
#define mmCGTS_CU4_TD_TCP_CTRL_REG 0 xf020
#define mmCGTS_CU5_SP0_CTRL_REG 0 xf021
#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0 xf022
#define mmCGTS_CU5_TA_CTRL_REG 0 xf023
#define mmCGTS_CU5_SP1_CTRL_REG 0 xf024
#define mmCGTS_CU5_TD_TCP_CTRL_REG 0 xf025
#define mmCGTS_CU6_SP0_CTRL_REG 0 xf026
#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0 xf027
#define mmCGTS_CU6_TA_CTRL_REG 0 xf028
#define mmCGTS_CU6_SP1_CTRL_REG 0 xf029
#define mmCGTS_CU6_TD_TCP_CTRL_REG 0 xf02a
#define mmCGTS_CU7_SP0_CTRL_REG 0 xf02b
#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0 xf02c
#define mmCGTS_CU7_TA_CTRL_REG 0 xf02d
#define mmCGTS_CU7_SP1_CTRL_REG 0 xf02e
#define mmCGTS_CU7_TD_TCP_CTRL_REG 0 xf02f
#define mmCGTS_CU8_SP0_CTRL_REG 0 xf030
#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0 xf031
#define mmCGTS_CU8_TA_SQC_CTRL_REG 0 xf032
#define mmCGTS_CU8_SP1_CTRL_REG 0 xf033
#define mmCGTS_CU8_TD_TCP_CTRL_REG 0 xf034
#define mmCGTS_CU9_SP0_CTRL_REG 0 xf035
#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0 xf036
#define mmCGTS_CU9_TA_CTRL_REG 0 xf037
#define mmCGTS_CU9_SP1_CTRL_REG 0 xf038
#define mmCGTS_CU9_TD_TCP_CTRL_REG 0 xf039
#define mmCGTS_CU10_SP0_CTRL_REG 0 xf03a
#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0 xf03b
#define mmCGTS_CU10_TA_CTRL_REG 0 xf03c
#define mmCGTS_CU10_SP1_CTRL_REG 0 xf03d
#define mmCGTS_CU10_TD_TCP_CTRL_REG 0 xf03e
#define mmCGTS_CU11_SP0_CTRL_REG 0 xf03f
#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0 xf040
#define mmCGTS_CU11_TA_CTRL_REG 0 xf041
#define mmCGTS_CU11_SP1_CTRL_REG 0 xf042
#define mmCGTS_CU11_TD_TCP_CTRL_REG 0 xf043
#define mmCGTS_CU12_SP0_CTRL_REG 0 xf044
#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0 xf045
#define mmCGTS_CU12_TA_SQC_CTRL_REG 0 xf046
#define mmCGTS_CU12_SP1_CTRL_REG 0 xf047
#define mmCGTS_CU12_TD_TCP_CTRL_REG 0 xf048
#define mmCGTS_CU13_SP0_CTRL_REG 0 xf049
#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0 xf04a
#define mmCGTS_CU13_TA_CTRL_REG 0 xf04b
#define mmCGTS_CU13_SP1_CTRL_REG 0 xf04c
#define mmCGTS_CU13_TD_TCP_CTRL_REG 0 xf04d
#define mmCGTS_CU14_SP0_CTRL_REG 0 xf04e
#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0 xf04f
#define mmCGTS_CU14_TA_CTRL_REG 0 xf050
#define mmCGTS_CU14_SP1_CTRL_REG 0 xf051
#define mmCGTS_CU14_TD_TCP_CTRL_REG 0 xf052
#define mmCGTS_CU15_SP0_CTRL_REG 0 xf053
#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0 xf054
#define mmCGTS_CU15_TA_CTRL_REG 0 xf055
#define mmCGTS_CU15_SP1_CTRL_REG 0 xf056
#define mmCGTS_CU15_TD_TCP_CTRL_REG 0 xf057
#define mmCGTT_SPI_CLK_CTRL 0 xf080
#define mmCGTT_PC_CLK_CTRL 0 xf081
#define mmCGTT_BCI_CLK_CTRL 0 xf082
#define mmSPI_WF_LIFETIME_CNTL 0 x24aa
#define mmSPI_WF_LIFETIME_LIMIT_0 0 x24ab
#define mmSPI_WF_LIFETIME_LIMIT_1 0 x24ac
#define mmSPI_WF_LIFETIME_LIMIT_2 0 x24ad
#define mmSPI_WF_LIFETIME_LIMIT_3 0 x24ae
#define mmSPI_WF_LIFETIME_LIMIT_4 0 x24af
#define mmSPI_WF_LIFETIME_LIMIT_5 0 x24b0
#define mmSPI_WF_LIFETIME_LIMIT_6 0 x24b1
#define mmSPI_WF_LIFETIME_LIMIT_7 0 x24b2
#define mmSPI_WF_LIFETIME_LIMIT_8 0 x24b3
#define mmSPI_WF_LIFETIME_LIMIT_9 0 x24b4
#define mmSPI_WF_LIFETIME_STATUS_0 0 x24b5
#define mmSPI_WF_LIFETIME_STATUS_1 0 x24b6
#define mmSPI_WF_LIFETIME_STATUS_2 0 x24b7
#define mmSPI_WF_LIFETIME_STATUS_3 0 x24b8
#define mmSPI_WF_LIFETIME_STATUS_4 0 x24b9
#define mmSPI_WF_LIFETIME_STATUS_5 0 x24ba
#define mmSPI_WF_LIFETIME_STATUS_6 0 x24bb
#define mmSPI_WF_LIFETIME_STATUS_7 0 x24bc
#define mmSPI_WF_LIFETIME_STATUS_8 0 x24bd
#define mmSPI_WF_LIFETIME_STATUS_9 0 x24be
#define mmSPI_WF_LIFETIME_STATUS_10 0 x24bf
#define mmSPI_WF_LIFETIME_STATUS_11 0 x24c0
#define mmSPI_WF_LIFETIME_STATUS_12 0 x24c1
#define mmSPI_WF_LIFETIME_STATUS_13 0 x24c2
#define mmSPI_WF_LIFETIME_STATUS_14 0 x24c3
#define mmSPI_WF_LIFETIME_STATUS_15 0 x24c4
#define mmSPI_WF_LIFETIME_STATUS_16 0 x24c5
#define mmSPI_WF_LIFETIME_STATUS_17 0 x24c6
#define mmSPI_WF_LIFETIME_STATUS_18 0 x24c7
#define mmSPI_WF_LIFETIME_STATUS_19 0 x24c8
#define mmSPI_WF_LIFETIME_STATUS_20 0 x24c9
#define mmSPI_WF_LIFETIME_DEBUG 0 x24ca
#define mmSPI_SLAVE_DEBUG_BUSY 0 x24d3
#define mmSPI_LB_CTR_CTRL 0 x24d4
#define mmSPI_LB_CU_MASK 0 x24d5
#define mmSPI_LB_DATA_REG 0 x24d6
#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0 x24d7
#define mmSPI_GDS_CREDITS 0 x24d8
#define mmSPI_SX_EXPORT_BUFFER_SIZES 0 x24d9
#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0 x24da
#define mmSPI_CSQ_WF_ACTIVE_STATUS 0 x24db
#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0 x24dc
#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0 x24dd
#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0 x24de
#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0 x24df
#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0 x24e0
#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0 x24e1
#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0 x24e2
#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0 x24e3
#define mmBCI_DEBUG_READ 0 x24eb
#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0 x24ec
#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0 x24ed
#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0 x24ee
#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0 x24ef
#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0 x24f0
#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0 x24f1
#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0 x24f2
#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0 x24f3
#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0 x24f4
#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0 x24f5
#define mmSPI_SHADER_TBA_LO_PS 0 x2c00
#define mmSPI_SHADER_TBA_HI_PS 0 x2c01
#define mmSPI_SHADER_TMA_LO_PS 0 x2c02
#define mmSPI_SHADER_TMA_HI_PS 0 x2c03
#define mmSPI_SHADER_PGM_LO_PS 0 x2c08
#define mmSPI_SHADER_PGM_HI_PS 0 x2c09
#define mmSPI_SHADER_PGM_RSRC1_PS 0 x2c0a
#define mmSPI_SHADER_PGM_RSRC2_PS 0 x2c0b
#define mmSPI_SHADER_PGM_RSRC3_PS 0 x2c07
#define mmSPI_SHADER_USER_DATA_PS_0 0 x2c0c
#define mmSPI_SHADER_USER_DATA_PS_1 0 x2c0d
#define mmSPI_SHADER_USER_DATA_PS_2 0 x2c0e
#define mmSPI_SHADER_USER_DATA_PS_3 0 x2c0f
#define mmSPI_SHADER_USER_DATA_PS_4 0 x2c10
#define mmSPI_SHADER_USER_DATA_PS_5 0 x2c11
#define mmSPI_SHADER_USER_DATA_PS_6 0 x2c12
#define mmSPI_SHADER_USER_DATA_PS_7 0 x2c13
#define mmSPI_SHADER_USER_DATA_PS_8 0 x2c14
#define mmSPI_SHADER_USER_DATA_PS_9 0 x2c15
#define mmSPI_SHADER_USER_DATA_PS_10 0 x2c16
#define mmSPI_SHADER_USER_DATA_PS_11 0 x2c17
#define mmSPI_SHADER_USER_DATA_PS_12 0 x2c18
#define mmSPI_SHADER_USER_DATA_PS_13 0 x2c19
#define mmSPI_SHADER_USER_DATA_PS_14 0 x2c1a
#define mmSPI_SHADER_USER_DATA_PS_15 0 x2c1b
#define mmSPI_SHADER_TBA_LO_VS 0 x2c40
#define mmSPI_SHADER_TBA_HI_VS 0 x2c41
#define mmSPI_SHADER_TMA_LO_VS 0 x2c42
#define mmSPI_SHADER_TMA_HI_VS 0 x2c43
#define mmSPI_SHADER_PGM_LO_VS 0 x2c48
#define mmSPI_SHADER_PGM_HI_VS 0 x2c49
#define mmSPI_SHADER_PGM_RSRC1_VS 0 x2c4a
#define mmSPI_SHADER_PGM_RSRC2_VS 0 x2c4b
#define mmSPI_SHADER_PGM_RSRC3_VS 0 x2c46
#define mmSPI_SHADER_LATE_ALLOC_VS 0 x2c47
#define mmSPI_SHADER_USER_DATA_VS_0 0 x2c4c
#define mmSPI_SHADER_USER_DATA_VS_1 0 x2c4d
#define mmSPI_SHADER_USER_DATA_VS_2 0 x2c4e
#define mmSPI_SHADER_USER_DATA_VS_3 0 x2c4f
#define mmSPI_SHADER_USER_DATA_VS_4 0 x2c50
#define mmSPI_SHADER_USER_DATA_VS_5 0 x2c51
#define mmSPI_SHADER_USER_DATA_VS_6 0 x2c52
#define mmSPI_SHADER_USER_DATA_VS_7 0 x2c53
#define mmSPI_SHADER_USER_DATA_VS_8 0 x2c54
#define mmSPI_SHADER_USER_DATA_VS_9 0 x2c55
#define mmSPI_SHADER_USER_DATA_VS_10 0 x2c56
#define mmSPI_SHADER_USER_DATA_VS_11 0 x2c57
#define mmSPI_SHADER_USER_DATA_VS_12 0 x2c58
#define mmSPI_SHADER_USER_DATA_VS_13 0 x2c59
#define mmSPI_SHADER_USER_DATA_VS_14 0 x2c5a
#define mmSPI_SHADER_USER_DATA_VS_15 0 x2c5b
#define mmSPI_SHADER_PGM_RSRC2_ES_VS 0 x2c7c
#define mmSPI_SHADER_PGM_RSRC2_LS_VS 0 x2c7d
#define mmSPI_SHADER_TBA_LO_GS 0 x2c80
#define mmSPI_SHADER_TBA_HI_GS 0 x2c81
#define mmSPI_SHADER_TMA_LO_GS 0 x2c82
#define mmSPI_SHADER_TMA_HI_GS 0 x2c83
#define mmSPI_SHADER_PGM_LO_GS 0 x2c88
#define mmSPI_SHADER_PGM_HI_GS 0 x2c89
#define mmSPI_SHADER_PGM_RSRC1_GS 0 x2c8a
#define mmSPI_SHADER_PGM_RSRC2_GS 0 x2c8b
#define mmSPI_SHADER_PGM_RSRC3_GS 0 x2c87
#define mmSPI_SHADER_USER_DATA_GS_0 0 x2c8c
#define mmSPI_SHADER_USER_DATA_GS_1 0 x2c8d
#define mmSPI_SHADER_USER_DATA_GS_2 0 x2c8e
#define mmSPI_SHADER_USER_DATA_GS_3 0 x2c8f
#define mmSPI_SHADER_USER_DATA_GS_4 0 x2c90
#define mmSPI_SHADER_USER_DATA_GS_5 0 x2c91
#define mmSPI_SHADER_USER_DATA_GS_6 0 x2c92
#define mmSPI_SHADER_USER_DATA_GS_7 0 x2c93
#define mmSPI_SHADER_USER_DATA_GS_8 0 x2c94
#define mmSPI_SHADER_USER_DATA_GS_9 0 x2c95
#define mmSPI_SHADER_USER_DATA_GS_10 0 x2c96
#define mmSPI_SHADER_USER_DATA_GS_11 0 x2c97
#define mmSPI_SHADER_USER_DATA_GS_12 0 x2c98
#define mmSPI_SHADER_USER_DATA_GS_13 0 x2c99
#define mmSPI_SHADER_USER_DATA_GS_14 0 x2c9a
#define mmSPI_SHADER_USER_DATA_GS_15 0 x2c9b
#define mmSPI_SHADER_PGM_RSRC2_ES_GS 0 x2cbc
#define mmSPI_SHADER_TBA_LO_ES 0 x2cc0
#define mmSPI_SHADER_TBA_HI_ES 0 x2cc1
#define mmSPI_SHADER_TMA_LO_ES 0 x2cc2
#define mmSPI_SHADER_TMA_HI_ES 0 x2cc3
#define mmSPI_SHADER_PGM_LO_ES 0 x2cc8
#define mmSPI_SHADER_PGM_HI_ES 0 x2cc9
#define mmSPI_SHADER_PGM_RSRC1_ES 0 x2cca
#define mmSPI_SHADER_PGM_RSRC2_ES 0 x2ccb
#define mmSPI_SHADER_PGM_RSRC3_ES 0 x2cc7
#define mmSPI_SHADER_USER_DATA_ES_0 0 x2ccc
#define mmSPI_SHADER_USER_DATA_ES_1 0 x2ccd
#define mmSPI_SHADER_USER_DATA_ES_2 0 x2cce
#define mmSPI_SHADER_USER_DATA_ES_3 0 x2ccf
#define mmSPI_SHADER_USER_DATA_ES_4 0 x2cd0
#define mmSPI_SHADER_USER_DATA_ES_5 0 x2cd1
#define mmSPI_SHADER_USER_DATA_ES_6 0 x2cd2
#define mmSPI_SHADER_USER_DATA_ES_7 0 x2cd3
#define mmSPI_SHADER_USER_DATA_ES_8 0 x2cd4
#define mmSPI_SHADER_USER_DATA_ES_9 0 x2cd5
#define mmSPI_SHADER_USER_DATA_ES_10 0 x2cd6
#define mmSPI_SHADER_USER_DATA_ES_11 0 x2cd7
#define mmSPI_SHADER_USER_DATA_ES_12 0 x2cd8
#define mmSPI_SHADER_USER_DATA_ES_13 0 x2cd9
#define mmSPI_SHADER_USER_DATA_ES_14 0 x2cda
#define mmSPI_SHADER_USER_DATA_ES_15 0 x2cdb
#define mmSPI_SHADER_PGM_RSRC2_LS_ES 0 x2cfd
#define mmSPI_SHADER_TBA_LO_HS 0 x2d00
#define mmSPI_SHADER_TBA_HI_HS 0 x2d01
#define mmSPI_SHADER_TMA_LO_HS 0 x2d02
#define mmSPI_SHADER_TMA_HI_HS 0 x2d03
#define mmSPI_SHADER_PGM_LO_HS 0 x2d08
#define mmSPI_SHADER_PGM_HI_HS 0 x2d09
#define mmSPI_SHADER_PGM_RSRC1_HS 0 x2d0a
#define mmSPI_SHADER_PGM_RSRC2_HS 0 x2d0b
#define mmSPI_SHADER_PGM_RSRC3_HS 0 x2d07
#define mmSPI_SHADER_USER_DATA_HS_0 0 x2d0c
#define mmSPI_SHADER_USER_DATA_HS_1 0 x2d0d
#define mmSPI_SHADER_USER_DATA_HS_2 0 x2d0e
#define mmSPI_SHADER_USER_DATA_HS_3 0 x2d0f
#define mmSPI_SHADER_USER_DATA_HS_4 0 x2d10
#define mmSPI_SHADER_USER_DATA_HS_5 0 x2d11
#define mmSPI_SHADER_USER_DATA_HS_6 0 x2d12
#define mmSPI_SHADER_USER_DATA_HS_7 0 x2d13
#define mmSPI_SHADER_USER_DATA_HS_8 0 x2d14
#define mmSPI_SHADER_USER_DATA_HS_9 0 x2d15
#define mmSPI_SHADER_USER_DATA_HS_10 0 x2d16
#define mmSPI_SHADER_USER_DATA_HS_11 0 x2d17
#define mmSPI_SHADER_USER_DATA_HS_12 0 x2d18
#define mmSPI_SHADER_USER_DATA_HS_13 0 x2d19
#define mmSPI_SHADER_USER_DATA_HS_14 0 x2d1a
#define mmSPI_SHADER_USER_DATA_HS_15 0 x2d1b
#define mmSPI_SHADER_PGM_RSRC2_LS_HS 0 x2d3d
#define mmSPI_SHADER_TBA_LO_LS 0 x2d40
#define mmSPI_SHADER_TBA_HI_LS 0 x2d41
#define mmSPI_SHADER_TMA_LO_LS 0 x2d42
#define mmSPI_SHADER_TMA_HI_LS 0 x2d43
#define mmSPI_SHADER_PGM_LO_LS 0 x2d48
#define mmSPI_SHADER_PGM_HI_LS 0 x2d49
#define mmSPI_SHADER_PGM_RSRC1_LS 0 x2d4a
#define mmSPI_SHADER_PGM_RSRC2_LS 0 x2d4b
#define mmSPI_SHADER_PGM_RSRC3_LS 0 x2d47
#define mmSPI_SHADER_USER_DATA_LS_0 0 x2d4c
#define mmSPI_SHADER_USER_DATA_LS_1 0 x2d4d
#define mmSPI_SHADER_USER_DATA_LS_2 0 x2d4e
#define mmSPI_SHADER_USER_DATA_LS_3 0 x2d4f
#define mmSPI_SHADER_USER_DATA_LS_4 0 x2d50
#define mmSPI_SHADER_USER_DATA_LS_5 0 x2d51
#define mmSPI_SHADER_USER_DATA_LS_6 0 x2d52
#define mmSPI_SHADER_USER_DATA_LS_7 0 x2d53
#define mmSPI_SHADER_USER_DATA_LS_8 0 x2d54
#define mmSPI_SHADER_USER_DATA_LS_9 0 x2d55
#define mmSPI_SHADER_USER_DATA_LS_10 0 x2d56
#define mmSPI_SHADER_USER_DATA_LS_11 0 x2d57
#define mmSPI_SHADER_USER_DATA_LS_12 0 x2d58
#define mmSPI_SHADER_USER_DATA_LS_13 0 x2d59
#define mmSPI_SHADER_USER_DATA_LS_14 0 x2d5a
#define mmSPI_SHADER_USER_DATA_LS_15 0 x2d5b
#define mmSQ_CONFIG 0 x2300
#define mmSQC_CONFIG 0 x2301
#define mmSQC_CACHES 0 xc348
#define mmSQC_WRITEBACK 0 xc349
#define mmSQC_DSM_CNTL 0 x230f
#define mmSQ_RANDOM_WAVE_PRI 0 x2303
#define mmSQ_REG_CREDITS 0 x2304
#define mmSQ_FIFO_SIZES 0 x2305
#define mmSQ_DSM_CNTL 0 x2306
#define mmCC_GC_SHADER_RATE_CONFIG 0 x2312
#define mmGC_USER_SHADER_RATE_CONFIG 0 x2313
#define mmSQ_INTERRUPT_AUTO_MASK 0 x2314
#define mmSQ_INTERRUPT_MSG_CTRL 0 x2315
#define mmSQ_PERFCOUNTER_CTRL 0 xd9e0
#define mmSQ_PERFCOUNTER_MASK 0 xd9e1
#define mmSQ_PERFCOUNTER_CTRL2 0 xd9e2
#define mmCC_SQC_BANK_DISABLE 0 x2307
#define mmUSER_SQC_BANK_DISABLE 0 x2308
#define mmSQ_PERFCOUNTER0_LO 0 xd1c0
#define mmSQ_PERFCOUNTER1_LO 0 xd1c2
#define mmSQ_PERFCOUNTER2_LO 0 xd1c4
#define mmSQ_PERFCOUNTER3_LO 0 xd1c6
#define mmSQ_PERFCOUNTER4_LO 0 xd1c8
#define mmSQ_PERFCOUNTER5_LO 0 xd1ca
#define mmSQ_PERFCOUNTER6_LO 0 xd1cc
#define mmSQ_PERFCOUNTER7_LO 0 xd1ce
#define mmSQ_PERFCOUNTER8_LO 0 xd1d0
#define mmSQ_PERFCOUNTER9_LO 0 xd1d2
#define mmSQ_PERFCOUNTER10_LO 0 xd1d4
#define mmSQ_PERFCOUNTER11_LO 0 xd1d6
#define mmSQ_PERFCOUNTER12_LO 0 xd1d8
#define mmSQ_PERFCOUNTER13_LO 0 xd1da
#define mmSQ_PERFCOUNTER14_LO 0 xd1dc
#define mmSQ_PERFCOUNTER15_LO 0 xd1de
#define mmSQ_PERFCOUNTER0_HI 0 xd1c1
#define mmSQ_PERFCOUNTER1_HI 0 xd1c3
#define mmSQ_PERFCOUNTER2_HI 0 xd1c5
#define mmSQ_PERFCOUNTER3_HI 0 xd1c7
#define mmSQ_PERFCOUNTER4_HI 0 xd1c9
#define mmSQ_PERFCOUNTER5_HI 0 xd1cb
#define mmSQ_PERFCOUNTER6_HI 0 xd1cd
#define mmSQ_PERFCOUNTER7_HI 0 xd1cf
#define mmSQ_PERFCOUNTER8_HI 0 xd1d1
#define mmSQ_PERFCOUNTER9_HI 0 xd1d3
#define mmSQ_PERFCOUNTER10_HI 0 xd1d5
#define mmSQ_PERFCOUNTER11_HI 0 xd1d7
#define mmSQ_PERFCOUNTER12_HI 0 xd1d9
#define mmSQ_PERFCOUNTER13_HI 0 xd1db
#define mmSQ_PERFCOUNTER14_HI 0 xd1dd
#define mmSQ_PERFCOUNTER15_HI 0 xd1df
#define mmSQ_PERFCOUNTER0_SELECT 0 xd9c0
#define mmSQ_PERFCOUNTER1_SELECT 0 xd9c1
#define mmSQ_PERFCOUNTER2_SELECT 0 xd9c2
#define mmSQ_PERFCOUNTER3_SELECT 0 xd9c3
#define mmSQ_PERFCOUNTER4_SELECT 0 xd9c4
#define mmSQ_PERFCOUNTER5_SELECT 0 xd9c5
#define mmSQ_PERFCOUNTER6_SELECT 0 xd9c6
#define mmSQ_PERFCOUNTER7_SELECT 0 xd9c7
#define mmSQ_PERFCOUNTER8_SELECT 0 xd9c8
#define mmSQ_PERFCOUNTER9_SELECT 0 xd9c9
#define mmSQ_PERFCOUNTER10_SELECT 0 xd9ca
#define mmSQ_PERFCOUNTER11_SELECT 0 xd9cb
#define mmSQ_PERFCOUNTER12_SELECT 0 xd9cc
#define mmSQ_PERFCOUNTER13_SELECT 0 xd9cd
#define mmSQ_PERFCOUNTER14_SELECT 0 xd9ce
#define mmSQ_PERFCOUNTER15_SELECT 0 xd9cf
#define mmCGTT_SQ_CLK_CTRL 0 xf08c
#define mmCGTT_SQG_CLK_CTRL 0 xf08d
#define mmSQ_ALU_CLK_CTRL 0 xf08e
#define mmSQ_TEX_CLK_CTRL 0 xf08f
#define mmSQ_LDS_CLK_CTRL 0 xf090
#define mmSQ_POWER_THROTTLE 0 xf091
#define mmSQ_POWER_THROTTLE2 0 xf092
#define mmSQ_TIME_HI 0 x237c
#define mmSQ_TIME_LO 0 x237d
#define mmSQ_THREAD_TRACE_BASE 0 xc330
#define mmSQ_THREAD_TRACE_BASE2 0 xc337
#define mmSQ_THREAD_TRACE_SIZE 0 xc331
#define mmSQ_THREAD_TRACE_MASK 0 xc332
#define mmSQ_THREAD_TRACE_USERDATA_0 0 xc340
#define mmSQ_THREAD_TRACE_USERDATA_1 0 xc341
#define mmSQ_THREAD_TRACE_USERDATA_2 0 xc342
#define mmSQ_THREAD_TRACE_USERDATA_3 0 xc343
#define mmSQ_THREAD_TRACE_MODE 0 xc336
#define mmSQ_THREAD_TRACE_CTRL 0 xc335
#define mmSQ_THREAD_TRACE_TOKEN_MASK 0 xc333
#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0 xc338
#define mmSQ_THREAD_TRACE_PERF_MASK 0 xc334
#define mmSQ_THREAD_TRACE_WPTR 0 xc339
#define mmSQ_THREAD_TRACE_STATUS 0 xc33a
#define mmSQ_THREAD_TRACE_CNTR 0 x2390
#define mmSQ_THREAD_TRACE_HIWATER 0 xc33b
#define mmSQ_LB_CTR_CTRL 0 x2398
#define mmSQ_LB_DATA_ALU_CYCLES 0 x2399
#define mmSQ_LB_DATA_TEX_CYCLES 0 x239a
#define mmSQ_LB_DATA_ALU_STALLS 0 x239b
#define mmSQ_LB_DATA_TEX_STALLS 0 x239c
#define mmSQC_EDC_CNT 0 x23a0
#define mmSQ_EDC_SEC_CNT 0 x23a1
#define mmSQ_EDC_DED_CNT 0 x23a2
#define mmSQ_EDC_INFO 0 x23a3
#define mmSQ_BUF_RSRC_WORD0 0 x23c0
#define mmSQ_BUF_RSRC_WORD1 0 x23c1
#define mmSQ_BUF_RSRC_WORD2 0 x23c2
#define mmSQ_BUF_RSRC_WORD3 0 x23c3
#define mmSQ_IMG_RSRC_WORD0 0 x23c4
#define mmSQ_IMG_RSRC_WORD1 0 x23c5
#define mmSQ_IMG_RSRC_WORD2 0 x23c6
#define mmSQ_IMG_RSRC_WORD3 0 x23c7
#define mmSQ_IMG_RSRC_WORD4 0 x23c8
#define mmSQ_IMG_RSRC_WORD5 0 x23c9
#define mmSQ_IMG_RSRC_WORD6 0 x23ca
#define mmSQ_IMG_RSRC_WORD7 0 x23cb
#define mmSQ_IMG_SAMP_WORD0 0 x23cc
#define mmSQ_IMG_SAMP_WORD1 0 x23cd
#define mmSQ_IMG_SAMP_WORD2 0 x23ce
#define mmSQ_IMG_SAMP_WORD3 0 x23cf
#define mmSQ_FLAT_SCRATCH_WORD0 0 x23d0
#define mmSQ_FLAT_SCRATCH_WORD1 0 x23d1
#define mmSQ_M0_GPR_IDX_WORD 0 x23d2
#define mmSQ_IND_INDEX 0 x2378
#define mmSQ_CMD 0 x237b
#define mmSQ_IND_DATA 0 x2379
#define mmSQ_REG_TIMESTAMP 0 x2374
#define mmSQ_CMD_TIMESTAMP 0 x2375
#define mmSQ_HV_VMID_CTRL 0 xf840
#define ixSQ_WAVE_INST_DW0 0 x1a
#define ixSQ_WAVE_INST_DW1 0 x1b
#define ixSQ_WAVE_PC_LO 0 x18
#define ixSQ_WAVE_PC_HI 0 x19
#define ixSQ_WAVE_IB_DBG0 0 x1c
#define ixSQ_WAVE_IB_DBG1 0 x1d
#define ixSQ_WAVE_EXEC_LO 0 x27e
#define ixSQ_WAVE_EXEC_HI 0 x27f
#define ixSQ_WAVE_STATUS 0 x12
#define ixSQ_WAVE_MODE 0 x11
#define ixSQ_WAVE_TRAPSTS 0 x13
#define ixSQ_WAVE_HW_ID 0 x14
#define ixSQ_WAVE_GPR_ALLOC 0 x15
#define ixSQ_WAVE_LDS_ALLOC 0 x16
#define ixSQ_WAVE_IB_STS 0 x17
#define ixSQ_WAVE_M0 0 x27c
#define ixSQ_WAVE_TBA_LO 0 x26c
#define ixSQ_WAVE_TBA_HI 0 x26d
#define ixSQ_WAVE_TMA_LO 0 x26e
#define ixSQ_WAVE_TMA_HI 0 x26f
#define ixSQ_WAVE_TTMP0 0 x270
#define ixSQ_WAVE_TTMP1 0 x271
#define ixSQ_WAVE_TTMP2 0 x272
#define ixSQ_WAVE_TTMP3 0 x273
#define ixSQ_WAVE_TTMP4 0 x274
#define ixSQ_WAVE_TTMP5 0 x275
#define ixSQ_WAVE_TTMP6 0 x276
#define ixSQ_WAVE_TTMP7 0 x277
#define ixSQ_WAVE_TTMP8 0 x278
#define ixSQ_WAVE_TTMP9 0 x279
#define ixSQ_WAVE_TTMP10 0 x27a
#define ixSQ_WAVE_TTMP11 0 x27b
#define mmSQ_DEBUG_STS_GLOBAL 0 x2309
#define mmSQ_DEBUG_STS_GLOBAL2 0 x2310
#define mmSQ_DEBUG_STS_GLOBAL3 0 x2311
#define ixSQ_DEBUG_STS_LOCAL 0 x8
#define ixSQ_DEBUG_CTRL_LOCAL 0 x9
#define mmSH_MEM_BASES 0 x230a
#define mmSH_MEM_APE1_BASE 0 x230b
#define mmSH_MEM_APE1_LIMIT 0 x230c
#define mmSH_MEM_CONFIG 0 x230d
#define mmSQ_THREAD_TRACE_WORD_CMN 0 x23b0
#define mmSQ_THREAD_TRACE_WORD_INST 0 x23b0
#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0 x23b0
#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0 x23b1
#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0 x23b0
#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0 x23b1
#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0 x23b0
#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0 x23b1
#define mmSQ_THREAD_TRACE_WORD_WAVE 0 x23b0
#define mmSQ_THREAD_TRACE_WORD_MISC 0 x23b0
#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0 x23b0
#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0 x23b0
#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0 x23b0
#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0 x23b0
#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0 x23b0
#define mmSQ_THREAD_TRACE_WORD_EVENT 0 x23b0
#define mmSQ_THREAD_TRACE_WORD_ISSUE 0 x23b0
#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0 x23b0
#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0 x23b1
#define mmSQ_WREXEC_EXEC_LO 0 x23b1
#define mmSQ_WREXEC_EXEC_HI 0 x23b1
#define mmSQC_GATCL1_CNTL 0 x23b2
#define mmSQC_ATC_EDC_GATCL1_CNT 0 x23b3
#define ixSQ_INTERRUPT_WORD_CMN 0 x20c0
#define ixSQ_INTERRUPT_WORD_AUTO 0 x20c0
#define ixSQ_INTERRUPT_WORD_WAVE 0 x20c0
#define mmSQ_SOP2 0 x237f
#define mmSQ_VOP1 0 x237f
#define mmSQ_MTBUF_1 0 x237f
#define mmSQ_EXP_1 0 x237f
#define mmSQ_MUBUF_1 0 x237f
#define mmSQ_SMEM_1 0 x237f
#define mmSQ_INST 0 x237f
#define mmSQ_EXP_0 0 x237f
#define mmSQ_MUBUF_0 0 x237f
#define mmSQ_VOP_SDWA 0 x237f
#define mmSQ_VOP3_0 0 x237f
#define mmSQ_VOP2 0 x237f
#define mmSQ_MTBUF_0 0 x237f
#define mmSQ_SOPP 0 x237f
#define mmSQ_FLAT_0 0 x237f
#define mmSQ_VOP3_0_SDST_ENC 0 x237f
#define mmSQ_MIMG_1 0 x237f
#define mmSQ_SOP1 0 x237f
#define mmSQ_SOPC 0 x237f
#define mmSQ_FLAT_1 0 x237f
#define mmSQ_DS_1 0 x237f
#define mmSQ_VOP3_1 0 x237f
#define mmSQ_SMEM_0 0 x237f
#define mmSQ_MIMG_0 0 x237f
#define mmSQ_SOPK 0 x237f
#define mmSQ_DS_0 0 x237f
#define mmSQ_VOP_DPP 0 x237f
#define mmSQ_VOPC 0 x237f
#define mmSQ_VINTRP 0 x237f
#define mmCGTT_SX_CLK_CTRL0 0 xf094
#define mmCGTT_SX_CLK_CTRL1 0 xf095
#define mmCGTT_SX_CLK_CTRL2 0 xf096
#define mmCGTT_SX_CLK_CTRL3 0 xf097
#define mmCGTT_SX_CLK_CTRL4 0 xf098
#define mmSX_DEBUG_BUSY 0 x2414
#define mmSX_DEBUG_BUSY_2 0 x2415
#define mmSX_DEBUG_BUSY_3 0 x2416
#define mmSX_DEBUG_BUSY_4 0 x2417
#define mmSX_DEBUG_1 0 x2418
#define mmSX_PERFCOUNTER0_SELECT 0 xda40
#define mmSX_PERFCOUNTER1_SELECT 0 xda41
#define mmSX_PERFCOUNTER2_SELECT 0 xda42
#define mmSX_PERFCOUNTER3_SELECT 0 xda43
#define mmSX_PERFCOUNTER0_SELECT1 0 xda44
#define mmSX_PERFCOUNTER1_SELECT1 0 xda45
#define mmSX_PERFCOUNTER0_LO 0 xd240
#define mmSX_PERFCOUNTER0_HI 0 xd241
#define mmSX_PERFCOUNTER1_LO 0 xd242
#define mmSX_PERFCOUNTER1_HI 0 xd243
#define mmSX_PERFCOUNTER2_LO 0 xd244
#define mmSX_PERFCOUNTER2_HI 0 xd245
#define mmSX_PERFCOUNTER3_LO 0 xd246
#define mmSX_PERFCOUNTER3_HI 0 xd247
#define mmSX_PS_DOWNCONVERT 0 xa1d5
#define mmSX_BLEND_OPT_EPSILON 0 xa1d6
#define mmSX_BLEND_OPT_CONTROL 0 xa1d7
#define mmSX_MRT0_BLEND_OPT 0 xa1d8
#define mmSX_MRT1_BLEND_OPT 0 xa1d9
#define mmSX_MRT2_BLEND_OPT 0 xa1da
#define mmSX_MRT3_BLEND_OPT 0 xa1db
#define mmSX_MRT4_BLEND_OPT 0 xa1dc
#define mmSX_MRT5_BLEND_OPT 0 xa1dd
#define mmSX_MRT6_BLEND_OPT 0 xa1de
#define mmSX_MRT7_BLEND_OPT 0 xa1df
#define mmTCC_CTRL 0 x2b80
#define mmTCC_EDC_CNT 0 x2b82
#define mmTCC_REDUNDANCY 0 x2b83
#define mmTCC_EXE_DISABLE 0 x2b84
#define mmTCC_DSM_CNTL 0 x2b85
#define mmTCC_CGTT_SCLK_CTRL 0 xf0ac
#define mmTCA_CGTT_SCLK_CTRL 0 xf0ad
#define mmTCC_PERFCOUNTER0_SELECT 0 xdb80
#define mmTCC_PERFCOUNTER1_SELECT 0 xdb82
#define mmTCC_PERFCOUNTER0_SELECT1 0 xdb81
#define mmTCC_PERFCOUNTER1_SELECT1 0 xdb83
#define mmTCC_PERFCOUNTER2_SELECT 0 xdb84
#define mmTCC_PERFCOUNTER3_SELECT 0 xdb85
#define mmTCC_PERFCOUNTER0_LO 0 xd380
#define mmTCC_PERFCOUNTER1_LO 0 xd382
#define mmTCC_PERFCOUNTER2_LO 0 xd384
#define mmTCC_PERFCOUNTER3_LO 0 xd386
#define mmTCC_PERFCOUNTER0_HI 0 xd381
#define mmTCC_PERFCOUNTER1_HI 0 xd383
#define mmTCC_PERFCOUNTER2_HI 0 xd385
#define mmTCC_PERFCOUNTER3_HI 0 xd387
#define mmTCA_CTRL 0 x2bc0
#define mmTCA_PERFCOUNTER0_SELECT 0 xdb90
#define mmTCA_PERFCOUNTER1_SELECT 0 xdb92
#define mmTCA_PERFCOUNTER0_SELECT1 0 xdb91
#define mmTCA_PERFCOUNTER1_SELECT1 0 xdb93
#define mmTCA_PERFCOUNTER2_SELECT 0 xdb94
#define mmTCA_PERFCOUNTER3_SELECT 0 xdb95
#define mmTCA_PERFCOUNTER0_LO 0 xd390
#define mmTCA_PERFCOUNTER1_LO 0 xd392
#define mmTCA_PERFCOUNTER2_LO 0 xd394
#define mmTCA_PERFCOUNTER3_LO 0 xd396
#define mmTCA_PERFCOUNTER0_HI 0 xd391
#define mmTCA_PERFCOUNTER1_HI 0 xd393
#define mmTCA_PERFCOUNTER2_HI 0 xd395
#define mmTCA_PERFCOUNTER3_HI 0 xd397
#define mmTA_BC_BASE_ADDR 0 xa020
#define mmTA_BC_BASE_ADDR_HI 0 xa021
#define mmTD_CNTL 0 x2525
#define mmTD_STATUS 0 x2526
#define mmTD_DEBUG_INDEX 0 x2528
#define mmTD_DEBUG_DATA 0 x2529
#define mmTD_DSM_CNTL 0 x252f
#define mmTD_PERFCOUNTER0_SELECT 0 xdb00
#define mmTD_PERFCOUNTER1_SELECT 0 xdb02
#define mmTD_PERFCOUNTER0_SELECT1 0 xdb01
#define mmTD_PERFCOUNTER0_LO 0 xd300
#define mmTD_PERFCOUNTER1_LO 0 xd302
#define mmTD_PERFCOUNTER0_HI 0 xd301
#define mmTD_PERFCOUNTER1_HI 0 xd303
#define mmTD_SCRATCH 0 x2533
#define mmTA_CNTL 0 x2541
#define mmTA_CNTL_AUX 0 x2542
#define mmTA_RESERVED_010C 0 x2543
#define mmTA_CS_BC_BASE_ADDR 0 xc380
#define mmTA_CS_BC_BASE_ADDR_HI 0 xc381
#define mmTA_STATUS 0 x2548
#define mmTA_DEBUG_INDEX 0 x254c
#define mmTA_DEBUG_DATA 0 x254d
#define mmTA_PERFCOUNTER0_SELECT 0 xdac0
#define mmTA_PERFCOUNTER1_SELECT 0 xdac2
#define mmTA_PERFCOUNTER0_SELECT1 0 xdac1
#define mmTA_PERFCOUNTER0_LO 0 xd2c0
#define mmTA_PERFCOUNTER1_LO 0 xd2c2
#define mmTA_PERFCOUNTER0_HI 0 xd2c1
#define mmTA_PERFCOUNTER1_HI 0 xd2c3
#define mmTA_SCRATCH 0 x2564
#define mmSH_HIDDEN_PRIVATE_BASE_VMID 0 x2580
#define mmSH_STATIC_MEM_CONFIG 0 x2581
#define mmTCP_INVALIDATE 0 x2b00
#define mmTCP_STATUS 0 x2b01
#define mmTCP_CNTL 0 x2b02
#define mmTCP_CHAN_STEER_LO 0 x2b03
#define mmTCP_CHAN_STEER_HI 0 x2b04
#define mmTCP_ADDR_CONFIG 0 x2b05
#define mmTCP_CREDIT 0 x2b06
#define mmTCP_PERFCOUNTER0_SELECT 0 xdb40
#define mmTCP_PERFCOUNTER1_SELECT 0 xdb42
#define mmTCP_PERFCOUNTER0_SELECT1 0 xdb41
#define mmTCP_PERFCOUNTER1_SELECT1 0 xdb43
#define mmTCP_PERFCOUNTER2_SELECT 0 xdb44
#define mmTCP_PERFCOUNTER3_SELECT 0 xdb45
#define mmTCP_PERFCOUNTER0_LO 0 xd340
#define mmTCP_PERFCOUNTER1_LO 0 xd342
#define mmTCP_PERFCOUNTER2_LO 0 xd344
#define mmTCP_PERFCOUNTER3_LO 0 xd346
#define mmTCP_PERFCOUNTER0_HI 0 xd341
#define mmTCP_PERFCOUNTER1_HI 0 xd343
#define mmTCP_PERFCOUNTER2_HI 0 xd345
#define mmTCP_PERFCOUNTER3_HI 0 xd347
#define mmTCP_BUFFER_ADDR_HASH_CNTL 0 x2b16
#define mmTCP_EDC_CNT 0 x2b17
#define mmTC_CFG_L1_LOAD_POLICY0 0 x2b1a
#define mmTC_CFG_L1_LOAD_POLICY1 0 x2b1b
#define mmTC_CFG_L1_STORE_POLICY 0 x2b1c
#define mmTC_CFG_L2_LOAD_POLICY0 0 x2b1d
#define mmTC_CFG_L2_LOAD_POLICY1 0 x2b1e
#define mmTC_CFG_L2_STORE_POLICY0 0 x2b1f
#define mmTC_CFG_L2_STORE_POLICY1 0 x2b20
#define mmTC_CFG_L2_ATOMIC_POLICY 0 x2b21
#define mmTC_CFG_L1_VOLATILE 0 x2b22
#define mmTC_CFG_L2_VOLATILE 0 x2b23
#define mmTCP_WATCH0_ADDR_H 0 x32a0
#define mmTCP_WATCH1_ADDR_H 0 x32a3
#define mmTCP_WATCH2_ADDR_H 0 x32a6
#define mmTCP_WATCH3_ADDR_H 0 x32a9
#define mmTCP_WATCH0_ADDR_L 0 x32a1
#define mmTCP_WATCH1_ADDR_L 0 x32a4
#define mmTCP_WATCH2_ADDR_L 0 x32a7
#define mmTCP_WATCH3_ADDR_L 0 x32aa
#define mmTCP_WATCH0_CNTL 0 x32a2
#define mmTCP_WATCH1_CNTL 0 x32a5
#define mmTCP_WATCH2_CNTL 0 x32a8
#define mmTCP_WATCH3_CNTL 0 x32ab
#define mmTCP_GATCL1_CNTL 0 x32b0
#define mmTCP_ATC_EDC_GATCL1_CNT 0 x32b1
#define mmTCP_GATCL1_DSM_CNTL 0 x32b2
#define mmTCP_DSM_CNTL 0 x32b3
#define mmTCP_CNTL2 0 x32b4
#define mmTD_CGTT_CTRL 0 xf09c
#define mmTA_CGTT_CTRL 0 xf09d
#define mmCGTT_TCP_CLK_CTRL 0 xf09e
#define mmCGTT_TCI_CLK_CTRL 0 xf09f
#define mmTCI_STATUS 0 x2b61
#define mmTCI_CNTL_1 0 x2b62
#define mmTCI_CNTL_2 0 x2b63
#define mmGDS_CONFIG 0 x25c0
#define mmGDS_CNTL_STATUS 0 x25c1
#define mmGDS_ENHANCE2 0 x25c2
#define mmGDS_PROTECTION_FAULT 0 x25c3
#define mmGDS_VM_PROTECTION_FAULT 0 x25c4
#define mmGDS_EDC_CNT 0 x25c5
#define mmGDS_EDC_GRBM_CNT 0 x25c6
#define mmGDS_EDC_OA_DED 0 x25c7
#define mmGDS_DEBUG_CNTL 0 x25c8
#define mmGDS_DEBUG_DATA 0 x25c9
#define mmGDS_DSM_CNTL 0 x25ca
#define mmCGTT_GDS_CLK_CTRL 0 xf0a0
#define mmGDS_RD_ADDR 0 xc400
#define mmGDS_RD_DATA 0 xc401
#define mmGDS_RD_BURST_ADDR 0 xc402
#define mmGDS_RD_BURST_COUNT 0 xc403
#define mmGDS_RD_BURST_DATA 0 xc404
#define mmGDS_WR_ADDR 0 xc405
#define mmGDS_WR_DATA 0 xc406
#define mmGDS_WR_BURST_ADDR 0 xc407
#define mmGDS_WR_BURST_DATA 0 xc408
#define mmGDS_WRITE_COMPLETE 0 xc409
#define mmGDS_ATOM_CNTL 0 xc40a
#define mmGDS_ATOM_COMPLETE 0 xc40b
#define mmGDS_ATOM_BASE 0 xc40c
#define mmGDS_ATOM_SIZE 0 xc40d
#define mmGDS_ATOM_OFFSET0 0 xc40e
#define mmGDS_ATOM_OFFSET1 0 xc40f
#define mmGDS_ATOM_DST 0 xc410
#define mmGDS_ATOM_OP 0 xc411
#define mmGDS_ATOM_SRC0 0 xc412
#define mmGDS_ATOM_SRC0_U 0 xc413
#define mmGDS_ATOM_SRC1 0 xc414
#define mmGDS_ATOM_SRC1_U 0 xc415
#define mmGDS_ATOM_READ0 0 xc416
#define mmGDS_ATOM_READ0_U 0 xc417
#define mmGDS_ATOM_READ1 0 xc418
#define mmGDS_ATOM_READ1_U 0 xc419
#define mmGDS_GWS_RESOURCE_CNTL 0 xc41a
#define mmGDS_GWS_RESOURCE 0 xc41b
#define mmGDS_GWS_RESOURCE_CNT 0 xc41c
#define mmGDS_OA_CNTL 0 xc41d
#define mmGDS_OA_COUNTER 0 xc41e
#define mmGDS_OA_ADDRESS 0 xc41f
#define mmGDS_OA_INCDEC 0 xc420
#define mmGDS_OA_RING_SIZE 0 xc421
#define ixGDS_DEBUG_REG0 0 x0
#define ixGDS_DEBUG_REG1 0 x1
#define ixGDS_DEBUG_REG2 0 x2
#define ixGDS_DEBUG_REG3 0 x3
#define ixGDS_DEBUG_REG4 0 x4
#define ixGDS_DEBUG_REG5 0 x5
#define ixGDS_DEBUG_REG6 0 x6
#define mmGDS_PERFCOUNTER0_SELECT 0 xda80
#define mmGDS_PERFCOUNTER1_SELECT 0 xda81
#define mmGDS_PERFCOUNTER2_SELECT 0 xda82
#define mmGDS_PERFCOUNTER3_SELECT 0 xda83
#define mmGDS_PERFCOUNTER0_LO 0 xd280
#define mmGDS_PERFCOUNTER1_LO 0 xd282
#define mmGDS_PERFCOUNTER2_LO 0 xd284
#define mmGDS_PERFCOUNTER3_LO 0 xd286
#define mmGDS_PERFCOUNTER0_HI 0 xd281
#define mmGDS_PERFCOUNTER1_HI 0 xd283
#define mmGDS_PERFCOUNTER2_HI 0 xd285
#define mmGDS_PERFCOUNTER3_HI 0 xd287
#define mmGDS_PERFCOUNTER0_SELECT1 0 xda84
#define mmGDS_VMID0_BASE 0 x3300
#define mmGDS_VMID1_BASE 0 x3302
#define mmGDS_VMID2_BASE 0 x3304
#define mmGDS_VMID3_BASE 0 x3306
#define mmGDS_VMID4_BASE 0 x3308
#define mmGDS_VMID5_BASE 0 x330a
#define mmGDS_VMID6_BASE 0 x330c
#define mmGDS_VMID7_BASE 0 x330e
#define mmGDS_VMID8_BASE 0 x3310
#define mmGDS_VMID9_BASE 0 x3312
#define mmGDS_VMID10_BASE 0 x3314
#define mmGDS_VMID11_BASE 0 x3316
#define mmGDS_VMID12_BASE 0 x3318
#define mmGDS_VMID13_BASE 0 x331a
#define mmGDS_VMID14_BASE 0 x331c
#define mmGDS_VMID15_BASE 0 x331e
#define mmGDS_VMID0_SIZE 0 x3301
#define mmGDS_VMID1_SIZE 0 x3303
#define mmGDS_VMID2_SIZE 0 x3305
#define mmGDS_VMID3_SIZE 0 x3307
#define mmGDS_VMID4_SIZE 0 x3309
#define mmGDS_VMID5_SIZE 0 x330b
#define mmGDS_VMID6_SIZE 0 x330d
#define mmGDS_VMID7_SIZE 0 x330f
#define mmGDS_VMID8_SIZE 0 x3311
#define mmGDS_VMID9_SIZE 0 x3313
#define mmGDS_VMID10_SIZE 0 x3315
#define mmGDS_VMID11_SIZE 0 x3317
#define mmGDS_VMID12_SIZE 0 x3319
#define mmGDS_VMID13_SIZE 0 x331b
#define mmGDS_VMID14_SIZE 0 x331d
#define mmGDS_VMID15_SIZE 0 x331f
#define mmGDS_GWS_VMID0 0 x3320
#define mmGDS_GWS_VMID1 0 x3321
#define mmGDS_GWS_VMID2 0 x3322
#define mmGDS_GWS_VMID3 0 x3323
#define mmGDS_GWS_VMID4 0 x3324
#define mmGDS_GWS_VMID5 0 x3325
#define mmGDS_GWS_VMID6 0 x3326
#define mmGDS_GWS_VMID7 0 x3327
#define mmGDS_GWS_VMID8 0 x3328
#define mmGDS_GWS_VMID9 0 x3329
#define mmGDS_GWS_VMID10 0 x332a
#define mmGDS_GWS_VMID11 0 x332b
#define mmGDS_GWS_VMID12 0 x332c
#define mmGDS_GWS_VMID13 0 x332d
#define mmGDS_GWS_VMID14 0 x332e
#define mmGDS_GWS_VMID15 0 x332f
#define mmGDS_OA_VMID0 0 x3330
#define mmGDS_OA_VMID1 0 x3331
#define mmGDS_OA_VMID2 0 x3332
#define mmGDS_OA_VMID3 0 x3333
#define mmGDS_OA_VMID4 0 x3334
#define mmGDS_OA_VMID5 0 x3335
#define mmGDS_OA_VMID6 0 x3336
#define mmGDS_OA_VMID7 0 x3337
#define mmGDS_OA_VMID8 0 x3338
#define mmGDS_OA_VMID9 0 x3339
#define mmGDS_OA_VMID10 0 x333a
#define mmGDS_OA_VMID11 0 x333b
#define mmGDS_OA_VMID12 0 x333c
#define mmGDS_OA_VMID13 0 x333d
#define mmGDS_OA_VMID14 0 x333e
#define mmGDS_OA_VMID15 0 x333f
#define mmGDS_GWS_RESET0 0 x3344
#define mmGDS_GWS_RESET1 0 x3345
#define mmGDS_GWS_RESOURCE_RESET 0 x3346
#define mmGDS_COMPUTE_MAX_WAVE_ID 0 x3348
#define mmGDS_OA_RESET_MASK 0 x3349
#define mmGDS_OA_RESET 0 x334a
#define mmGDS_ENHANCE 0 x334b
#define mmGDS_OA_CGPG_RESTORE 0 x334c
#define mmGDS_CS_CTXSW_STATUS 0 x334d
#define mmGDS_CS_CTXSW_CNT0 0 x334e
#define mmGDS_CS_CTXSW_CNT1 0 x334f
#define mmGDS_CS_CTXSW_CNT2 0 x3350
#define mmGDS_CS_CTXSW_CNT3 0 x3351
#define mmGDS_GFX_CTXSW_STATUS 0 x3352
#define mmGDS_VS_CTXSW_CNT0 0 x3353
#define mmGDS_VS_CTXSW_CNT1 0 x3354
#define mmGDS_VS_CTXSW_CNT2 0 x3355
#define mmGDS_VS_CTXSW_CNT3 0 x3356
#define mmGDS_PS0_CTXSW_CNT0 0 x3357
#define mmGDS_PS1_CTXSW_CNT0 0 x335b
#define mmGDS_PS2_CTXSW_CNT0 0 x335f
#define mmGDS_PS3_CTXSW_CNT0 0 x3363
#define mmGDS_PS4_CTXSW_CNT0 0 x3367
#define mmGDS_PS5_CTXSW_CNT0 0 x336b
#define mmGDS_PS6_CTXSW_CNT0 0 x336f
#define mmGDS_PS7_CTXSW_CNT0 0 x3373
#define mmGDS_PS0_CTXSW_CNT1 0 x3358
#define mmGDS_PS1_CTXSW_CNT1 0 x335c
#define mmGDS_PS2_CTXSW_CNT1 0 x3360
#define mmGDS_PS3_CTXSW_CNT1 0 x3364
#define mmGDS_PS4_CTXSW_CNT1 0 x3368
#define mmGDS_PS5_CTXSW_CNT1 0 x336c
#define mmGDS_PS6_CTXSW_CNT1 0 x3370
#define mmGDS_PS7_CTXSW_CNT1 0 x3374
#define mmGDS_PS0_CTXSW_CNT2 0 x3359
#define mmGDS_PS1_CTXSW_CNT2 0 x335d
#define mmGDS_PS2_CTXSW_CNT2 0 x3361
#define mmGDS_PS3_CTXSW_CNT2 0 x3365
#define mmGDS_PS4_CTXSW_CNT2 0 x3369
#define mmGDS_PS5_CTXSW_CNT2 0 x336d
#define mmGDS_PS6_CTXSW_CNT2 0 x3371
#define mmGDS_PS7_CTXSW_CNT2 0 x3375
#define mmGDS_PS0_CTXSW_CNT3 0 x335a
#define mmGDS_PS1_CTXSW_CNT3 0 x335e
#define mmGDS_PS2_CTXSW_CNT3 0 x3362
#define mmGDS_PS3_CTXSW_CNT3 0 x3366
#define mmGDS_PS4_CTXSW_CNT3 0 x336a
#define mmGDS_PS5_CTXSW_CNT3 0 x336e
#define mmGDS_PS6_CTXSW_CNT3 0 x3372
#define mmGDS_PS7_CTXSW_CNT3 0 x3376
#define mmCS_COPY_STATE 0 xa1f3
#define mmGFX_COPY_STATE 0 xa1f4
#define mmVGT_DRAW_INITIATOR 0 xa1fc
#define mmVGT_EVENT_INITIATOR 0 xa2a4
#define mmVGT_EVENT_ADDRESS_REG 0 xa1fe
#define mmVGT_DMA_BASE_HI 0 xa1f9
#define mmVGT_DMA_BASE 0 xa1fa
#define mmVGT_DMA_INDEX_TYPE 0 xa29f
#define mmVGT_DMA_NUM_INSTANCES 0 xa2a2
#define mmIA_ENHANCE 0 xa29c
#define mmVGT_DMA_SIZE 0 xa29d
#define mmVGT_DMA_MAX_SIZE 0 xa29e
#define mmVGT_DMA_PRIMITIVE_TYPE 0 x2271
#define mmVGT_DMA_CONTROL 0 x2272
#define mmVGT_IMMED_DATA 0 xa1fd
#define mmVGT_INDEX_TYPE 0 xc243
#define mmVGT_NUM_INDICES 0 xc24c
#define mmVGT_NUM_INSTANCES 0 xc24d
#define mmVGT_PRIMITIVE_TYPE 0 xc242
#define mmVGT_PRIMITIVEID_EN 0 xa2a1
#define mmVGT_PRIMITIVEID_RESET 0 xa2a3
#define mmVGT_VTX_CNT_EN 0 xa2ae
#define mmVGT_REUSE_OFF 0 xa2ad
#define mmVGT_INSTANCE_STEP_RATE_0 0 xa2a8
#define mmVGT_INSTANCE_STEP_RATE_1 0 xa2a9
#define mmVGT_MAX_VTX_INDX 0 xa100
#define mmVGT_MIN_VTX_INDX 0 xa101
#define mmVGT_INDX_OFFSET 0 xa102
#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0 xa316
#define mmVGT_OUT_DEALLOC_CNTL 0 xa317
#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0 xa103
#define mmVGT_MULTI_PRIM_IB_RESET_EN 0 xa2a5
#define mmVGT_ENHANCE 0 xa294
#define mmVGT_OUTPUT_PATH_CNTL 0 xa284
#define mmVGT_HOS_CNTL 0 xa285
#define mmVGT_HOS_MAX_TESS_LEVEL 0 xa286
#define mmVGT_HOS_MIN_TESS_LEVEL 0 xa287
#define mmVGT_HOS_REUSE_DEPTH 0 xa288
#define mmVGT_GROUP_PRIM_TYPE 0 xa289
#define mmVGT_GROUP_FIRST_DECR 0 xa28a
#define mmVGT_GROUP_DECR 0 xa28b
#define mmVGT_GROUP_VECT_0_CNTL 0 xa28c
#define mmVGT_GROUP_VECT_1_CNTL 0 xa28d
#define mmVGT_GROUP_VECT_0_FMT_CNTL 0 xa28e
#define mmVGT_GROUP_VECT_1_FMT_CNTL 0 xa28f
#define mmVGT_VTX_VECT_EJECT_REG 0 x222c
#define mmVGT_DMA_DATA_FIFO_DEPTH 0 x222d
#define mmVGT_DMA_REQ_FIFO_DEPTH 0 x222e
#define mmVGT_DRAW_INIT_FIFO_DEPTH 0 x222f
#define mmVGT_LAST_COPY_STATE 0 x2230
#define mmCC_GC_SHADER_ARRAY_CONFIG 0 x226f
#define mmGC_USER_SHADER_ARRAY_CONFIG 0 x2270
#define mmVGT_GS_MODE 0 xa290
#define mmVGT_GS_ONCHIP_CNTL 0 xa291
#define mmVGT_GS_OUT_PRIM_TYPE 0 xa29b
#define mmVGT_CACHE_INVALIDATION 0 x2231
#define mmVGT_RESET_DEBUG 0 x2232
#define mmVGT_STRMOUT_DELAY 0 x2233
#define mmVGT_FIFO_DEPTHS 0 x2234
#define mmVGT_GS_PER_ES 0 xa295
#define mmVGT_ES_PER_GS 0 xa296
#define mmVGT_GS_PER_VS 0 xa297
#define mmVGT_GS_VERTEX_REUSE 0 x2235
#define mmVGT_MC_LAT_CNTL 0 x2236
#define mmIA_CNTL_STATUS 0 x2237
#define mmVGT_STRMOUT_CONFIG 0 xa2e5
#define mmVGT_STRMOUT_BUFFER_SIZE_0 0 xa2b4
#define mmVGT_STRMOUT_BUFFER_SIZE_1 0 xa2b8
#define mmVGT_STRMOUT_BUFFER_SIZE_2 0 xa2bc
#define mmVGT_STRMOUT_BUFFER_SIZE_3 0 xa2c0
#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0 xa2b7
#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0 xa2bb
#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0 xa2bf
#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0 xa2c3
#define mmVGT_STRMOUT_VTX_STRIDE_0 0 xa2b5
#define mmVGT_STRMOUT_VTX_STRIDE_1 0 xa2b9
#define mmVGT_STRMOUT_VTX_STRIDE_2 0 xa2bd
#define mmVGT_STRMOUT_VTX_STRIDE_3 0 xa2c1
#define mmVGT_STRMOUT_BUFFER_CONFIG 0 xa2e6
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0 xc244
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0 xc245
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0 xc246
#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0 xc247
#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0 xa2ca
#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0 xa2cb
#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0 xa2cc
#define mmVGT_GS_MAX_VERT_OUT 0 xa2ce
#define mmVGT_SHADER_STAGES_EN 0 xa2d5
#define mmVGT_DISPATCH_DRAW_INDEX 0 xa2dd
#define mmVGT_LS_HS_CONFIG 0 xa2d6
#define mmVGT_DMA_LS_HS_CONFIG 0 x2273
#define mmVGT_TF_PARAM 0 xa2db
#define mmVGT_TESS_DISTRIBUTION 0 xa2d4
#define mmVGT_TF_RING_SIZE 0 xc24e
#define mmVGT_SYS_CONFIG 0 x2263
#define mmVGT_HS_OFFCHIP_PARAM 0 xc24f
#define mmVGT_TF_MEMORY_BASE 0 xc250
#define mmVGT_GS_INSTANCE_CNT 0 xa2e4
#define mmIA_MULTI_VGT_PARAM 0 xa2aa
#define mmVGT_VS_MAX_WAVE_ID 0 x2268
#define mmVGT_ESGS_RING_SIZE 0 xc240
#define mmVGT_GSVS_RING_SIZE 0 xc241
#define mmVGT_GSVS_RING_OFFSET_1 0 xa298
#define mmVGT_GSVS_RING_OFFSET_2 0 xa299
#define mmVGT_GSVS_RING_OFFSET_3 0 xa29a
#define mmVGT_ESGS_RING_ITEMSIZE 0 xa2ab
#define mmVGT_GSVS_RING_ITEMSIZE 0 xa2ac
#define mmVGT_GS_VERT_ITEMSIZE 0 xa2d7
#define mmVGT_GS_VERT_ITEMSIZE_1 0 xa2d8
#define mmVGT_GS_VERT_ITEMSIZE_2 0 xa2d9
#define mmVGT_GS_VERT_ITEMSIZE_3 0 xa2da
#define mmWD_CNTL_STATUS 0 x223f
#define mmWD_ENHANCE 0 xa2a0
#define mmGFX_PIPE_CONTROL 0 x226d
#define mmCGTT_VGT_CLK_CTRL 0 xf084
#define mmCGTT_IA_CLK_CTRL 0 xf085
#define mmCGTT_WD_CLK_CTRL 0 xf086
#define mmVGT_DEBUG_CNTL 0 x2238
#define mmVGT_DEBUG_DATA 0 x2239
#define mmIA_DEBUG_CNTL 0 x223a
#define mmIA_DEBUG_DATA 0 x223b
#define mmVGT_CNTL_STATUS 0 x223c
#define mmWD_DEBUG_CNTL 0 x223d
#define mmWD_DEBUG_DATA 0 x223e
#define mmWD_QOS 0 x2242
#define mmCC_GC_PRIM_CONFIG 0 x2240
#define mmGC_USER_PRIM_CONFIG 0 x2241
#define ixWD_DEBUG_REG0 0 x0
#define ixWD_DEBUG_REG1 0 x1
#define ixWD_DEBUG_REG2 0 x2
#define ixWD_DEBUG_REG3 0 x3
#define ixWD_DEBUG_REG4 0 x4
#define ixWD_DEBUG_REG5 0 x5
#define ixWD_DEBUG_REG6 0 x6
#define ixWD_DEBUG_REG7 0 x7
#define ixWD_DEBUG_REG8 0 x8
#define ixWD_DEBUG_REG9 0 x9
#define ixWD_DEBUG_REG10 0 xa
#define ixIA_DEBUG_REG0 0 x0
#define ixIA_DEBUG_REG1 0 x1
#define ixIA_DEBUG_REG2 0 x2
#define ixIA_DEBUG_REG3 0 x3
#define ixIA_DEBUG_REG4 0 x4
#define ixIA_DEBUG_REG5 0 x5
#define ixIA_DEBUG_REG6 0 x6
#define ixIA_DEBUG_REG7 0 x7
#define ixIA_DEBUG_REG8 0 x8
#define ixIA_DEBUG_REG9 0 x9
#define ixVGT_DEBUG_REG0 0 x0
#define ixVGT_DEBUG_REG1 0 x1
#define ixVGT_DEBUG_REG2 0 x1e
#define ixVGT_DEBUG_REG3 0 x1f
#define ixVGT_DEBUG_REG4 0 x20
#define ixVGT_DEBUG_REG5 0 x21
#define ixVGT_DEBUG_REG6 0 x22
#define ixVGT_DEBUG_REG7 0 x23
#define ixVGT_DEBUG_REG8 0 x8
#define ixVGT_DEBUG_REG9 0 x9
#define ixVGT_DEBUG_REG10 0 xa
#define ixVGT_DEBUG_REG11 0 xb
#define ixVGT_DEBUG_REG12 0 xc
#define ixVGT_DEBUG_REG13 0 xd
#define ixVGT_DEBUG_REG14 0 xe
#define ixVGT_DEBUG_REG15 0 xf
#define ixVGT_DEBUG_REG16 0 x10
#define ixVGT_DEBUG_REG17 0 x11
#define ixVGT_DEBUG_REG18 0 x7
#define ixVGT_DEBUG_REG19 0 x13
#define ixVGT_DEBUG_REG20 0 x14
#define ixVGT_DEBUG_REG21 0 x15
#define ixVGT_DEBUG_REG22 0 x16
#define ixVGT_DEBUG_REG23 0 x17
#define ixVGT_DEBUG_REG24 0 x18
#define ixVGT_DEBUG_REG25 0 x19
#define ixVGT_DEBUG_REG26 0 x24
#define ixVGT_DEBUG_REG27 0 x1b
#define ixVGT_DEBUG_REG28 0 x1c
#define ixVGT_DEBUG_REG29 0 x1d
#define ixVGT_DEBUG_REG31 0 x26
#define ixVGT_DEBUG_REG32 0 x27
#define ixVGT_DEBUG_REG33 0 x28
#define ixVGT_DEBUG_REG34 0 x29
#define ixVGT_DEBUG_REG36 0 x2b
#define mmVGT_PERFCOUNTER_SEID_MASK 0 xd894
#define mmVGT_PERFCOUNTER0_SELECT 0 xd88c
#define mmVGT_PERFCOUNTER1_SELECT 0 xd88d
#define mmVGT_PERFCOUNTER2_SELECT 0 xd88e
#define mmVGT_PERFCOUNTER3_SELECT 0 xd88f
#define mmVGT_PERFCOUNTER0_SELECT1 0 xd890
#define mmVGT_PERFCOUNTER1_SELECT1 0 xd891
#define mmVGT_PERFCOUNTER0_LO 0 xd090
#define mmVGT_PERFCOUNTER1_LO 0 xd092
#define mmVGT_PERFCOUNTER2_LO 0 xd094
#define mmVGT_PERFCOUNTER3_LO 0 xd096
#define mmVGT_PERFCOUNTER0_HI 0 xd091
#define mmVGT_PERFCOUNTER1_HI 0 xd093
#define mmVGT_PERFCOUNTER2_HI 0 xd095
#define mmVGT_PERFCOUNTER3_HI 0 xd097
#define mmIA_PERFCOUNTER0_SELECT 0 xd884
#define mmIA_PERFCOUNTER1_SELECT 0 xd885
#define mmIA_PERFCOUNTER2_SELECT 0 xd886
#define mmIA_PERFCOUNTER3_SELECT 0 xd887
#define mmIA_PERFCOUNTER0_SELECT1 0 xd888
#define mmIA_PERFCOUNTER0_LO 0 xd088
#define mmIA_PERFCOUNTER1_LO 0 xd08a
#define mmIA_PERFCOUNTER2_LO 0 xd08c
#define mmIA_PERFCOUNTER3_LO 0 xd08e
#define mmIA_PERFCOUNTER0_HI 0 xd089
#define mmIA_PERFCOUNTER1_HI 0 xd08b
#define mmIA_PERFCOUNTER2_HI 0 xd08d
#define mmIA_PERFCOUNTER3_HI 0 xd08f
#define mmWD_PERFCOUNTER0_SELECT 0 xd880
#define mmWD_PERFCOUNTER1_SELECT 0 xd881
#define mmWD_PERFCOUNTER2_SELECT 0 xd882
#define mmWD_PERFCOUNTER3_SELECT 0 xd883
#define mmWD_PERFCOUNTER0_LO 0 xd080
#define mmWD_PERFCOUNTER1_LO 0 xd082
#define mmWD_PERFCOUNTER2_LO 0 xd084
#define mmWD_PERFCOUNTER3_LO 0 xd086
#define mmWD_PERFCOUNTER0_HI 0 xd081
#define mmWD_PERFCOUNTER1_HI 0 xd083
#define mmWD_PERFCOUNTER2_HI 0 xd085
#define mmWD_PERFCOUNTER3_HI 0 xd087
#define mmDIDT_IND_INDEX 0 x3280
#define mmDIDT_IND_DATA 0 x3281
#define ixDIDT_SQ_CTRL0 0 x0
#define ixDIDT_SQ_CTRL1 0 x1
#define ixDIDT_SQ_CTRL2 0 x2
#define ixDIDT_SQ_CTRL_OCP 0 x3
#define ixDIDT_SQ_WEIGHT0_3 0 x10
#define ixDIDT_SQ_WEIGHT4_7 0 x11
#define ixDIDT_SQ_WEIGHT8_11 0 x12
#define ixDIDT_DB_CTRL0 0 x20
#define ixDIDT_DB_CTRL1 0 x21
#define ixDIDT_DB_CTRL2 0 x22
#define ixDIDT_DB_CTRL_OCP 0 x23
#define ixDIDT_DB_WEIGHT0_3 0 x30
#define ixDIDT_DB_WEIGHT4_7 0 x31
#define ixDIDT_DB_WEIGHT8_11 0 x32
#define ixDIDT_TD_CTRL0 0 x40
#define ixDIDT_TD_CTRL1 0 x41
#define ixDIDT_TD_CTRL2 0 x42
#define ixDIDT_TD_CTRL_OCP 0 x43
#define ixDIDT_TD_WEIGHT0_3 0 x50
#define ixDIDT_TD_WEIGHT4_7 0 x51
#define ixDIDT_TD_WEIGHT8_11 0 x52
#define ixDIDT_TCP_CTRL0 0 x60
#define ixDIDT_TCP_CTRL1 0 x61
#define ixDIDT_TCP_CTRL2 0 x62
#define ixDIDT_TCP_CTRL_OCP 0 x63
#define ixDIDT_TCP_WEIGHT0_3 0 x70
#define ixDIDT_TCP_WEIGHT4_7 0 x71
#define ixDIDT_TCP_WEIGHT8_11 0 x72
#define ixDIDT_DBR_CTRL0 0 x80
#define ixDIDT_DBR_CTRL1 0 x81
#define ixDIDT_DBR_CTRL2 0 x82
#define ixDIDT_DBR_CTRL_OCP 0 x83
#define ixDIDT_DBR_WEIGHT0_3 0 x90
#define ixDIDT_DBR_WEIGHT4_7 0 x91
#define ixDIDT_DBR_WEIGHT8_11 0 x92
#endif /* GFX_8_1_D_H */
Messung V0.5 in Prozent C=99 H=98 G=98
¤ Dauer der Verarbeitung: 0.157 Sekunden
(vorverarbeitet am 2026-06-06)
¤
*© Formatika GbR, Deutschland