/* * Copyright 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * #ifndef _gc_9_4_2_OFFSET_HEADER#define _gc_9_4_2_OFFSET_HEADER// addressBlock: didtind // base address: 0x0 #define ixDIDT_SQ_CTRL0 0 x0000#define ixDIDT_SQ_CTRL2 0 x0002#define ixDIDT_SQ_STALL_CTRL 0 x0004#define ixDIDT_SQ_TUNING_CTRL 0 x0005#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 0 x0006#define ixDIDT_SQ_CTRL3 0 x0007#define ixDIDT_SQ_STALL_PATTERN_1_2 0 x0008#define ixDIDT_SQ_STALL_PATTERN_3_4 0 x0009#define ixDIDT_SQ_STALL_PATTERN_5_6 0 x000a#define ixDIDT_SQ_STALL_PATTERN_7 0 x000b#define ixDIDT_SQ_MPD_SCALE_FACTOR 0 x000c#define ixDIDT_SQ_THROTTLE_CNTL0 0 x000d#define ixDIDT_SQ_THROTTLE_CNTL1 0 x000e#define ixDIDT_SQ_THROTTLE_CNTL_STATUS 0 x000f#define ixDIDT_SQ_WEIGHT0_3 0 x0010#define ixDIDT_SQ_WEIGHT4_7 0 x0011#define ixDIDT_SQ_WEIGHT8_11 0 x0012#define ixDIDT_SQ_EDC_CTRL 0 x0013#define ixDIDT_SQ_THROTTLE_CTRL 0 x0014#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0 x0015#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0 x0016#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0 x0017#define ixDIDT_SQ_EDC_STALL_PATTERN_7 0 x0018#define ixDIDT_SQ_EDC_STATUS 0 x0019#define ixDIDT_SQ_EDC_STALL_DELAY_1 0 x001a#define ixDIDT_SQ_EDC_STALL_DELAY_2 0 x001b#define ixDIDT_SQ_EDC_STALL_DELAY_3 0 x001c#define ixDIDT_SQ_EDC_STALL_DELAY_4 0 x001d#define ixDIDT_SQ_EDC_OVERFLOW 0 x001e#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA 0 x001f#define ixDIDT_DB_CTRL0 0 x0020#define ixDIDT_DB_CTRL2 0 x0022#define ixDIDT_DB_STALL_CTRL 0 x0024#define ixDIDT_DB_TUNING_CTRL 0 x0025#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL 0 x0026#define ixDIDT_DB_CTRL3 0 x0027#define ixDIDT_DB_STALL_PATTERN_1_2 0 x0028#define ixDIDT_DB_STALL_PATTERN_3_4 0 x0029#define ixDIDT_DB_STALL_PATTERN_5_6 0 x002a#define ixDIDT_DB_STALL_PATTERN_7 0 x002b#define ixDIDT_DB_MPD_SCALE_FACTOR 0 x002c#define ixDIDT_DB_THROTTLE_CNTL0 0 x002d#define ixDIDT_DB_THROTTLE_CNTL1 0 x002e#define ixDIDT_DB_THROTTLE_CNTL_STATUS 0 x002f#define ixDIDT_DB_WEIGHT0_3 0 x0030#define ixDIDT_DB_WEIGHT4_7 0 x0031#define ixDIDT_DB_WEIGHT8_11 0 x0032#define ixDIDT_DB_EDC_CTRL 0 x0033#define ixDIDT_DB_THROTTLE_CTRL 0 x0034#define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0 x0035#define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0 x0036#define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0 x0037#define ixDIDT_DB_EDC_STALL_PATTERN_7 0 x0038#define ixDIDT_DB_EDC_STATUS 0 x0039#define ixDIDT_DB_EDC_STALL_DELAY_1 0 x003a#define ixDIDT_DB_EDC_OVERFLOW 0 x003e#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA 0 x003f#define ixDIDT_TD_CTRL0 0 x0040#define ixDIDT_TD_CTRL2 0 x0042#define ixDIDT_TD_STALL_CTRL 0 x0044#define ixDIDT_TD_TUNING_CTRL 0 x0045#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL 0 x0046#define ixDIDT_TD_CTRL3 0 x0047#define ixDIDT_TD_STALL_PATTERN_1_2 0 x0048#define ixDIDT_TD_STALL_PATTERN_3_4 0 x0049#define ixDIDT_TD_STALL_PATTERN_5_6 0 x004a#define ixDIDT_TD_STALL_PATTERN_7 0 x004b#define ixDIDT_TD_MPD_SCALE_FACTOR 0 x004c#define ixDIDT_TD_THROTTLE_CNTL0 0 x004d#define ixDIDT_TD_THROTTLE_CNTL1 0 x004e#define ixDIDT_TD_THROTTLE_CNTL_STATUS 0 x004f#define ixDIDT_TD_WEIGHT0_3 0 x0050#define ixDIDT_TD_WEIGHT4_7 0 x0051#define ixDIDT_TD_WEIGHT8_11 0 x0052#define ixDIDT_TD_EDC_CTRL 0 x0053#define ixDIDT_TD_THROTTLE_CTRL 0 x0054#define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0 x0055#define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0 x0056#define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0 x0057#define ixDIDT_TD_EDC_STALL_PATTERN_7 0 x0058#define ixDIDT_TD_EDC_STATUS 0 x0059#define ixDIDT_TD_EDC_STALL_DELAY_1 0 x005a#define ixDIDT_TD_EDC_STALL_DELAY_2 0 x005b#define ixDIDT_TD_EDC_STALL_DELAY_3 0 x005c#define ixDIDT_TD_EDC_STALL_DELAY_4 0 x005d#define ixDIDT_TD_EDC_OVERFLOW 0 x005e#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA 0 x005f#define ixDIDT_TCP_CTRL0 0 x0060#define ixDIDT_TCP_CTRL2 0 x0062#define ixDIDT_TCP_STALL_CTRL 0 x0064#define ixDIDT_TCP_TUNING_CTRL 0 x0065#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL 0 x0066#define ixDIDT_TCP_CTRL3 0 x0067#define ixDIDT_TCP_STALL_PATTERN_1_2 0 x0068#define ixDIDT_TCP_STALL_PATTERN_3_4 0 x0069#define ixDIDT_TCP_STALL_PATTERN_5_6 0 x006a#define ixDIDT_TCP_STALL_PATTERN_7 0 x006b#define ixDIDT_TCP_MPD_SCALE_FACTOR 0 x006c#define ixDIDT_TCP_THROTTLE_CNTL0 0 x006d#define ixDIDT_TCP_THROTTLE_CNTL1 0 x006e#define ixDIDT_TCP_THROTTLE_CNTL_STATUS 0 x006f#define ixDIDT_TCP_WEIGHT0_3 0 x0070#define ixDIDT_TCP_WEIGHT4_7 0 x0071#define ixDIDT_TCP_WEIGHT8_11 0 x0072#define ixDIDT_TCP_EDC_CTRL 0 x0073#define ixDIDT_TCP_THROTTLE_CTRL 0 x0074#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0 x0075#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0 x0076#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0 x0077#define ixDIDT_TCP_EDC_STALL_PATTERN_7 0 x0078#define ixDIDT_TCP_EDC_STATUS 0 x0079#define ixDIDT_TCP_EDC_STALL_DELAY_1 0 x007a#define ixDIDT_TCP_EDC_STALL_DELAY_2 0 x007b#define ixDIDT_TCP_EDC_STALL_DELAY_3 0 x007c#define ixDIDT_TCP_EDC_STALL_DELAY_4 0 x007d#define ixDIDT_TCP_EDC_OVERFLOW 0 x007e#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA 0 x007f#define ixDIDT_SQ_STALL_EVENT_COUNTER 0 x00a0#define ixDIDT_DB_STALL_EVENT_COUNTER 0 x00a1#define ixDIDT_TD_STALL_EVENT_COUNTER 0 x00a2#define ixDIDT_TCP_STALL_EVENT_COUNTER 0 x00a3#define ixDIDT_DBR_STALL_EVENT_COUNTER 0 x00a4#define ixDIDT_SQ_EDC_PCC_PERF_COUNTER 0 x00a5#define ixDIDT_TD_EDC_PCC_PERF_COUNTER 0 x00a6#define ixDIDT_TCP_EDC_PCC_PERF_COUNTER 0 x00a7#define ixDIDT_DB_EDC_PCC_PERF_COUNTER 0 x00a8#define ixDIDT_DBR_EDC_PCC_PERF_COUNTER 0 x00a9#define ixDIDT_SQ_CTRL1 0 x00b0#define ixDIDT_SQ_EDC_THRESHOLD 0 x00b1#define ixDIDT_DB_CTRL1 0 x00b2#define ixDIDT_DB_EDC_THRESHOLD 0 x00b3#define ixDIDT_TD_CTRL1 0 x00b4#define ixDIDT_TD_EDC_THRESHOLD 0 x00b5#define ixDIDT_TCP_CTRL1 0 x00b6#define ixDIDT_TCP_EDC_THRESHOLD 0 x00b7// addressBlock: gc_cpdec // base address: 0x8200 #define regCP_CPC_STATUS 0 x0084#define regCP_CPC_STATUS_BASE_IDX 0 #define regCP_CPC_BUSY_STAT 0 x0085#define regCP_CPC_BUSY_STAT_BASE_IDX 0 #define regCP_CPC_STALLED_STAT1 0 x0086#define regCP_CPC_STALLED_STAT1_BASE_IDX 0 #define regCP_CPF_STATUS 0 x0087#define regCP_CPF_STATUS_BASE_IDX 0 #define regCP_CPF_BUSY_STAT 0 x0088#define regCP_CPF_BUSY_STAT_BASE_IDX 0 #define regCP_CPF_STALLED_STAT1 0 x0089#define regCP_CPF_STALLED_STAT1_BASE_IDX 0 #define regCP_CPC_GRBM_FREE_COUNT 0 x008b#define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 #define regCP_CPC_PRIV_VIOLATION_ADDR 0 x008c#define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX 0 #define regCP_MEC_CNTL 0 x008d#define regCP_MEC_CNTL_BASE_IDX 0 #define regCP_MEC_ME1_HEADER_DUMP 0 x008e#define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 #define regCP_MEC_ME2_HEADER_DUMP 0 x008f#define regCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0 #define regCP_CPC_SCRATCH_INDEX 0 x0090#define regCP_CPC_SCRATCH_INDEX_BASE_IDX 0 #define regCP_CPC_SCRATCH_DATA 0 x0091#define regCP_CPC_SCRATCH_DATA_BASE_IDX 0 #define regCP_CPF_GRBM_FREE_COUNT 0 x0092#define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 #define regCP_CPC_HALT_HYST_COUNT 0 x00a7#define regCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 #define regCP_CE_COMPARE_COUNT 0 x00c0#define regCP_CE_COMPARE_COUNT_BASE_IDX 0 #define regCP_CE_DE_COUNT 0 x00c1#define regCP_CE_DE_COUNT_BASE_IDX 0 #define regCP_DE_CE_COUNT 0 x00c2#define regCP_DE_CE_COUNT_BASE_IDX 0 #define regCP_DE_LAST_INVAL_COUNT 0 x00c3#define regCP_DE_LAST_INVAL_COUNT_BASE_IDX 0 #define regCP_DE_DE_COUNT 0 x00c4#define regCP_DE_DE_COUNT_BASE_IDX 0 #define regCP_STALLED_STAT3 0 x019c#define regCP_STALLED_STAT3_BASE_IDX 0 #define regCP_STALLED_STAT1 0 x019d#define regCP_STALLED_STAT1_BASE_IDX 0 #define regCP_STALLED_STAT2 0 x019e#define regCP_STALLED_STAT2_BASE_IDX 0 #define regCP_BUSY_STAT 0 x019f#define regCP_BUSY_STAT_BASE_IDX 0 #define regCP_STAT 0 x01a0#define regCP_STAT_BASE_IDX 0 #define regCP_ME_HEADER_DUMP 0 x01a1#define regCP_ME_HEADER_DUMP_BASE_IDX 0 #define regCP_PFP_HEADER_DUMP 0 x01a2#define regCP_PFP_HEADER_DUMP_BASE_IDX 0 #define regCP_GRBM_FREE_COUNT 0 x01a3#define regCP_GRBM_FREE_COUNT_BASE_IDX 0 #define regCP_CE_HEADER_DUMP 0 x01a4#define regCP_CE_HEADER_DUMP_BASE_IDX 0 #define regCP_PFP_INSTR_PNTR 0 x01a5#define regCP_PFP_INSTR_PNTR_BASE_IDX 0 #define regCP_ME_INSTR_PNTR 0 x01a6#define regCP_ME_INSTR_PNTR_BASE_IDX 0 #define regCP_CE_INSTR_PNTR 0 x01a7#define regCP_CE_INSTR_PNTR_BASE_IDX 0 #define regCP_MEC1_INSTR_PNTR 0 x01a8#define regCP_MEC1_INSTR_PNTR_BASE_IDX 0 #define regCP_MEC2_INSTR_PNTR 0 x01a9#define regCP_MEC2_INSTR_PNTR_BASE_IDX 0 #define regCP_CSF_STAT 0 x01b4#define regCP_CSF_STAT_BASE_IDX 0 #define regCP_ME_CNTL 0 x01b6#define regCP_ME_CNTL_BASE_IDX 0 #define regCP_CNTX_STAT 0 x01b8#define regCP_CNTX_STAT_BASE_IDX 0 #define regCP_ME_PREEMPTION 0 x01b9#define regCP_ME_PREEMPTION_BASE_IDX 0 #define regCP_ROQ_THRESHOLDS 0 x01bc#define regCP_ROQ_THRESHOLDS_BASE_IDX 0 #define regCP_MEQ_STQ_THRESHOLD 0 x01bd#define regCP_MEQ_STQ_THRESHOLD_BASE_IDX 0 #define regCP_RB2_RPTR 0 x01be#define regCP_RB2_RPTR_BASE_IDX 0 #define regCP_RB1_RPTR 0 x01bf#define regCP_RB1_RPTR_BASE_IDX 0 #define regCP_RB0_RPTR 0 x01c0#define regCP_RB0_RPTR_BASE_IDX 0 #define regCP_RB_RPTR 0 x01c0#define regCP_RB_RPTR_BASE_IDX 0 #define regCP_RB_WPTR_DELAY 0 x01c1#define regCP_RB_WPTR_DELAY_BASE_IDX 0 #define regCP_RB_WPTR_POLL_CNTL 0 x01c2#define regCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 #define regCP_ROQ1_THRESHOLDS 0 x01d5#define regCP_ROQ1_THRESHOLDS_BASE_IDX 0 #define regCP_ROQ2_THRESHOLDS 0 x01d6#define regCP_ROQ2_THRESHOLDS_BASE_IDX 0 #define regCP_STQ_THRESHOLDS 0 x01d7#define regCP_STQ_THRESHOLDS_BASE_IDX 0 #define regCP_QUEUE_THRESHOLDS 0 x01d8#define regCP_QUEUE_THRESHOLDS_BASE_IDX 0 #define regCP_MEQ_THRESHOLDS 0 x01d9#define regCP_MEQ_THRESHOLDS_BASE_IDX 0 #define regCP_ROQ_AVAIL 0 x01da#define regCP_ROQ_AVAIL_BASE_IDX 0 #define regCP_STQ_AVAIL 0 x01db#define regCP_STQ_AVAIL_BASE_IDX 0 #define regCP_ROQ2_AVAIL 0 x01dc#define regCP_ROQ2_AVAIL_BASE_IDX 0 #define regCP_MEQ_AVAIL 0 x01dd#define regCP_MEQ_AVAIL_BASE_IDX 0 #define regCP_CMD_INDEX 0 x01de#define regCP_CMD_INDEX_BASE_IDX 0 #define regCP_CMD_DATA 0 x01df#define regCP_CMD_DATA_BASE_IDX 0 #define regCP_ROQ_RB_STAT 0 x01e0#define regCP_ROQ_RB_STAT_BASE_IDX 0 #define regCP_ROQ_IB1_STAT 0 x01e1#define regCP_ROQ_IB1_STAT_BASE_IDX 0 #define regCP_ROQ_IB2_STAT 0 x01e2#define regCP_ROQ_IB2_STAT_BASE_IDX 0 #define regCP_STQ_STAT 0 x01e3#define regCP_STQ_STAT_BASE_IDX 0 #define regCP_STQ_WR_STAT 0 x01e4#define regCP_STQ_WR_STAT_BASE_IDX 0 #define regCP_MEQ_STAT 0 x01e5#define regCP_MEQ_STAT_BASE_IDX 0 #define regCP_CEQ1_AVAIL 0 x01e6#define regCP_CEQ1_AVAIL_BASE_IDX 0 #define regCP_CEQ2_AVAIL 0 x01e7#define regCP_CEQ2_AVAIL_BASE_IDX 0 #define regCP_CE_ROQ_RB_STAT 0 x01e8#define regCP_CE_ROQ_RB_STAT_BASE_IDX 0 #define regCP_CE_ROQ_IB1_STAT 0 x01e9#define regCP_CE_ROQ_IB1_STAT_BASE_IDX 0 #define regCP_CE_ROQ_IB2_STAT 0 x01ea#define regCP_CE_ROQ_IB2_STAT_BASE_IDX 0 #define regCP_PRIV_VIOLATION_ADDR 0 x01fa#define regCP_PRIV_VIOLATION_ADDR_BASE_IDX 0 // addressBlock: gc_cppdec // base address: 0xc080 #define regCP_EOPQ_WAIT_TIME 0 x1035#define regCP_EOPQ_WAIT_TIME_BASE_IDX 0 #define regCP_CPC_MGCG_SYNC_CNTL 0 x1036#define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 #define regCPC_INT_INFO 0 x1037#define regCPC_INT_INFO_BASE_IDX 0 #define regCP_VIRT_STATUS 0 x1038#define regCP_VIRT_STATUS_BASE_IDX 0 #define regCPC_INT_ADDR 0 x1039#define regCPC_INT_ADDR_BASE_IDX 0 #define regCPC_INT_PASID 0 x103a#define regCPC_INT_PASID_BASE_IDX 0 #define regCP_GFX_ERROR 0 x103b#define regCP_GFX_ERROR_BASE_IDX 0 #define regCPG_UTCL1_CNTL 0 x103c#define regCPG_UTCL1_CNTL_BASE_IDX 0 #define regCPC_UTCL1_CNTL 0 x103d#define regCPC_UTCL1_CNTL_BASE_IDX 0 #define regCPF_UTCL1_CNTL 0 x103e#define regCPF_UTCL1_CNTL_BASE_IDX 0 #define regCP_AQL_SMM_STATUS 0 x103f#define regCP_AQL_SMM_STATUS_BASE_IDX 0 #define regCP_RB0_BASE 0 x1040#define regCP_RB0_BASE_BASE_IDX 0 #define regCP_RB_BASE 0 x1040#define regCP_RB_BASE_BASE_IDX 0 #define regCP_RB0_CNTL 0 x1041#define regCP_RB0_CNTL_BASE_IDX 0 #define regCP_RB_CNTL 0 x1041#define regCP_RB_CNTL_BASE_IDX 0 #define regCP_RB_RPTR_WR 0 x1042#define regCP_RB_RPTR_WR_BASE_IDX 0 #define regCP_RB0_RPTR_ADDR 0 x1043#define regCP_RB0_RPTR_ADDR_BASE_IDX 0 #define regCP_RB_RPTR_ADDR 0 x1043#define regCP_RB_RPTR_ADDR_BASE_IDX 0 #define regCP_RB0_RPTR_ADDR_HI 0 x1044#define regCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 #define regCP_RB_RPTR_ADDR_HI 0 x1044#define regCP_RB_RPTR_ADDR_HI_BASE_IDX 0 #define regCP_RB0_BUFSZ_MASK 0 x1045#define regCP_RB0_BUFSZ_MASK_BASE_IDX 0 #define regCP_RB_BUFSZ_MASK 0 x1045#define regCP_RB_BUFSZ_MASK_BASE_IDX 0 #define regCP_RB_WPTR_POLL_ADDR_LO 0 x1046#define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 #define regCP_RB_WPTR_POLL_ADDR_HI 0 x1047#define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 #define regCP_INT_CNTL 0 x1049#define regCP_INT_CNTL_BASE_IDX 0 #define regCP_INT_STATUS 0 x104a#define regCP_INT_STATUS_BASE_IDX 0 #define regCP_DEVICE_ID 0 x104b#define regCP_DEVICE_ID_BASE_IDX 0 #define regCP_ME0_PIPE_PRIORITY_CNTS 0 x104c#define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 #define regCP_RING_PRIORITY_CNTS 0 x104c#define regCP_RING_PRIORITY_CNTS_BASE_IDX 0 #define regCP_ME0_PIPE0_PRIORITY 0 x104d#define regCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 #define regCP_RING0_PRIORITY 0 x104d#define regCP_RING0_PRIORITY_BASE_IDX 0 #define regCP_ME0_PIPE1_PRIORITY 0 x104e#define regCP_ME0_PIPE1_PRIORITY_BASE_IDX 0 #define regCP_RING1_PRIORITY 0 x104e#define regCP_RING1_PRIORITY_BASE_IDX 0 #define regCP_ME0_PIPE2_PRIORITY 0 x104f#define regCP_ME0_PIPE2_PRIORITY_BASE_IDX 0 #define regCP_RING2_PRIORITY 0 x104f#define regCP_RING2_PRIORITY_BASE_IDX 0 #define regCP_FATAL_ERROR 0 x1050#define regCP_FATAL_ERROR_BASE_IDX 0 #define regCP_RB_VMID 0 x1051#define regCP_RB_VMID_BASE_IDX 0 #define regCP_ME0_PIPE0_VMID 0 x1052#define regCP_ME0_PIPE0_VMID_BASE_IDX 0 #define regCP_ME0_PIPE1_VMID 0 x1053#define regCP_ME0_PIPE1_VMID_BASE_IDX 0 #define regCP_RB0_WPTR 0 x1054#define regCP_RB0_WPTR_BASE_IDX 0 #define regCP_RB_WPTR 0 x1054#define regCP_RB_WPTR_BASE_IDX 0 #define regCP_RB0_WPTR_HI 0 x1055#define regCP_RB0_WPTR_HI_BASE_IDX 0 #define regCP_RB_WPTR_HI 0 x1055#define regCP_RB_WPTR_HI_BASE_IDX 0 #define regCP_RB1_WPTR 0 x1056#define regCP_RB1_WPTR_BASE_IDX 0 #define regCP_RB1_WPTR_HI 0 x1057#define regCP_RB1_WPTR_HI_BASE_IDX 0 #define regCP_RB2_WPTR 0 x1058#define regCP_RB2_WPTR_BASE_IDX 0 #define regCP_RB_DOORBELL_CONTROL 0 x1059#define regCP_RB_DOORBELL_CONTROL_BASE_IDX 0 #define regCP_RB_DOORBELL_RANGE_LOWER 0 x105a#define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 #define regCP_RB_DOORBELL_RANGE_UPPER 0 x105b#define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 #define regCP_MEC_DOORBELL_RANGE_LOWER 0 x105c#define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 #define regCP_MEC_DOORBELL_RANGE_UPPER 0 x105d#define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 #define regCPG_UTCL1_ERROR 0 x105e#define regCPG_UTCL1_ERROR_BASE_IDX 0 #define regCPC_UTCL1_ERROR 0 x105f#define regCPC_UTCL1_ERROR_BASE_IDX 0 #define regCP_RB1_BASE 0 x1060#define regCP_RB1_BASE_BASE_IDX 0 #define regCP_RB1_CNTL 0 x1061#define regCP_RB1_CNTL_BASE_IDX 0 #define regCP_RB1_RPTR_ADDR 0 x1062#define regCP_RB1_RPTR_ADDR_BASE_IDX 0 #define regCP_RB1_RPTR_ADDR_HI 0 x1063#define regCP_RB1_RPTR_ADDR_HI_BASE_IDX 0 #define regCP_RB2_BASE 0 x1065#define regCP_RB2_BASE_BASE_IDX 0 #define regCP_RB2_CNTL 0 x1066#define regCP_RB2_CNTL_BASE_IDX 0 #define regCP_RB2_RPTR_ADDR 0 x1067#define regCP_RB2_RPTR_ADDR_BASE_IDX 0 #define regCP_RB2_RPTR_ADDR_HI 0 x1068#define regCP_RB2_RPTR_ADDR_HI_BASE_IDX 0 #define regCP_RB0_ACTIVE 0 x1069#define regCP_RB0_ACTIVE_BASE_IDX 0 #define regCP_RB_ACTIVE 0 x1069#define regCP_RB_ACTIVE_BASE_IDX 0 #define regCP_INT_CNTL_RING0 0 x106a#define regCP_INT_CNTL_RING0_BASE_IDX 0 #define regCP_INT_CNTL_RING1 0 x106b#define regCP_INT_CNTL_RING1_BASE_IDX 0 #define regCP_INT_CNTL_RING2 0 x106c#define regCP_INT_CNTL_RING2_BASE_IDX 0 #define regCP_INT_STATUS_RING0 0 x106d#define regCP_INT_STATUS_RING0_BASE_IDX 0 #define regCP_INT_STATUS_RING1 0 x106e#define regCP_INT_STATUS_RING1_BASE_IDX 0 #define regCP_INT_STATUS_RING2 0 x106f#define regCP_INT_STATUS_RING2_BASE_IDX 0 #define regCP_ME_F32_INTERRUPT 0 x1073#define regCP_ME_F32_INTERRUPT_BASE_IDX 0 #define regCP_PFP_F32_INTERRUPT 0 x1074#define regCP_PFP_F32_INTERRUPT_BASE_IDX 0 #define regCP_CE_F32_INTERRUPT 0 x1075#define regCP_CE_F32_INTERRUPT_BASE_IDX 0 #define regCP_MEC1_F32_INTERRUPT 0 x1076#define regCP_MEC1_F32_INTERRUPT_BASE_IDX 0 #define regCP_MEC2_F32_INTERRUPT 0 x1077#define regCP_MEC2_F32_INTERRUPT_BASE_IDX 0 #define regCP_PWR_CNTL 0 x1078#define regCP_PWR_CNTL_BASE_IDX 0 #define regCP_MEM_SLP_CNTL 0 x1079#define regCP_MEM_SLP_CNTL_BASE_IDX 0 #define regCP_ECC_DMA_FIRST_OCCURRENCE 0 x107a#define regCP_ECC_DMA_FIRST_OCCURRENCE_BASE_IDX 0 #define regCP_ECC_FIRSTOCCURRENCE 0 x107a#define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 #define regCP_ECC_FIRSTOCCURRENCE_RING0 0 x107b#define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 #define regCP_ECC_FIRSTOCCURRENCE_RING1 0 x107c#define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0 #define regCP_ECC_FIRSTOCCURRENCE_RING2 0 x107d#define regCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0 #define regGB_EDC_MODE 0 x107e#define regGB_EDC_MODE_BASE_IDX 0 #define regCP_PQ_WPTR_POLL_CNTL 0 x1083#define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 #define regCP_PQ_WPTR_POLL_CNTL1 0 x1084#define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 #define regCP_ME1_PIPE0_INT_CNTL 0 x1085#define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 #define regCP_ME1_PIPE1_INT_CNTL 0 x1086#define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 #define regCP_ME1_PIPE2_INT_CNTL 0 x1087#define regCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 #define regCP_ME1_PIPE3_INT_CNTL 0 x1088#define regCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 #define regCP_ME2_PIPE0_INT_CNTL 0 x1089#define regCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0 #define regCP_ME2_PIPE1_INT_CNTL 0 x108a#define regCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0 #define regCP_ME2_PIPE2_INT_CNTL 0 x108b#define regCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0 #define regCP_ME2_PIPE3_INT_CNTL 0 x108c#define regCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0 #define regCP_ME1_PIPE0_INT_STATUS 0 x108d#define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 #define regCP_ME1_PIPE1_INT_STATUS 0 x108e#define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 #define regCP_ME1_PIPE2_INT_STATUS 0 x108f#define regCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 #define regCP_ME1_PIPE3_INT_STATUS 0 x1090#define regCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 #define regCP_ME2_PIPE0_INT_STATUS 0 x1091#define regCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0 #define regCP_ME2_PIPE1_INT_STATUS 0 x1092#define regCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0 #define regCP_ME2_PIPE2_INT_STATUS 0 x1093#define regCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0 #define regCP_ME2_PIPE3_INT_STATUS 0 x1094#define regCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0 #define regCP_ME1_INT_STAT_DEBUG 0 x1095#define regCP_ME1_INT_STAT_DEBUG_BASE_IDX 0 #define regCP_ME2_INT_STAT_DEBUG 0 x1096#define regCP_ME2_INT_STAT_DEBUG_BASE_IDX 0 #define regCC_GC_EDC_CONFIG 0 x1098#define regCC_GC_EDC_CONFIG_BASE_IDX 0 #define regCP_ME1_PIPE_PRIORITY_CNTS 0 x1099#define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 #define regCP_ME1_PIPE0_PRIORITY 0 x109a#define regCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 #define regCP_ME1_PIPE1_PRIORITY 0 x109b#define regCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 #define regCP_ME1_PIPE2_PRIORITY 0 x109c#define regCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 #define regCP_ME1_PIPE3_PRIORITY 0 x109d#define regCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 #define regCP_ME2_PIPE_PRIORITY_CNTS 0 x109e#define regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0 #define regCP_ME2_PIPE0_PRIORITY 0 x109f#define regCP_ME2_PIPE0_PRIORITY_BASE_IDX 0 #define regCP_ME2_PIPE1_PRIORITY 0 x10a0#define regCP_ME2_PIPE1_PRIORITY_BASE_IDX 0 #define regCP_ME2_PIPE2_PRIORITY 0 x10a1#define regCP_ME2_PIPE2_PRIORITY_BASE_IDX 0 #define regCP_ME2_PIPE3_PRIORITY 0 x10a2#define regCP_ME2_PIPE3_PRIORITY_BASE_IDX 0 #define regCP_CE_PRGRM_CNTR_START 0 x10a3#define regCP_CE_PRGRM_CNTR_START_BASE_IDX 0 #define regCP_PFP_PRGRM_CNTR_START 0 x10a4#define regCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 #define regCP_ME_PRGRM_CNTR_START 0 x10a5#define regCP_ME_PRGRM_CNTR_START_BASE_IDX 0 #define regCP_MEC1_PRGRM_CNTR_START 0 x10a6#define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 #define regCP_MEC2_PRGRM_CNTR_START 0 x10a7#define regCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0 #define regCP_CE_INTR_ROUTINE_START 0 x10a8#define regCP_CE_INTR_ROUTINE_START_BASE_IDX 0 #define regCP_PFP_INTR_ROUTINE_START 0 x10a9#define regCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 #define regCP_ME_INTR_ROUTINE_START 0 x10aa#define regCP_ME_INTR_ROUTINE_START_BASE_IDX 0 #define regCP_MEC1_INTR_ROUTINE_START 0 x10ab#define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 #define regCP_MEC2_INTR_ROUTINE_START 0 x10ac#define regCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0 #define regCP_CONTEXT_CNTL 0 x10ad#define regCP_CONTEXT_CNTL_BASE_IDX 0 #define regCP_MAX_CONTEXT 0 x10ae#define regCP_MAX_CONTEXT_BASE_IDX 0 #define regCP_IQ_WAIT_TIME1 0 x10af#define regCP_IQ_WAIT_TIME1_BASE_IDX 0 #define regCP_IQ_WAIT_TIME2 0 x10b0#define regCP_IQ_WAIT_TIME2_BASE_IDX 0 #define regCP_RB0_BASE_HI 0 x10b1#define regCP_RB0_BASE_HI_BASE_IDX 0 #define regCP_RB1_BASE_HI 0 x10b2#define regCP_RB1_BASE_HI_BASE_IDX 0 #define regCP_VMID_RESET 0 x10b3#define regCP_VMID_RESET_BASE_IDX 0 #define regCPC_INT_CNTL 0 x10b4#define regCPC_INT_CNTL_BASE_IDX 0 #define regCPC_INT_STATUS 0 x10b5#define regCPC_INT_STATUS_BASE_IDX 0 #define regCP_VMID_PREEMPT 0 x10b6#define regCP_VMID_PREEMPT_BASE_IDX 0 #define regCPC_INT_CNTX_ID 0 x10b7#define regCPC_INT_CNTX_ID_BASE_IDX 0 #define regCP_PQ_STATUS 0 x10b8#define regCP_PQ_STATUS_BASE_IDX 0 #define regCP_CPC_IC_BASE_LO 0 x10b9#define regCP_CPC_IC_BASE_LO_BASE_IDX 0 #define regCP_CPC_IC_BASE_HI 0 x10ba#define regCP_CPC_IC_BASE_HI_BASE_IDX 0 #define regCP_CPC_IC_BASE_CNTL 0 x10bb#define regCP_CPC_IC_BASE_CNTL_BASE_IDX 0 #define regCP_CPC_IC_OP_CNTL 0 x10bc#define regCP_CPC_IC_OP_CNTL_BASE_IDX 0 #define regCP_MEC1_F32_INT_DIS 0 x10bd#define regCP_MEC1_F32_INT_DIS_BASE_IDX 0 #define regCP_MEC2_F32_INT_DIS 0 x10be#define regCP_MEC2_F32_INT_DIS_BASE_IDX 0 #define regCP_VMID_STATUS 0 x10bf#define regCP_VMID_STATUS_BASE_IDX 0 // addressBlock: gc_cppdec2 // base address: 0xc600 #define regCP_RB_DOORBELL_CONTROL_SCH_0 0 x1180#define regCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX 0 #define regCP_RB_DOORBELL_CONTROL_SCH_1 0 x1181#define regCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX 0 #define regCP_RB_DOORBELL_CONTROL_SCH_2 0 x1182#define regCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX 0 #define regCP_RB_DOORBELL_CONTROL_SCH_3 0 x1183#define regCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX 0 #define regCP_RB_DOORBELL_CONTROL_SCH_4 0 x1184#define regCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX 0 #define regCP_RB_DOORBELL_CONTROL_SCH_5 0 x1185#define regCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX 0 #define regCP_RB_DOORBELL_CONTROL_SCH_6 0 x1186#define regCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX 0 #define regCP_RB_DOORBELL_CONTROL_SCH_7 0 x1187#define regCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0 #define regCP_RB_DOORBELL_CLEAR 0 x1188#define regCP_RB_DOORBELL_CLEAR_BASE_IDX 0 #define regCPF_EDC_TAG_CNT 0 x1189#define regCPF_EDC_TAG_CNT_BASE_IDX 0 #define regCPF_EDC_ROQ_CNT 0 x118a#define regCPF_EDC_ROQ_CNT_BASE_IDX 0 #define regCPG_EDC_TAG_CNT 0 x118b#define regCPG_EDC_TAG_CNT_BASE_IDX 0 #define regCPG_EDC_DMA_CNT 0 x118d#define regCPG_EDC_DMA_CNT_BASE_IDX 0 #define regCPC_EDC_SCRATCH_CNT 0 x118e#define regCPC_EDC_SCRATCH_CNT_BASE_IDX 0 #define regCPC_EDC_UCODE_CNT 0 x118f#define regCPC_EDC_UCODE_CNT_BASE_IDX 0 #define regDC_EDC_STATE_CNT 0 x1191#define regDC_EDC_STATE_CNT_BASE_IDX 0 #define regDC_EDC_CSINVOC_CNT 0 x1192#define regDC_EDC_CSINVOC_CNT_BASE_IDX 0 #define regDC_EDC_RESTORE_CNT 0 x1193#define regDC_EDC_RESTORE_CNT_BASE_IDX 0 #define regCP_CPF_DSM_CNTL 0 x1194#define regCP_CPF_DSM_CNTL_BASE_IDX 0 #define regCP_CPG_DSM_CNTL 0 x1195#define regCP_CPG_DSM_CNTL_BASE_IDX 0 #define regCP_CPC_DSM_CNTL 0 x1196#define regCP_CPC_DSM_CNTL_BASE_IDX 0 #define regCP_CPF_DSM_CNTL2 0 x1197#define regCP_CPF_DSM_CNTL2_BASE_IDX 0 #define regCP_CPG_DSM_CNTL2 0 x1198#define regCP_CPG_DSM_CNTL2_BASE_IDX 0 #define regCP_CPC_DSM_CNTL2 0 x1199#define regCP_CPC_DSM_CNTL2_BASE_IDX 0 #define regCP_CPF_DSM_CNTL2A 0 x119a#define regCP_CPF_DSM_CNTL2A_BASE_IDX 0 #define regCP_CPG_DSM_CNTL2A 0 x119b#define regCP_CPG_DSM_CNTL2A_BASE_IDX 0 #define regCP_CPC_DSM_CNTL2A 0 x119c#define regCP_CPC_DSM_CNTL2A_BASE_IDX 0 #define regCP_EDC_FUE_CNTL 0 x119d#define regCP_EDC_FUE_CNTL_BASE_IDX 0 #define regCP_GFX_MQD_CONTROL 0 x11a0#define regCP_GFX_MQD_CONTROL_BASE_IDX 0 #define regCP_GFX_MQD_BASE_ADDR 0 x11a1#define regCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 #define regCP_GFX_MQD_BASE_ADDR_HI 0 x11a2#define regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 #define regCP_RB_STATUS 0 x11a3#define regCP_RB_STATUS_BASE_IDX 0 #define regCPG_UTCL1_STATUS 0 x11b4#define regCPG_UTCL1_STATUS_BASE_IDX 0 #define regCPC_UTCL1_STATUS 0 x11b5#define regCPC_UTCL1_STATUS_BASE_IDX 0 #define regCPF_UTCL1_STATUS 0 x11b6#define regCPF_UTCL1_STATUS_BASE_IDX 0 #define regCP_SD_CNTL 0 x11b7#define regCP_SD_CNTL_BASE_IDX 0 #define regCP_SOFT_RESET_CNTL 0 x11b9#define regCP_SOFT_RESET_CNTL_BASE_IDX 0 #define regCP_CPC_GFX_CNTL 0 x11ba#define regCP_CPC_GFX_CNTL_BASE_IDX 0 // addressBlock: gc_cpphqddec // base address: 0xc800 #define regCP_HQD_GFX_CONTROL 0 x123e#define regCP_HQD_GFX_CONTROL_BASE_IDX 0 #define regCP_HQD_GFX_STATUS 0 x123f#define regCP_HQD_GFX_STATUS_BASE_IDX 0 #define regCP_HPD_ROQ_OFFSETS 0 x1240#define regCP_HPD_ROQ_OFFSETS_BASE_IDX 0 #define regCP_HPD_STATUS0 0 x1241#define regCP_HPD_STATUS0_BASE_IDX 0 #define regCP_HPD_UTCL1_CNTL 0 x1242#define regCP_HPD_UTCL1_CNTL_BASE_IDX 0 #define regCP_HPD_UTCL1_ERROR 0 x1243#define regCP_HPD_UTCL1_ERROR_BASE_IDX 0 #define regCP_HPD_UTCL1_ERROR_ADDR 0 x1244#define regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 #define regCP_MQD_BASE_ADDR 0 x1245#define regCP_MQD_BASE_ADDR_BASE_IDX 0 #define regCP_MQD_BASE_ADDR_HI 0 x1246#define regCP_MQD_BASE_ADDR_HI_BASE_IDX 0 #define regCP_HQD_ACTIVE 0 x1247#define regCP_HQD_ACTIVE_BASE_IDX 0 #define regCP_HQD_VMID 0 x1248#define regCP_HQD_VMID_BASE_IDX 0 #define regCP_HQD_PERSISTENT_STATE 0 x1249#define regCP_HQD_PERSISTENT_STATE_BASE_IDX 0 #define regCP_HQD_PIPE_PRIORITY 0 x124a#define regCP_HQD_PIPE_PRIORITY_BASE_IDX 0 #define regCP_HQD_QUEUE_PRIORITY 0 x124b#define regCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 #define regCP_HQD_QUANTUM 0 x124c#define regCP_HQD_QUANTUM_BASE_IDX 0 #define regCP_HQD_PQ_BASE 0 x124d#define regCP_HQD_PQ_BASE_BASE_IDX 0 #define regCP_HQD_PQ_BASE_HI 0 x124e#define regCP_HQD_PQ_BASE_HI_BASE_IDX 0 #define regCP_HQD_PQ_RPTR 0 x124f#define regCP_HQD_PQ_RPTR_BASE_IDX 0 #define regCP_HQD_PQ_RPTR_REPORT_ADDR 0 x1250#define regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 #define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0 x1251#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 #define regCP_HQD_PQ_WPTR_POLL_ADDR 0 x1252#define regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI 0 x1253#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 #define regCP_HQD_PQ_DOORBELL_CONTROL 0 x1254#define regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 #define regCP_HQD_PQ_CONTROL 0 x1256#define regCP_HQD_PQ_CONTROL_BASE_IDX 0 #define regCP_HQD_IB_BASE_ADDR 0 x1257#define regCP_HQD_IB_BASE_ADDR_BASE_IDX 0 #define regCP_HQD_IB_BASE_ADDR_HI 0 x1258#define regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 #define regCP_HQD_IB_RPTR 0 x1259#define regCP_HQD_IB_RPTR_BASE_IDX 0 #define regCP_HQD_IB_CONTROL 0 x125a#define regCP_HQD_IB_CONTROL_BASE_IDX 0 #define regCP_HQD_IQ_TIMER 0 x125b#define regCP_HQD_IQ_TIMER_BASE_IDX 0 #define regCP_HQD_IQ_RPTR 0 x125c#define regCP_HQD_IQ_RPTR_BASE_IDX 0 #define regCP_HQD_DEQUEUE_REQUEST 0 x125d#define regCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 #define regCP_HQD_DMA_OFFLOAD 0 x125e#define regCP_HQD_DMA_OFFLOAD_BASE_IDX 0 #define regCP_HQD_OFFLOAD 0 x125e#define regCP_HQD_OFFLOAD_BASE_IDX 0 #define regCP_HQD_SEMA_CMD 0 x125f#define regCP_HQD_SEMA_CMD_BASE_IDX 0 #define regCP_HQD_MSG_TYPE 0 x1260#define regCP_HQD_MSG_TYPE_BASE_IDX 0 #define regCP_HQD_ATOMIC0_PREOP_LO 0 x1261#define regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 #define regCP_HQD_ATOMIC0_PREOP_HI 0 x1262#define regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 #define regCP_HQD_ATOMIC1_PREOP_LO 0 x1263#define regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 #define regCP_HQD_ATOMIC1_PREOP_HI 0 x1264#define regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 #define regCP_HQD_HQ_SCHEDULER0 0 x1265#define regCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 #define regCP_HQD_HQ_STATUS0 0 x1265#define regCP_HQD_HQ_STATUS0_BASE_IDX 0 #define regCP_HQD_HQ_CONTROL0 0 x1266#define regCP_HQD_HQ_CONTROL0_BASE_IDX 0 #define regCP_HQD_HQ_SCHEDULER1 0 x1266#define regCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 #define regCP_MQD_CONTROL 0 x1267#define regCP_MQD_CONTROL_BASE_IDX 0 #define regCP_HQD_HQ_STATUS1 0 x1268#define regCP_HQD_HQ_STATUS1_BASE_IDX 0 #define regCP_HQD_HQ_CONTROL1 0 x1269#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0 #define regCP_HQD_EOP_BASE_ADDR 0 x126a#define regCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 #define regCP_HQD_EOP_BASE_ADDR_HI 0 x126b#define regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 #define regCP_HQD_EOP_CONTROL 0 x126c#define regCP_HQD_EOP_CONTROL_BASE_IDX 0 #define regCP_HQD_EOP_RPTR 0 x126d#define regCP_HQD_EOP_RPTR_BASE_IDX 0 #define regCP_HQD_EOP_WPTR 0 x126e#define regCP_HQD_EOP_WPTR_BASE_IDX 0 #define regCP_HQD_EOP_EVENTS 0 x126f#define regCP_HQD_EOP_EVENTS_BASE_IDX 0 #define regCP_HQD_CTX_SAVE_BASE_ADDR_LO 0 x1270#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 #define regCP_HQD_CTX_SAVE_BASE_ADDR_HI 0 x1271#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 #define regCP_HQD_CTX_SAVE_CONTROL 0 x1272#define regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 #define regCP_HQD_CNTL_STACK_OFFSET 0 x1273#define regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 #define regCP_HQD_CNTL_STACK_SIZE 0 x1274#define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 #define regCP_HQD_WG_STATE_OFFSET 0 x1275#define regCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 #define regCP_HQD_CTX_SAVE_SIZE 0 x1276#define regCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 #define regCP_HQD_GDS_RESOURCE_STATE 0 x1277#define regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 #define regCP_HQD_ERROR 0 x1278#define regCP_HQD_ERROR_BASE_IDX 0 #define regCP_HQD_EOP_WPTR_MEM 0 x1279#define regCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 #define regCP_HQD_AQL_CONTROL 0 x127a#define regCP_HQD_AQL_CONTROL_BASE_IDX 0 #define regCP_HQD_PQ_WPTR_LO 0 x127b#define regCP_HQD_PQ_WPTR_LO_BASE_IDX 0 #define regCP_HQD_PQ_WPTR_HI 0 x127c#define regCP_HQD_PQ_WPTR_HI_BASE_IDX 0 // addressBlock: gc_didtdec // base address: 0xca00 #define regDIDT_IND_INDEX 0 x1280#define regDIDT_IND_INDEX_BASE_IDX 0 #define regDIDT_IND_DATA 0 x1281#define regDIDT_IND_DATA_BASE_IDX 0 #define regDIDT_INDEX_AUTO_INCR_EN 0 x1282#define regDIDT_INDEX_AUTO_INCR_EN_BASE_IDX 0 // addressBlock: gc_ea_gceadec // base address: 0xa800 #define regGCEA_DRAM_RD_CLI2GRP_MAP0 0 x0a00#define regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 #define regGCEA_DRAM_RD_CLI2GRP_MAP1 0 x0a01#define regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 #define regGCEA_DRAM_WR_CLI2GRP_MAP0 0 x0a02#define regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 #define regGCEA_DRAM_WR_CLI2GRP_MAP1 0 x0a03#define regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 #define regGCEA_DRAM_RD_GRP2VC_MAP 0 x0a04#define regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 #define regGCEA_DRAM_WR_GRP2VC_MAP 0 x0a05#define regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 #define regGCEA_DRAM_RD_LAZY 0 x0a06#define regGCEA_DRAM_RD_LAZY_BASE_IDX 0 #define regGCEA_DRAM_WR_LAZY 0 x0a07#define regGCEA_DRAM_WR_LAZY_BASE_IDX 0 #define regGCEA_DRAM_RD_CAM_CNTL 0 x0a08#define regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX 0 #define regGCEA_DRAM_WR_CAM_CNTL 0 x0a09#define regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX 0 #define regGCEA_DRAM_PAGE_BURST 0 x0a0a#define regGCEA_DRAM_PAGE_BURST_BASE_IDX 0 #define regGCEA_DRAM_RD_PRI_AGE 0 x0a0b#define regGCEA_DRAM_RD_PRI_AGE_BASE_IDX 0 #define regGCEA_DRAM_WR_PRI_AGE 0 x0a0c#define regGCEA_DRAM_WR_PRI_AGE_BASE_IDX 0 #define regGCEA_DRAM_RD_PRI_QUEUING 0 x0a0d#define regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX 0 #define regGCEA_DRAM_WR_PRI_QUEUING 0 x0a0e#define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX 0 #define regGCEA_DRAM_RD_PRI_FIXED 0 x0a0f#define regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX 0 #define regGCEA_DRAM_WR_PRI_FIXED 0 x0a10#define regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX 0 #define regGCEA_DRAM_RD_PRI_URGENCY 0 x0a11#define regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX 0 #define regGCEA_DRAM_WR_PRI_URGENCY 0 x0a12#define regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX 0 #define regGCEA_DRAM_RD_PRI_QUANT_PRI1 0 x0a13#define regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 #define regGCEA_DRAM_RD_PRI_QUANT_PRI2 0 x0a14#define regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 #define regGCEA_DRAM_RD_PRI_QUANT_PRI3 0 x0a15#define regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 #define regGCEA_DRAM_WR_PRI_QUANT_PRI1 0 x0a16#define regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 #define regGCEA_DRAM_WR_PRI_QUANT_PRI2 0 x0a17#define regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 #define regGCEA_DRAM_WR_PRI_QUANT_PRI3 0 x0a18#define regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 #define regGCEA_ADDRNORM_BASE_ADDR0 0 x0a34#define regGCEA_ADDRNORM_BASE_ADDR0_BASE_IDX 0 #define regGCEA_ADDRNORM_LIMIT_ADDR0 0 x0a35#define regGCEA_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 #define regGCEA_ADDRNORM_BASE_ADDR1 0 x0a36#define regGCEA_ADDRNORM_BASE_ADDR1_BASE_IDX 0 #define regGCEA_ADDRNORM_LIMIT_ADDR1 0 x0a37#define regGCEA_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 #define regGCEA_ADDRNORM_OFFSET_ADDR1 0 x0a38#define regGCEA_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 #define regGCEA_ADDRNORM_BASE_ADDR2 0 x0a39#define regGCEA_ADDRNORM_BASE_ADDR2_BASE_IDX 0 #define regGCEA_ADDRNORM_LIMIT_ADDR2 0 x0a3a#define regGCEA_ADDRNORM_LIMIT_ADDR2_BASE_IDX 0 #define regGCEA_ADDRNORM_BASE_ADDR3 0 x0a3b#define regGCEA_ADDRNORM_BASE_ADDR3_BASE_IDX 0 #define regGCEA_ADDRNORM_LIMIT_ADDR3 0 x0a3c#define regGCEA_ADDRNORM_LIMIT_ADDR3_BASE_IDX 0 #define regGCEA_ADDRNORM_OFFSET_ADDR3 0 x0a3d#define regGCEA_ADDRNORM_OFFSET_ADDR3_BASE_IDX 0 #define regGCEA_ADDRNORM_MEGABASE_ADDR0 0 x0a3e#define regGCEA_ADDRNORM_MEGABASE_ADDR0_BASE_IDX 0 #define regGCEA_ADDRNORM_MEGALIMIT_ADDR0 0 x0a3f#define regGCEA_ADDRNORM_MEGALIMIT_ADDR0_BASE_IDX 0 #define regGCEA_ADDRNORM_MEGABASE_ADDR1 0 x0a40#define regGCEA_ADDRNORM_MEGABASE_ADDR1_BASE_IDX 0 #define regGCEA_ADDRNORM_MEGALIMIT_ADDR1 0 x0a41#define regGCEA_ADDRNORM_MEGALIMIT_ADDR1_BASE_IDX 0 #define regGCEA_ADDRNORMDRAM_HOLE_CNTL 0 x0a43#define regGCEA_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 #define regGCEA_ADDRNORMGMI_HOLE_CNTL 0 x0a44#define regGCEA_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 0 #define regGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 x0a45#define regGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 #define regGCEA_ADDRNORMGMI_NP2_CHANNEL_CFG 0 x0a46#define regGCEA_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 0 #define regGCEA_ADDRDEC_BANK_CFG 0 x0a47#define regGCEA_ADDRDEC_BANK_CFG_BASE_IDX 0 #define regGCEA_ADDRDEC_MISC_CFG 0 x0a48#define regGCEA_ADDRDEC_MISC_CFG_BASE_IDX 0 #define regGCEA_ADDRDECDRAM_HARVEST_ENABLE 0 x0a53#define regGCEA_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 #define regGCEA_ADDRDECGMI_HARVEST_ENABLE 0 x0a5e#define regGCEA_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 0 #define regGCEA_ADDRDEC0_BASE_ADDR_CS0 0 x0a5f#define regGCEA_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 #define regGCEA_ADDRDEC0_BASE_ADDR_CS1 0 x0a60#define regGCEA_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 #define regGCEA_ADDRDEC0_BASE_ADDR_CS2 0 x0a61#define regGCEA_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 #define regGCEA_ADDRDEC0_BASE_ADDR_CS3 0 x0a62#define regGCEA_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 #define regGCEA_ADDRDEC0_BASE_ADDR_SECCS0 0 x0a63#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 #define regGCEA_ADDRDEC0_BASE_ADDR_SECCS1 0 x0a64#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 #define regGCEA_ADDRDEC0_BASE_ADDR_SECCS2 0 x0a65#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 #define regGCEA_ADDRDEC0_BASE_ADDR_SECCS3 0 x0a66#define regGCEA_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 #define regGCEA_ADDRDEC0_ADDR_MASK_CS01 0 x0a67#define regGCEA_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC0_ADDR_MASK_CS23 0 x0a68#define regGCEA_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC0_ADDR_MASK_SECCS01 0 x0a69#define regGCEA_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 #define regGCEA_ADDRDEC0_ADDR_MASK_SECCS23 0 x0a6a#define regGCEA_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 #define regGCEA_ADDRDEC0_ADDR_CFG_CS01 0 x0a6b#define regGCEA_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC0_ADDR_CFG_CS23 0 x0a6c#define regGCEA_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC0_ADDR_SEL_CS01 0 x0a6d#define regGCEA_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC0_ADDR_SEL_CS23 0 x0a6e#define regGCEA_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC0_ADDR_SEL2_CS01 0 x0a6f#define regGCEA_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC0_ADDR_SEL2_CS23 0 x0a70#define regGCEA_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC0_COL_SEL_LO_CS01 0 x0a71#define regGCEA_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC0_COL_SEL_LO_CS23 0 x0a72#define regGCEA_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC0_COL_SEL_HI_CS01 0 x0a73#define regGCEA_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC0_COL_SEL_HI_CS23 0 x0a74#define regGCEA_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC0_RM_SEL_CS01 0 x0a75#define regGCEA_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC0_RM_SEL_CS23 0 x0a76#define regGCEA_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC0_RM_SEL_SECCS01 0 x0a77#define regGCEA_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 #define regGCEA_ADDRDEC0_RM_SEL_SECCS23 0 x0a78#define regGCEA_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 #define regGCEA_ADDRDEC1_BASE_ADDR_CS0 0 x0a79#define regGCEA_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 #define regGCEA_ADDRDEC1_BASE_ADDR_CS1 0 x0a7a#define regGCEA_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 #define regGCEA_ADDRDEC1_BASE_ADDR_CS2 0 x0a7b#define regGCEA_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 #define regGCEA_ADDRDEC1_BASE_ADDR_CS3 0 x0a7c#define regGCEA_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 #define regGCEA_ADDRDEC1_BASE_ADDR_SECCS0 0 x0a7d#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 #define regGCEA_ADDRDEC1_BASE_ADDR_SECCS1 0 x0a7e#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 #define regGCEA_ADDRDEC1_BASE_ADDR_SECCS2 0 x0a7f#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 #define regGCEA_ADDRDEC1_BASE_ADDR_SECCS3 0 x0a80#define regGCEA_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 #define regGCEA_ADDRDEC1_ADDR_MASK_CS01 0 x0a81#define regGCEA_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC1_ADDR_MASK_CS23 0 x0a82#define regGCEA_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC1_ADDR_MASK_SECCS01 0 x0a83#define regGCEA_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 #define regGCEA_ADDRDEC1_ADDR_MASK_SECCS23 0 x0a84#define regGCEA_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 #define regGCEA_ADDRDEC1_ADDR_CFG_CS01 0 x0a85#define regGCEA_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC1_ADDR_CFG_CS23 0 x0a86#define regGCEA_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC1_ADDR_SEL_CS01 0 x0a87#define regGCEA_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC1_ADDR_SEL_CS23 0 x0a88#define regGCEA_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC1_ADDR_SEL2_CS01 0 x0a89#define regGCEA_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC1_ADDR_SEL2_CS23 0 x0a8a#define regGCEA_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC1_COL_SEL_LO_CS01 0 x0a8b#define regGCEA_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC1_COL_SEL_LO_CS23 0 x0a8c#define regGCEA_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC1_COL_SEL_HI_CS01 0 x0a8d#define regGCEA_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC1_COL_SEL_HI_CS23 0 x0a8e#define regGCEA_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC1_RM_SEL_CS01 0 x0a8f#define regGCEA_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC1_RM_SEL_CS23 0 x0a90#define regGCEA_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC1_RM_SEL_SECCS01 0 x0a91#define regGCEA_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 #define regGCEA_ADDRDEC1_RM_SEL_SECCS23 0 x0a92#define regGCEA_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 #define regGCEA_ADDRDEC2_BASE_ADDR_CS0 0 x0a93#define regGCEA_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 0 #define regGCEA_ADDRDEC2_BASE_ADDR_CS1 0 x0a94#define regGCEA_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 0 #define regGCEA_ADDRDEC2_BASE_ADDR_CS2 0 x0a95#define regGCEA_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 0 #define regGCEA_ADDRDEC2_BASE_ADDR_CS3 0 x0a96#define regGCEA_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 0 #define regGCEA_ADDRDEC2_BASE_ADDR_SECCS0 0 x0a97#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 0 #define regGCEA_ADDRDEC2_BASE_ADDR_SECCS1 0 x0a98#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 0 #define regGCEA_ADDRDEC2_BASE_ADDR_SECCS2 0 x0a99#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 0 #define regGCEA_ADDRDEC2_BASE_ADDR_SECCS3 0 x0a9a#define regGCEA_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 0 #define regGCEA_ADDRDEC2_ADDR_MASK_CS01 0 x0a9b#define regGCEA_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC2_ADDR_MASK_CS23 0 x0a9c#define regGCEA_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC2_ADDR_MASK_SECCS01 0 x0a9d#define regGCEA_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 0 #define regGCEA_ADDRDEC2_ADDR_MASK_SECCS23 0 x0a9e#define regGCEA_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 0 #define regGCEA_ADDRDEC2_ADDR_CFG_CS01 0 x0a9f#define regGCEA_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC2_ADDR_CFG_CS23 0 x0aa0#define regGCEA_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC2_ADDR_SEL_CS01 0 x0aa1#define regGCEA_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC2_ADDR_SEL_CS23 0 x0aa2#define regGCEA_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC2_ADDR_SEL2_CS01 0 x0aa3#define regGCEA_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC2_ADDR_SEL2_CS23 0 x0aa4#define regGCEA_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC2_COL_SEL_LO_CS01 0 x0aa5#define regGCEA_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC2_COL_SEL_LO_CS23 0 x0aa6#define regGCEA_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC2_COL_SEL_HI_CS01 0 x0aa7#define regGCEA_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC2_COL_SEL_HI_CS23 0 x0aa8#define regGCEA_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC2_RM_SEL_CS01 0 x0aa9#define regGCEA_ADDRDEC2_RM_SEL_CS01_BASE_IDX 0 #define regGCEA_ADDRDEC2_RM_SEL_CS23 0 x0aaa#define regGCEA_ADDRDEC2_RM_SEL_CS23_BASE_IDX 0 #define regGCEA_ADDRDEC2_RM_SEL_SECCS01 0 x0aab#define regGCEA_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 0 #define regGCEA_ADDRDEC2_RM_SEL_SECCS23 0 x0aac#define regGCEA_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 0 #define regGCEA_ADDRNORMDRAM_GLOBAL_CNTL 0 x0aad#define regGCEA_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 0 #define regGCEA_ADDRNORMGMI_GLOBAL_CNTL 0 x0aae#define regGCEA_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 0 #define regGCEA_ADDRNORM_MEGACONTROL_ADDR0 0 x0ad1#define regGCEA_ADDRNORM_MEGACONTROL_ADDR0_BASE_IDX 0 #define regGCEA_ADDRNORM_MEGACONTROL_ADDR1 0 x0ad2#define regGCEA_ADDRNORM_MEGACONTROL_ADDR1_BASE_IDX 0 #define regGCEA_ADDRNORMDRAM_MASKING 0 x0ad3#define regGCEA_ADDRNORMDRAM_MASKING_BASE_IDX 0 #define regGCEA_ADDRNORMGMI_MASKING 0 x0ad4#define regGCEA_ADDRNORMGMI_MASKING_BASE_IDX 0 #define regGCEA_IO_RD_CLI2GRP_MAP0 0 x0ad5#define regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 #define regGCEA_IO_RD_CLI2GRP_MAP1 0 x0ad6#define regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 #define regGCEA_IO_WR_CLI2GRP_MAP0 0 x0ad7#define regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 #define regGCEA_IO_WR_CLI2GRP_MAP1 0 x0ad8#define regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 #define regGCEA_IO_RD_COMBINE_FLUSH 0 x0ad9#define regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX 0 #define regGCEA_IO_WR_COMBINE_FLUSH 0 x0ada#define regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX 0 #define regGCEA_IO_GROUP_BURST 0 x0adb#define regGCEA_IO_GROUP_BURST_BASE_IDX 0 #define regGCEA_IO_RD_PRI_AGE 0 x0adc#define regGCEA_IO_RD_PRI_AGE_BASE_IDX 0 #define regGCEA_IO_WR_PRI_AGE 0 x0add#define regGCEA_IO_WR_PRI_AGE_BASE_IDX 0 #define regGCEA_IO_RD_PRI_QUEUING 0 x0ade#define regGCEA_IO_RD_PRI_QUEUING_BASE_IDX 0 #define regGCEA_IO_WR_PRI_QUEUING 0 x0adf#define regGCEA_IO_WR_PRI_QUEUING_BASE_IDX 0 #define regGCEA_IO_RD_PRI_FIXED 0 x0ae0#define regGCEA_IO_RD_PRI_FIXED_BASE_IDX 0 #define regGCEA_IO_WR_PRI_FIXED 0 x0ae1#define regGCEA_IO_WR_PRI_FIXED_BASE_IDX 0 #define regGCEA_IO_RD_PRI_URGENCY 0 x0ae2#define regGCEA_IO_RD_PRI_URGENCY_BASE_IDX 0 #define regGCEA_IO_WR_PRI_URGENCY 0 x0ae3#define regGCEA_IO_WR_PRI_URGENCY_BASE_IDX 0 #define regGCEA_IO_RD_PRI_URGENCY_MASKING 0 x0ae4#define regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 #define regGCEA_IO_WR_PRI_URGENCY_MASKING 0 x0ae5#define regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 #define regGCEA_IO_RD_PRI_QUANT_PRI1 0 x0ae6#define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 #define regGCEA_IO_RD_PRI_QUANT_PRI2 0 x0ae7#define regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 #define regGCEA_IO_RD_PRI_QUANT_PRI3 0 x0ae8#define regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 #define regGCEA_IO_WR_PRI_QUANT_PRI1 0 x0ae9#define regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 #define regGCEA_IO_WR_PRI_QUANT_PRI2 0 x0aea#define regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 #define regGCEA_IO_WR_PRI_QUANT_PRI3 0 x0aeb#define regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 #define regGCEA_MISC 0 x0afa#define regGCEA_MISC_BASE_IDX 0 #define regGCEA_LATENCY_SAMPLING 0 x0afb#define regGCEA_LATENCY_SAMPLING_BASE_IDX 0 #define regGCEA_PERFCOUNTER_LO 0 x0afc#define regGCEA_PERFCOUNTER_LO_BASE_IDX 0 #define regGCEA_PERFCOUNTER_HI 0 x0afd#define regGCEA_PERFCOUNTER_HI_BASE_IDX 0 #define regGCEA_PERFCOUNTER0_CFG 0 x0afe#define regGCEA_PERFCOUNTER0_CFG_BASE_IDX 0 #define regGCEA_PERFCOUNTER1_CFG 0 x0aff#define regGCEA_PERFCOUNTER1_CFG_BASE_IDX 0 // addressBlock: gc_ea_gceadec2 // base address: 0x9c00 #define regGCEA_PERFCOUNTER_RSLT_CNTL 0 x0700#define regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 #define regGCEA_EDC_CNT 0 x0706#define regGCEA_EDC_CNT_BASE_IDX 0 #define regGCEA_EDC_CNT2 0 x0707#define regGCEA_EDC_CNT2_BASE_IDX 0 #define regGCEA_DSM_CNTL 0 x0708#define regGCEA_DSM_CNTL_BASE_IDX 0 #define regGCEA_DSM_CNTLA 0 x0709#define regGCEA_DSM_CNTLA_BASE_IDX 0 #define regGCEA_DSM_CNTLB 0 x070a#define regGCEA_DSM_CNTLB_BASE_IDX 0 #define regGCEA_DSM_CNTL2 0 x070b#define regGCEA_DSM_CNTL2_BASE_IDX 0 #define regGCEA_DSM_CNTL2A 0 x070c#define regGCEA_DSM_CNTL2A_BASE_IDX 0 #define regGCEA_DSM_CNTL2B 0 x070d#define regGCEA_DSM_CNTL2B_BASE_IDX 0 #define regGCEA_TCC_XBR_CREDITS 0 x070e#define regGCEA_TCC_XBR_CREDITS_BASE_IDX 0 #define regGCEA_TCC_XBR_MAXBURST 0 x070f#define regGCEA_TCC_XBR_MAXBURST_BASE_IDX 0 #define regGCEA_PROBE_CNTL 0 x0710#define regGCEA_PROBE_CNTL_BASE_IDX 0 #define regGCEA_PROBE_MAP 0 x0711#define regGCEA_PROBE_MAP_BASE_IDX 0 #define regGCEA_ERR_STATUS 0 x0712#define regGCEA_ERR_STATUS_BASE_IDX 0 #define regGCEA_MISC2 0 x0713#define regGCEA_MISC2_BASE_IDX 0 #define regGCEA_DRAM_BANK_ARB 0 x0714#define regGCEA_DRAM_BANK_ARB_BASE_IDX 0 #define regGCEA_ADDRDEC_SELECT 0 x071a#define regGCEA_ADDRDEC_SELECT_BASE_IDX 0 #define regGCEA_EDC_CNT3 0 x071b#define regGCEA_EDC_CNT3_BASE_IDX 0 // addressBlock: gc_ea_pwrdec // base address: 0x3c000 #define regGCEA_CGTT_CLK_CTRL 0 x50c4#define regGCEA_CGTT_CLK_CTRL_BASE_IDX 1 // addressBlock: gc_gccacdec // base address: 0xca10 #define regGC_CAC_CTRL_1 0 x1284#define regGC_CAC_CTRL_1_BASE_IDX 0 #define regGC_CAC_CTRL_2 0 x1285#define regGC_CAC_CTRL_2_BASE_IDX 0 #define regGC_CAC_INDEX_AUTO_INCR_EN 0 x1286#define regGC_CAC_INDEX_AUTO_INCR_EN_BASE_IDX 0 #define regGC_CAC_AGGR_LOWER 0 x1287#define regGC_CAC_AGGR_LOWER_BASE_IDX 0 #define regGC_CAC_AGGR_UPPER 0 x1288#define regGC_CAC_AGGR_UPPER_BASE_IDX 0 #define regGC_EDC_PERF_COUNTER 0 x1289#define regGC_EDC_PERF_COUNTER_BASE_IDX 0 #define regPCC_PERF_COUNTER 0 x128a#define regPCC_PERF_COUNTER_BASE_IDX 0 #define regGC_CAC_SOFT_CTRL 0 x128d#define regGC_CAC_SOFT_CTRL_BASE_IDX 0 #define regGC_DIDT_CTRL0 0 x128e#define regGC_DIDT_CTRL0_BASE_IDX 0 #define regGC_DIDT_CTRL1 0 x128f#define regGC_DIDT_CTRL1_BASE_IDX 0 #define regGC_DIDT_CTRL2 0 x1290#define regGC_DIDT_CTRL2_BASE_IDX 0 #define regGC_DIDT_WEIGHT 0 x1291#define regGC_DIDT_WEIGHT_BASE_IDX 0 #define regGC_THROTTLE_CTRL1 0 x1292#define regGC_THROTTLE_CTRL1_BASE_IDX 0 #define regGC_EDC_CTRL 0 x1293#define regGC_EDC_CTRL_BASE_IDX 0 #define regGC_EDC_THRESHOLD 0 x1294#define regGC_EDC_THRESHOLD_BASE_IDX 0 #define regGC_EDC_STATUS 0 x1295#define regGC_EDC_STATUS_BASE_IDX 0 #define regGC_EDC_OVERFLOW 0 x1296#define regGC_EDC_OVERFLOW_BASE_IDX 0 #define regGC_EDC_ROLLING_POWER_DELTA 0 x1297#define regGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 0 #define regGC_EDC_CTRL1 0 x1298#define regGC_EDC_CTRL1_BASE_IDX 0 #define regGC_THROTTLE_CTRL2 0 x1299#define regGC_THROTTLE_CTRL2_BASE_IDX 0 #define regPWRBRK_PERF_COUNTER 0 x129a#define regPWRBRK_PERF_COUNTER_BASE_IDX 0 #define regGC_THROTTLE_CTRL 0 x129b#define regGC_THROTTLE_CTRL_BASE_IDX 0 #define regGC_CAC_IND_INDEX 0 x129c#define regGC_CAC_IND_INDEX_BASE_IDX 0 #define regGC_CAC_IND_DATA 0 x129d#define regGC_CAC_IND_DATA_BASE_IDX 0 #define regSE_CAC_IND_INDEX 0 x129e#define regSE_CAC_IND_INDEX_BASE_IDX 0 #define regSE_CAC_IND_DATA 0 x129f#define regSE_CAC_IND_DATA_BASE_IDX 0 // addressBlock: gc_gdsdec // base address: 0x9700 #define regGDS_CONFIG 0 x05c0#define regGDS_CONFIG_BASE_IDX 0 #define regGDS_CNTL_STATUS 0 x05c1#define regGDS_CNTL_STATUS_BASE_IDX 0 #define regGDS_ENHANCE2 0 x05c2#define regGDS_ENHANCE2_BASE_IDX 0 #define regGDS_PROTECTION_FAULT 0 x05c3#define regGDS_PROTECTION_FAULT_BASE_IDX 0 #define regGDS_VM_PROTECTION_FAULT 0 x05c4#define regGDS_VM_PROTECTION_FAULT_BASE_IDX 0 #define regGDS_EDC_CNT 0 x05c5#define regGDS_EDC_CNT_BASE_IDX 0 #define regGDS_EDC_GRBM_CNT 0 x05c6#define regGDS_EDC_GRBM_CNT_BASE_IDX 0 #define regGDS_EDC_OA_DED 0 x05c7#define regGDS_EDC_OA_DED_BASE_IDX 0 #define regGDS_DSM_CNTL 0 x05ca#define regGDS_DSM_CNTL_BASE_IDX 0 #define regGDS_EDC_OA_PHY_CNT 0 x05cb#define regGDS_EDC_OA_PHY_CNT_BASE_IDX 0 #define regGDS_EDC_OA_PIPE_CNT 0 x05cc#define regGDS_EDC_OA_PIPE_CNT_BASE_IDX 0 #define regGDS_DSM_CNTL2 0 x05cd#define regGDS_DSM_CNTL2_BASE_IDX 0 #define regGDS_WD_GDS_CSB 0 x05ce#define regGDS_WD_GDS_CSB_BASE_IDX 0 // addressBlock: gc_gdspdec // base address: 0xcc00 #define regGDS_VMID0_BASE 0 x1300#define regGDS_VMID0_BASE_BASE_IDX 0 #define regGDS_VMID0_SIZE 0 x1301#define regGDS_VMID0_SIZE_BASE_IDX 0 #define regGDS_VMID1_BASE 0 x1302#define regGDS_VMID1_BASE_BASE_IDX 0 #define regGDS_VMID1_SIZE 0 x1303#define regGDS_VMID1_SIZE_BASE_IDX 0 #define regGDS_VMID2_BASE 0 x1304#define regGDS_VMID2_BASE_BASE_IDX 0 #define regGDS_VMID2_SIZE 0 x1305#define regGDS_VMID2_SIZE_BASE_IDX 0 #define regGDS_VMID3_BASE 0 x1306#define regGDS_VMID3_BASE_BASE_IDX 0 #define regGDS_VMID3_SIZE 0 x1307#define regGDS_VMID3_SIZE_BASE_IDX 0 #define regGDS_VMID4_BASE 0 x1308#define regGDS_VMID4_BASE_BASE_IDX 0 #define regGDS_VMID4_SIZE 0 x1309#define regGDS_VMID4_SIZE_BASE_IDX 0 #define regGDS_VMID5_BASE 0 x130a#define regGDS_VMID5_BASE_BASE_IDX 0 #define regGDS_VMID5_SIZE 0 x130b#define regGDS_VMID5_SIZE_BASE_IDX 0 #define regGDS_VMID6_BASE 0 x130c#define regGDS_VMID6_BASE_BASE_IDX 0 #define regGDS_VMID6_SIZE 0 x130d#define regGDS_VMID6_SIZE_BASE_IDX 0 #define regGDS_VMID7_BASE 0 x130e#define regGDS_VMID7_BASE_BASE_IDX 0 #define regGDS_VMID7_SIZE 0 x130f#define regGDS_VMID7_SIZE_BASE_IDX 0 #define regGDS_VMID8_BASE 0 x1310#define regGDS_VMID8_BASE_BASE_IDX 0 #define regGDS_VMID8_SIZE 0 x1311#define regGDS_VMID8_SIZE_BASE_IDX 0 #define regGDS_VMID9_BASE 0 x1312#define regGDS_VMID9_BASE_BASE_IDX 0 #define regGDS_VMID9_SIZE 0 x1313#define regGDS_VMID9_SIZE_BASE_IDX 0 #define regGDS_VMID10_BASE 0 x1314#define regGDS_VMID10_BASE_BASE_IDX 0 #define regGDS_VMID10_SIZE 0 x1315#define regGDS_VMID10_SIZE_BASE_IDX 0 #define regGDS_VMID11_BASE 0 x1316#define regGDS_VMID11_BASE_BASE_IDX 0 #define regGDS_VMID11_SIZE 0 x1317#define regGDS_VMID11_SIZE_BASE_IDX 0 #define regGDS_VMID12_BASE 0 x1318#define regGDS_VMID12_BASE_BASE_IDX 0 #define regGDS_VMID12_SIZE 0 x1319#define regGDS_VMID12_SIZE_BASE_IDX 0 #define regGDS_VMID13_BASE 0 x131a#define regGDS_VMID13_BASE_BASE_IDX 0 #define regGDS_VMID13_SIZE 0 x131b#define regGDS_VMID13_SIZE_BASE_IDX 0 #define regGDS_VMID14_BASE 0 x131c#define regGDS_VMID14_BASE_BASE_IDX 0 #define regGDS_VMID14_SIZE 0 x131d#define regGDS_VMID14_SIZE_BASE_IDX 0 #define regGDS_VMID15_BASE 0 x131e#define regGDS_VMID15_BASE_BASE_IDX 0 #define regGDS_VMID15_SIZE 0 x131f#define regGDS_VMID15_SIZE_BASE_IDX 0 #define regGDS_GWS_VMID0 0 x1320#define regGDS_GWS_VMID0_BASE_IDX 0 #define regGDS_GWS_VMID1 0 x1321#define regGDS_GWS_VMID1_BASE_IDX 0 #define regGDS_GWS_VMID2 0 x1322#define regGDS_GWS_VMID2_BASE_IDX 0 #define regGDS_GWS_VMID3 0 x1323#define regGDS_GWS_VMID3_BASE_IDX 0 #define regGDS_GWS_VMID4 0 x1324#define regGDS_GWS_VMID4_BASE_IDX 0 #define regGDS_GWS_VMID5 0 x1325#define regGDS_GWS_VMID5_BASE_IDX 0 #define regGDS_GWS_VMID6 0 x1326#define regGDS_GWS_VMID6_BASE_IDX 0 #define regGDS_GWS_VMID7 0 x1327#define regGDS_GWS_VMID7_BASE_IDX 0 #define regGDS_GWS_VMID8 0 x1328#define regGDS_GWS_VMID8_BASE_IDX 0 #define regGDS_GWS_VMID9 0 x1329#define regGDS_GWS_VMID9_BASE_IDX 0 #define regGDS_GWS_VMID10 0 x132a#define regGDS_GWS_VMID10_BASE_IDX 0 #define regGDS_GWS_VMID11 0 x132b#define regGDS_GWS_VMID11_BASE_IDX 0 #define regGDS_GWS_VMID12 0 x132c#define regGDS_GWS_VMID12_BASE_IDX 0 #define regGDS_GWS_VMID13 0 x132d#define regGDS_GWS_VMID13_BASE_IDX 0 #define regGDS_GWS_VMID14 0 x132e#define regGDS_GWS_VMID14_BASE_IDX 0 #define regGDS_GWS_VMID15 0 x132f#define regGDS_GWS_VMID15_BASE_IDX 0 #define regGDS_OA_VMID0 0 x1330#define regGDS_OA_VMID0_BASE_IDX 0 #define regGDS_OA_VMID1 0 x1331#define regGDS_OA_VMID1_BASE_IDX 0 #define regGDS_OA_VMID2 0 x1332#define regGDS_OA_VMID2_BASE_IDX 0 #define regGDS_OA_VMID3 0 x1333#define regGDS_OA_VMID3_BASE_IDX 0 #define regGDS_OA_VMID4 0 x1334#define regGDS_OA_VMID4_BASE_IDX 0 #define regGDS_OA_VMID5 0 x1335#define regGDS_OA_VMID5_BASE_IDX 0 #define regGDS_OA_VMID6 0 x1336#define regGDS_OA_VMID6_BASE_IDX 0 #define regGDS_OA_VMID7 0 x1337#define regGDS_OA_VMID7_BASE_IDX 0 #define regGDS_OA_VMID8 0 x1338#define regGDS_OA_VMID8_BASE_IDX 0 #define regGDS_OA_VMID9 0 x1339#define regGDS_OA_VMID9_BASE_IDX 0 #define regGDS_OA_VMID10 0 x133a#define regGDS_OA_VMID10_BASE_IDX 0 #define regGDS_OA_VMID11 0 x133b#define regGDS_OA_VMID11_BASE_IDX 0 #define regGDS_OA_VMID12 0 x133c#define regGDS_OA_VMID12_BASE_IDX 0 #define regGDS_OA_VMID13 0 x133d#define regGDS_OA_VMID13_BASE_IDX 0 #define regGDS_OA_VMID14 0 x133e#define regGDS_OA_VMID14_BASE_IDX 0 #define regGDS_OA_VMID15 0 x133f#define regGDS_OA_VMID15_BASE_IDX 0 #define regGDS_GWS_RESET0 0 x1344#define regGDS_GWS_RESET0_BASE_IDX 0 #define regGDS_GWS_RESET1 0 x1345#define regGDS_GWS_RESET1_BASE_IDX 0 #define regGDS_GWS_RESOURCE_RESET 0 x1346#define regGDS_GWS_RESOURCE_RESET_BASE_IDX 0 #define regGDS_COMPUTE_MAX_WAVE_ID 0 x1348#define regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0 #define regGDS_OA_RESET_MASK 0 x1349#define regGDS_OA_RESET_MASK_BASE_IDX 0 #define regGDS_OA_RESET 0 x134a#define regGDS_OA_RESET_BASE_IDX 0 #define regGDS_ENHANCE 0 x134b#define regGDS_ENHANCE_BASE_IDX 0 #define regGDS_OA_CGPG_RESTORE 0 x134c#define regGDS_OA_CGPG_RESTORE_BASE_IDX 0 #define regGDS_CS_CTXSW_STATUS 0 x134d#define regGDS_CS_CTXSW_STATUS_BASE_IDX 0 #define regGDS_CS_CTXSW_CNT0 0 x134e#define regGDS_CS_CTXSW_CNT0_BASE_IDX 0 #define regGDS_CS_CTXSW_CNT1 0 x134f#define regGDS_CS_CTXSW_CNT1_BASE_IDX 0 #define regGDS_CS_CTXSW_CNT2 0 x1350#define regGDS_CS_CTXSW_CNT2_BASE_IDX 0 #define regGDS_CS_CTXSW_CNT3 0 x1351#define regGDS_CS_CTXSW_CNT3_BASE_IDX 0 #define regGDS_GFX_CTXSW_STATUS 0 x1352#define regGDS_GFX_CTXSW_STATUS_BASE_IDX 0 #define regGDS_VS_CTXSW_CNT0 0 x1353#define regGDS_VS_CTXSW_CNT0_BASE_IDX 0 #define regGDS_VS_CTXSW_CNT1 0 x1354#define regGDS_VS_CTXSW_CNT1_BASE_IDX 0 #define regGDS_VS_CTXSW_CNT2 0 x1355#define regGDS_VS_CTXSW_CNT2_BASE_IDX 0 #define regGDS_VS_CTXSW_CNT3 0 x1356#define regGDS_VS_CTXSW_CNT3_BASE_IDX 0 #define regGDS_PS0_CTXSW_CNT0 0 x1357#define regGDS_PS0_CTXSW_CNT0_BASE_IDX 0 #define regGDS_PS0_CTXSW_CNT1 0 x1358#define regGDS_PS0_CTXSW_CNT1_BASE_IDX 0 #define regGDS_PS0_CTXSW_CNT2 0 x1359#define regGDS_PS0_CTXSW_CNT2_BASE_IDX 0 #define regGDS_PS0_CTXSW_CNT3 0 x135a#define regGDS_PS0_CTXSW_CNT3_BASE_IDX 0 #define regGDS_PS1_CTXSW_CNT0 0 x135b#define regGDS_PS1_CTXSW_CNT0_BASE_IDX 0 #define regGDS_PS1_CTXSW_CNT1 0 x135c#define regGDS_PS1_CTXSW_CNT1_BASE_IDX 0 #define regGDS_PS1_CTXSW_CNT2 0 x135d#define regGDS_PS1_CTXSW_CNT2_BASE_IDX 0 #define regGDS_PS1_CTXSW_CNT3 0 x135e#define regGDS_PS1_CTXSW_CNT3_BASE_IDX 0 #define regGDS_PS2_CTXSW_CNT0 0 x135f#define regGDS_PS2_CTXSW_CNT0_BASE_IDX 0 #define regGDS_PS2_CTXSW_CNT1 0 x1360#define regGDS_PS2_CTXSW_CNT1_BASE_IDX 0 #define regGDS_PS2_CTXSW_CNT2 0 x1361#define regGDS_PS2_CTXSW_CNT2_BASE_IDX 0 #define regGDS_PS2_CTXSW_CNT3 0 x1362#define regGDS_PS2_CTXSW_CNT3_BASE_IDX 0 #define regGDS_PS3_CTXSW_CNT0 0 x1363#define regGDS_PS3_CTXSW_CNT0_BASE_IDX 0 #define regGDS_PS3_CTXSW_CNT1 0 x1364#define regGDS_PS3_CTXSW_CNT1_BASE_IDX 0 #define regGDS_PS3_CTXSW_CNT2 0 x1365#define regGDS_PS3_CTXSW_CNT2_BASE_IDX 0 #define regGDS_PS3_CTXSW_CNT3 0 x1366#define regGDS_PS3_CTXSW_CNT3_BASE_IDX 0 #define regGDS_PS4_CTXSW_CNT0 0 x1367#define regGDS_PS4_CTXSW_CNT0_BASE_IDX 0 #define regGDS_PS4_CTXSW_CNT1 0 x1368#define regGDS_PS4_CTXSW_CNT1_BASE_IDX 0 #define regGDS_PS4_CTXSW_CNT2 0 x1369#define regGDS_PS4_CTXSW_CNT2_BASE_IDX 0 #define regGDS_PS4_CTXSW_CNT3 0 x136a#define regGDS_PS4_CTXSW_CNT3_BASE_IDX 0 #define regGDS_PS5_CTXSW_CNT0 0 x136b#define regGDS_PS5_CTXSW_CNT0_BASE_IDX 0 #define regGDS_PS5_CTXSW_CNT1 0 x136c#define regGDS_PS5_CTXSW_CNT1_BASE_IDX 0 #define regGDS_PS5_CTXSW_CNT2 0 x136d#define regGDS_PS5_CTXSW_CNT2_BASE_IDX 0 #define regGDS_PS5_CTXSW_CNT3 0 x136e#define regGDS_PS5_CTXSW_CNT3_BASE_IDX 0 #define regGDS_PS6_CTXSW_CNT0 0 x136f#define regGDS_PS6_CTXSW_CNT0_BASE_IDX 0 #define regGDS_PS6_CTXSW_CNT1 0 x1370#define regGDS_PS6_CTXSW_CNT1_BASE_IDX 0 #define regGDS_PS6_CTXSW_CNT2 0 x1371#define regGDS_PS6_CTXSW_CNT2_BASE_IDX 0 #define regGDS_PS6_CTXSW_CNT3 0 x1372#define regGDS_PS6_CTXSW_CNT3_BASE_IDX 0 #define regGDS_PS7_CTXSW_CNT0 0 x1373#define regGDS_PS7_CTXSW_CNT0_BASE_IDX 0 #define regGDS_PS7_CTXSW_CNT1 0 x1374#define regGDS_PS7_CTXSW_CNT1_BASE_IDX 0 #define regGDS_PS7_CTXSW_CNT2 0 x1375#define regGDS_PS7_CTXSW_CNT2_BASE_IDX 0 #define regGDS_PS7_CTXSW_CNT3 0 x1376#define regGDS_PS7_CTXSW_CNT3_BASE_IDX 0 #define regGDS_GS_CTXSW_CNT0 0 x1377#define regGDS_GS_CTXSW_CNT0_BASE_IDX 0 #define regGDS_GS_CTXSW_CNT1 0 x1378#define regGDS_GS_CTXSW_CNT1_BASE_IDX 0 #define regGDS_GS_CTXSW_CNT2 0 x1379#define regGDS_GS_CTXSW_CNT2_BASE_IDX 0 #define regGDS_GS_CTXSW_CNT3 0 x137a#define regGDS_GS_CTXSW_CNT3_BASE_IDX 0 // addressBlock: gc_gfxdec0 // base address: 0x28000 #define regDB_RENDER_CONTROL 0 x0000#define regDB_RENDER_CONTROL_BASE_IDX 1 #define regDB_COUNT_CONTROL 0 x0001#define regDB_COUNT_CONTROL_BASE_IDX 1 #define regDB_DEPTH_VIEW 0 x0002#define regDB_DEPTH_VIEW_BASE_IDX 1 #define regDB_RENDER_OVERRIDE 0 x0003#define regDB_RENDER_OVERRIDE_BASE_IDX 1 #define regDB_RENDER_OVERRIDE2 0 x0004#define regDB_RENDER_OVERRIDE2_BASE_IDX 1 #define regDB_HTILE_DATA_BASE 0 x0005#define regDB_HTILE_DATA_BASE_BASE_IDX 1 #define regDB_HTILE_DATA_BASE_HI 0 x0006#define regDB_HTILE_DATA_BASE_HI_BASE_IDX 1 #define regDB_DEPTH_SIZE 0 x0007#define regDB_DEPTH_SIZE_BASE_IDX 1 #define regDB_DEPTH_BOUNDS_MIN 0 x0008#define regDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 #define regDB_DEPTH_BOUNDS_MAX 0 x0009#define regDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 #define regDB_STENCIL_CLEAR 0 x000a#define regDB_STENCIL_CLEAR_BASE_IDX 1 #define regDB_DEPTH_CLEAR 0 x000b#define regDB_DEPTH_CLEAR_BASE_IDX 1 #define regPA_SC_SCREEN_SCISSOR_TL 0 x000c#define regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 #define regPA_SC_SCREEN_SCISSOR_BR 0 x000d#define regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 #define regDB_Z_INFO 0 x000e#define regDB_Z_INFO_BASE_IDX 1 #define regDB_STENCIL_INFO 0 x000f#define regDB_STENCIL_INFO_BASE_IDX 1 #define regDB_Z_READ_BASE 0 x0010#define regDB_Z_READ_BASE_BASE_IDX 1 #define regDB_Z_READ_BASE_HI 0 x0011#define regDB_Z_READ_BASE_HI_BASE_IDX 1 #define regDB_STENCIL_READ_BASE 0 x0012#define regDB_STENCIL_READ_BASE_BASE_IDX 1 #define regDB_STENCIL_READ_BASE_HI 0 x0013#define regDB_STENCIL_READ_BASE_HI_BASE_IDX 1 #define regDB_Z_WRITE_BASE 0 x0014#define regDB_Z_WRITE_BASE_BASE_IDX 1 #define regDB_Z_WRITE_BASE_HI 0 x0015#define regDB_Z_WRITE_BASE_HI_BASE_IDX 1 #define regDB_STENCIL_WRITE_BASE 0 x0016#define regDB_STENCIL_WRITE_BASE_BASE_IDX 1 #define regDB_STENCIL_WRITE_BASE_HI 0 x0017#define regDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 #define regDB_DFSM_CONTROL 0 x0018#define regDB_DFSM_CONTROL_BASE_IDX 1 #define regDB_Z_INFO2 0 x001a#define regDB_Z_INFO2_BASE_IDX 1 #define regDB_STENCIL_INFO2 0 x001b#define regDB_STENCIL_INFO2_BASE_IDX 1 #define regCOHER_DEST_BASE_HI_0 0 x007a#define regCOHER_DEST_BASE_HI_0_BASE_IDX 1 #define regCOHER_DEST_BASE_HI_1 0 x007b#define regCOHER_DEST_BASE_HI_1_BASE_IDX 1 #define regCOHER_DEST_BASE_HI_2 0 x007c#define regCOHER_DEST_BASE_HI_2_BASE_IDX 1 #define regCOHER_DEST_BASE_HI_3 0 x007d#define regCOHER_DEST_BASE_HI_3_BASE_IDX 1 #define regCOHER_DEST_BASE_2 0 x007e#define regCOHER_DEST_BASE_2_BASE_IDX 1 #define regCOHER_DEST_BASE_3 0 x007f#define regCOHER_DEST_BASE_3_BASE_IDX 1 #define regPA_SC_WINDOW_OFFSET 0 x0080#define regPA_SC_WINDOW_OFFSET_BASE_IDX 1 #define regPA_SC_WINDOW_SCISSOR_TL 0 x0081#define regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 #define regPA_SC_WINDOW_SCISSOR_BR 0 x0082#define regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 #define regPA_SC_CLIPRECT_RULE 0 x0083#define regPA_SC_CLIPRECT_RULE_BASE_IDX 1 #define regPA_SC_CLIPRECT_0_TL 0 x0084#define regPA_SC_CLIPRECT_0_TL_BASE_IDX 1 #define regPA_SC_CLIPRECT_0_BR 0 x0085#define regPA_SC_CLIPRECT_0_BR_BASE_IDX 1 #define regPA_SC_CLIPRECT_1_TL 0 x0086#define regPA_SC_CLIPRECT_1_TL_BASE_IDX 1 #define regPA_SC_CLIPRECT_1_BR 0 x0087#define regPA_SC_CLIPRECT_1_BR_BASE_IDX 1 #define regPA_SC_CLIPRECT_2_TL 0 x0088#define regPA_SC_CLIPRECT_2_TL_BASE_IDX 1 #define regPA_SC_CLIPRECT_2_BR 0 x0089#define regPA_SC_CLIPRECT_2_BR_BASE_IDX 1 #define regPA_SC_CLIPRECT_3_TL 0 x008a#define regPA_SC_CLIPRECT_3_TL_BASE_IDX 1 #define regPA_SC_CLIPRECT_3_BR 0 x008b#define regPA_SC_CLIPRECT_3_BR_BASE_IDX 1 #define regPA_SC_EDGERULE 0 x008c#define regPA_SC_EDGERULE_BASE_IDX 1 #define regPA_SU_HARDWARE_SCREEN_OFFSET 0 x008d#define regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 #define regCB_TARGET_MASK 0 x008e#define regCB_TARGET_MASK_BASE_IDX 1 #define regCB_SHADER_MASK 0 x008f#define regCB_SHADER_MASK_BASE_IDX 1 #define regPA_SC_GENERIC_SCISSOR_TL 0 x0090#define regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 #define regPA_SC_GENERIC_SCISSOR_BR 0 x0091#define regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 #define regCOHER_DEST_BASE_0 0 x0092#define regCOHER_DEST_BASE_0_BASE_IDX 1 #define regCOHER_DEST_BASE_1 0 x0093#define regCOHER_DEST_BASE_1_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_0_TL 0 x0094#define regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_0_BR 0 x0095#define regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_1_TL 0 x0096#define regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_1_BR 0 x0097#define regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_2_TL 0 x0098#define regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_2_BR 0 x0099#define regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_3_TL 0 x009a#define regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_3_BR 0 x009b#define regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_4_TL 0 x009c#define regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_4_BR 0 x009d#define regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_5_TL 0 x009e#define regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_5_BR 0 x009f#define regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_6_TL 0 x00a0#define regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_6_BR 0 x00a1#define regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_7_TL 0 x00a2#define regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_7_BR 0 x00a3#define regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_8_TL 0 x00a4#define regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_8_BR 0 x00a5#define regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_9_TL 0 x00a6#define regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_9_BR 0 x00a7#define regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_10_TL 0 x00a8#define regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_10_BR 0 x00a9#define regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_11_TL 0 x00aa#define regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_11_BR 0 x00ab#define regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_12_TL 0 x00ac#define regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_12_BR 0 x00ad#define regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_13_TL 0 x00ae#define regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_13_BR 0 x00af#define regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_14_TL 0 x00b0#define regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_14_BR 0 x00b1#define regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_15_TL 0 x00b2#define regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 #define regPA_SC_VPORT_SCISSOR_15_BR 0 x00b3#define regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_0 0 x00b4#define regPA_SC_VPORT_ZMIN_0_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_0 0 x00b5#define regPA_SC_VPORT_ZMAX_0_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_1 0 x00b6#define regPA_SC_VPORT_ZMIN_1_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_1 0 x00b7#define regPA_SC_VPORT_ZMAX_1_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_2 0 x00b8#define regPA_SC_VPORT_ZMIN_2_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_2 0 x00b9#define regPA_SC_VPORT_ZMAX_2_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_3 0 x00ba#define regPA_SC_VPORT_ZMIN_3_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_3 0 x00bb#define regPA_SC_VPORT_ZMAX_3_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_4 0 x00bc#define regPA_SC_VPORT_ZMIN_4_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_4 0 x00bd#define regPA_SC_VPORT_ZMAX_4_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_5 0 x00be#define regPA_SC_VPORT_ZMIN_5_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_5 0 x00bf#define regPA_SC_VPORT_ZMAX_5_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_6 0 x00c0#define regPA_SC_VPORT_ZMIN_6_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_6 0 x00c1#define regPA_SC_VPORT_ZMAX_6_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_7 0 x00c2#define regPA_SC_VPORT_ZMIN_7_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_7 0 x00c3#define regPA_SC_VPORT_ZMAX_7_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_8 0 x00c4#define regPA_SC_VPORT_ZMIN_8_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_8 0 x00c5#define regPA_SC_VPORT_ZMAX_8_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_9 0 x00c6#define regPA_SC_VPORT_ZMIN_9_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_9 0 x00c7#define regPA_SC_VPORT_ZMAX_9_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_10 0 x00c8#define regPA_SC_VPORT_ZMIN_10_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_10 0 x00c9#define regPA_SC_VPORT_ZMAX_10_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_11 0 x00ca#define regPA_SC_VPORT_ZMIN_11_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_11 0 x00cb#define regPA_SC_VPORT_ZMAX_11_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_12 0 x00cc#define regPA_SC_VPORT_ZMIN_12_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_12 0 x00cd#define regPA_SC_VPORT_ZMAX_12_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_13 0 x00ce#define regPA_SC_VPORT_ZMIN_13_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_13 0 x00cf#define regPA_SC_VPORT_ZMAX_13_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_14 0 x00d0#define regPA_SC_VPORT_ZMIN_14_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_14 0 x00d1#define regPA_SC_VPORT_ZMAX_14_BASE_IDX 1 #define regPA_SC_VPORT_ZMIN_15 0 x00d2#define regPA_SC_VPORT_ZMIN_15_BASE_IDX 1 #define regPA_SC_VPORT_ZMAX_15 0 x00d3#define regPA_SC_VPORT_ZMAX_15_BASE_IDX 1 #define regPA_SC_RASTER_CONFIG 0 x00d4#define regPA_SC_RASTER_CONFIG_BASE_IDX 1 #define regPA_SC_RASTER_CONFIG_1 0 x00d5#define regPA_SC_RASTER_CONFIG_1_BASE_IDX 1 #define regPA_SC_SCREEN_EXTENT_CONTROL 0 x00d6#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 #define regPA_SC_TILE_STEERING_OVERRIDE 0 x00d7#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 #define regCP_PERFMON_CNTX_CNTL 0 x00d8#define regCP_PERFMON_CNTX_CNTL_BASE_IDX 1 #define regCP_PIPEID 0 x00d9#define regCP_PIPEID_BASE_IDX 1 #define regCP_RINGID 0 x00d9#define regCP_RINGID_BASE_IDX 1 #define regCP_VMID 0 x00da#define regCP_VMID_BASE_IDX 1 #define regPA_SC_RIGHT_VERT_GRID 0 x00e8#define regPA_SC_RIGHT_VERT_GRID_BASE_IDX 1 #define regPA_SC_LEFT_VERT_GRID 0 x00e9#define regPA_SC_LEFT_VERT_GRID_BASE_IDX 1 #define regPA_SC_HORIZ_GRID 0 x00ea#define regPA_SC_HORIZ_GRID_BASE_IDX 1 #define regVGT_MULTI_PRIM_IB_RESET_INDX 0 x0103#define regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 #define regCB_BLEND_RED 0 x0105#define regCB_BLEND_RED_BASE_IDX 1 #define regCB_BLEND_GREEN 0 x0106#define regCB_BLEND_GREEN_BASE_IDX 1 #define regCB_BLEND_BLUE 0 x0107#define regCB_BLEND_BLUE_BASE_IDX 1 #define regCB_BLEND_ALPHA 0 x0108#define regCB_BLEND_ALPHA_BASE_IDX 1 #define regCB_DCC_CONTROL 0 x0109#define regCB_DCC_CONTROL_BASE_IDX 1 #define regDB_STENCIL_CONTROL 0 x010b#define regDB_STENCIL_CONTROL_BASE_IDX 1 #define regDB_STENCILREFMASK 0 x010c#define regDB_STENCILREFMASK_BASE_IDX 1 #define regDB_STENCILREFMASK_BF 0 x010d#define regDB_STENCILREFMASK_BF_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE 0 x010f#define regPA_CL_VPORT_XSCALE_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET 0 x0110#define regPA_CL_VPORT_XOFFSET_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE 0 x0111#define regPA_CL_VPORT_YSCALE_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET 0 x0112#define regPA_CL_VPORT_YOFFSET_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE 0 x0113#define regPA_CL_VPORT_ZSCALE_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET 0 x0114#define regPA_CL_VPORT_ZOFFSET_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE_1 0 x0115#define regPA_CL_VPORT_XSCALE_1_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET_1 0 x0116#define regPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE_1 0 x0117#define regPA_CL_VPORT_YSCALE_1_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET_1 0 x0118#define regPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE_1 0 x0119#define regPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET_1 0 x011a#define regPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE_2 0 x011b#define regPA_CL_VPORT_XSCALE_2_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET_2 0 x011c#define regPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE_2 0 x011d#define regPA_CL_VPORT_YSCALE_2_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET_2 0 x011e#define regPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE_2 0 x011f#define regPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET_2 0 x0120#define regPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE_3 0 x0121#define regPA_CL_VPORT_XSCALE_3_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET_3 0 x0122#define regPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE_3 0 x0123#define regPA_CL_VPORT_YSCALE_3_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET_3 0 x0124#define regPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE_3 0 x0125#define regPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET_3 0 x0126#define regPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE_4 0 x0127#define regPA_CL_VPORT_XSCALE_4_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET_4 0 x0128#define regPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE_4 0 x0129#define regPA_CL_VPORT_YSCALE_4_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET_4 0 x012a#define regPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE_4 0 x012b#define regPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET_4 0 x012c#define regPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE_5 0 x012d#define regPA_CL_VPORT_XSCALE_5_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET_5 0 x012e#define regPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE_5 0 x012f#define regPA_CL_VPORT_YSCALE_5_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET_5 0 x0130#define regPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE_5 0 x0131#define regPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET_5 0 x0132#define regPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE_6 0 x0133#define regPA_CL_VPORT_XSCALE_6_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET_6 0 x0134#define regPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE_6 0 x0135#define regPA_CL_VPORT_YSCALE_6_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET_6 0 x0136#define regPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE_6 0 x0137#define regPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET_6 0 x0138#define regPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE_7 0 x0139#define regPA_CL_VPORT_XSCALE_7_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET_7 0 x013a#define regPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE_7 0 x013b#define regPA_CL_VPORT_YSCALE_7_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET_7 0 x013c#define regPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE_7 0 x013d#define regPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET_7 0 x013e#define regPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE_8 0 x013f#define regPA_CL_VPORT_XSCALE_8_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET_8 0 x0140#define regPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE_8 0 x0141#define regPA_CL_VPORT_YSCALE_8_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET_8 0 x0142#define regPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE_8 0 x0143#define regPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET_8 0 x0144#define regPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE_9 0 x0145#define regPA_CL_VPORT_XSCALE_9_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET_9 0 x0146#define regPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE_9 0 x0147#define regPA_CL_VPORT_YSCALE_9_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET_9 0 x0148#define regPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE_9 0 x0149#define regPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET_9 0 x014a#define regPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE_10 0 x014b#define regPA_CL_VPORT_XSCALE_10_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET_10 0 x014c#define regPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE_10 0 x014d#define regPA_CL_VPORT_YSCALE_10_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET_10 0 x014e#define regPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE_10 0 x014f#define regPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET_10 0 x0150#define regPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE_11 0 x0151#define regPA_CL_VPORT_XSCALE_11_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET_11 0 x0152#define regPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE_11 0 x0153#define regPA_CL_VPORT_YSCALE_11_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET_11 0 x0154#define regPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE_11 0 x0155#define regPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET_11 0 x0156#define regPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE_12 0 x0157#define regPA_CL_VPORT_XSCALE_12_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET_12 0 x0158#define regPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE_12 0 x0159#define regPA_CL_VPORT_YSCALE_12_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET_12 0 x015a#define regPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE_12 0 x015b#define regPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET_12 0 x015c#define regPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE_13 0 x015d#define regPA_CL_VPORT_XSCALE_13_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET_13 0 x015e#define regPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE_13 0 x015f#define regPA_CL_VPORT_YSCALE_13_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET_13 0 x0160#define regPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE_13 0 x0161#define regPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET_13 0 x0162#define regPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE_14 0 x0163#define regPA_CL_VPORT_XSCALE_14_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET_14 0 x0164#define regPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE_14 0 x0165#define regPA_CL_VPORT_YSCALE_14_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET_14 0 x0166#define regPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE_14 0 x0167#define regPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET_14 0 x0168#define regPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 #define regPA_CL_VPORT_XSCALE_15 0 x0169#define regPA_CL_VPORT_XSCALE_15_BASE_IDX 1 #define regPA_CL_VPORT_XOFFSET_15 0 x016a#define regPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 #define regPA_CL_VPORT_YSCALE_15 0 x016b#define regPA_CL_VPORT_YSCALE_15_BASE_IDX 1 #define regPA_CL_VPORT_YOFFSET_15 0 x016c#define regPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 #define regPA_CL_VPORT_ZSCALE_15 0 x016d#define regPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 #define regPA_CL_VPORT_ZOFFSET_15 0 x016e#define regPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 #define regPA_CL_UCP_0_X 0 x016f#define regPA_CL_UCP_0_X_BASE_IDX 1 #define regPA_CL_UCP_0_Y 0 x0170#define regPA_CL_UCP_0_Y_BASE_IDX 1 #define regPA_CL_UCP_0_Z 0 x0171#define regPA_CL_UCP_0_Z_BASE_IDX 1 #define regPA_CL_UCP_0_W 0 x0172#define regPA_CL_UCP_0_W_BASE_IDX 1 #define regPA_CL_UCP_1_X 0 x0173#define regPA_CL_UCP_1_X_BASE_IDX 1 #define regPA_CL_UCP_1_Y 0 x0174#define regPA_CL_UCP_1_Y_BASE_IDX 1 #define regPA_CL_UCP_1_Z 0 x0175#define regPA_CL_UCP_1_Z_BASE_IDX 1 #define regPA_CL_UCP_1_W 0 x0176#define regPA_CL_UCP_1_W_BASE_IDX 1 #define regPA_CL_UCP_2_X 0 x0177#define regPA_CL_UCP_2_X_BASE_IDX 1 #define regPA_CL_UCP_2_Y 0 x0178#define regPA_CL_UCP_2_Y_BASE_IDX 1 #define regPA_CL_UCP_2_Z 0 x0179#define regPA_CL_UCP_2_Z_BASE_IDX 1 #define regPA_CL_UCP_2_W 0 x017a#define regPA_CL_UCP_2_W_BASE_IDX 1 #define regPA_CL_UCP_3_X 0 x017b#define regPA_CL_UCP_3_X_BASE_IDX 1 #define regPA_CL_UCP_3_Y 0 x017c#define regPA_CL_UCP_3_Y_BASE_IDX 1 #define regPA_CL_UCP_3_Z 0 x017d#define regPA_CL_UCP_3_Z_BASE_IDX 1 #define regPA_CL_UCP_3_W 0 x017e#define regPA_CL_UCP_3_W_BASE_IDX 1 #define regPA_CL_UCP_4_X 0 x017f#define regPA_CL_UCP_4_X_BASE_IDX 1 #define regPA_CL_UCP_4_Y 0 x0180#define regPA_CL_UCP_4_Y_BASE_IDX 1 #define regPA_CL_UCP_4_Z 0 x0181#define regPA_CL_UCP_4_Z_BASE_IDX 1 #define regPA_CL_UCP_4_W 0 x0182#define regPA_CL_UCP_4_W_BASE_IDX 1 #define regPA_CL_UCP_5_X 0 x0183#define regPA_CL_UCP_5_X_BASE_IDX 1 #define regPA_CL_UCP_5_Y 0 x0184#define regPA_CL_UCP_5_Y_BASE_IDX 1 #define regPA_CL_UCP_5_Z 0 x0185#define regPA_CL_UCP_5_Z_BASE_IDX 1 #define regPA_CL_UCP_5_W 0 x0186#define regPA_CL_UCP_5_W_BASE_IDX 1 #define regPA_CL_PROG_NEAR_CLIP_Z 0 x0187#define regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_0 0 x0191#define regSPI_PS_INPUT_CNTL_0_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_1 0 x0192#define regSPI_PS_INPUT_CNTL_1_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_2 0 x0193#define regSPI_PS_INPUT_CNTL_2_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_3 0 x0194#define regSPI_PS_INPUT_CNTL_3_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_4 0 x0195#define regSPI_PS_INPUT_CNTL_4_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_5 0 x0196#define regSPI_PS_INPUT_CNTL_5_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_6 0 x0197#define regSPI_PS_INPUT_CNTL_6_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_7 0 x0198#define regSPI_PS_INPUT_CNTL_7_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_8 0 x0199#define regSPI_PS_INPUT_CNTL_8_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_9 0 x019a#define regSPI_PS_INPUT_CNTL_9_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_10 0 x019b#define regSPI_PS_INPUT_CNTL_10_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_11 0 x019c#define regSPI_PS_INPUT_CNTL_11_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_12 0 x019d#define regSPI_PS_INPUT_CNTL_12_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_13 0 x019e#define regSPI_PS_INPUT_CNTL_13_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_14 0 x019f#define regSPI_PS_INPUT_CNTL_14_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_15 0 x01a0#define regSPI_PS_INPUT_CNTL_15_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_16 0 x01a1#define regSPI_PS_INPUT_CNTL_16_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_17 0 x01a2#define regSPI_PS_INPUT_CNTL_17_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_18 0 x01a3#define regSPI_PS_INPUT_CNTL_18_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_19 0 x01a4#define regSPI_PS_INPUT_CNTL_19_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_20 0 x01a5#define regSPI_PS_INPUT_CNTL_20_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_21 0 x01a6#define regSPI_PS_INPUT_CNTL_21_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_22 0 x01a7#define regSPI_PS_INPUT_CNTL_22_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_23 0 x01a8#define regSPI_PS_INPUT_CNTL_23_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_24 0 x01a9#define regSPI_PS_INPUT_CNTL_24_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_25 0 x01aa#define regSPI_PS_INPUT_CNTL_25_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_26 0 x01ab#define regSPI_PS_INPUT_CNTL_26_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_27 0 x01ac#define regSPI_PS_INPUT_CNTL_27_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_28 0 x01ad#define regSPI_PS_INPUT_CNTL_28_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_29 0 x01ae#define regSPI_PS_INPUT_CNTL_29_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_30 0 x01af#define regSPI_PS_INPUT_CNTL_30_BASE_IDX 1 #define regSPI_PS_INPUT_CNTL_31 0 x01b0#define regSPI_PS_INPUT_CNTL_31_BASE_IDX 1 #define regSPI_VS_OUT_CONFIG 0 x01b1#define regSPI_VS_OUT_CONFIG_BASE_IDX 1 #define regSPI_PS_INPUT_ENA 0 x01b3#define regSPI_PS_INPUT_ENA_BASE_IDX 1 #define regSPI_PS_INPUT_ADDR 0 x01b4#define regSPI_PS_INPUT_ADDR_BASE_IDX 1 #define regSPI_INTERP_CONTROL_0 0 x01b5#define regSPI_INTERP_CONTROL_0_BASE_IDX 1 #define regSPI_PS_IN_CONTROL 0 x01b6#define regSPI_PS_IN_CONTROL_BASE_IDX 1 #define regSPI_BARYC_CNTL 0 x01b8#define regSPI_BARYC_CNTL_BASE_IDX 1 #define regSPI_TMPRING_SIZE 0 x01ba#define regSPI_TMPRING_SIZE_BASE_IDX 1 #define regSPI_SHADER_POS_FORMAT 0 x01c3#define regSPI_SHADER_POS_FORMAT_BASE_IDX 1 #define regSPI_SHADER_Z_FORMAT 0 x01c4#define regSPI_SHADER_Z_FORMAT_BASE_IDX 1 #define regSPI_SHADER_COL_FORMAT 0 x01c5#define regSPI_SHADER_COL_FORMAT_BASE_IDX 1 #define regSX_PS_DOWNCONVERT 0 x01d5#define regSX_PS_DOWNCONVERT_BASE_IDX 1 #define regSX_BLEND_OPT_EPSILON 0 x01d6#define regSX_BLEND_OPT_EPSILON_BASE_IDX 1 #define regSX_BLEND_OPT_CONTROL 0 x01d7#define regSX_BLEND_OPT_CONTROL_BASE_IDX 1 #define regSX_MRT0_BLEND_OPT 0 x01d8#define regSX_MRT0_BLEND_OPT_BASE_IDX 1 #define regSX_MRT1_BLEND_OPT 0 x01d9#define regSX_MRT1_BLEND_OPT_BASE_IDX 1 #define regSX_MRT2_BLEND_OPT 0 x01da#define regSX_MRT2_BLEND_OPT_BASE_IDX 1 #define regSX_MRT3_BLEND_OPT 0 x01db#define regSX_MRT3_BLEND_OPT_BASE_IDX 1 #define regSX_MRT4_BLEND_OPT 0 x01dc#define regSX_MRT4_BLEND_OPT_BASE_IDX 1 #define regSX_MRT5_BLEND_OPT 0 x01dd#define regSX_MRT5_BLEND_OPT_BASE_IDX 1 #define regSX_MRT6_BLEND_OPT 0 x01de#define regSX_MRT6_BLEND_OPT_BASE_IDX 1 #define regSX_MRT7_BLEND_OPT 0 x01df#define regSX_MRT7_BLEND_OPT_BASE_IDX 1 #define regCB_BLEND0_CONTROL 0 x01e0#define regCB_BLEND0_CONTROL_BASE_IDX 1 #define regCB_BLEND1_CONTROL 0 x01e1#define regCB_BLEND1_CONTROL_BASE_IDX 1 #define regCB_BLEND2_CONTROL 0 x01e2#define regCB_BLEND2_CONTROL_BASE_IDX 1 #define regCB_BLEND3_CONTROL 0 x01e3#define regCB_BLEND3_CONTROL_BASE_IDX 1 #define regCB_BLEND4_CONTROL 0 x01e4#define regCB_BLEND4_CONTROL_BASE_IDX 1 #define regCB_BLEND5_CONTROL 0 x01e5#define regCB_BLEND5_CONTROL_BASE_IDX 1 #define regCB_BLEND6_CONTROL 0 x01e6#define regCB_BLEND6_CONTROL_BASE_IDX 1 #define regCB_BLEND7_CONTROL 0 x01e7#define regCB_BLEND7_CONTROL_BASE_IDX 1 #define regCB_MRT0_EPITCH 0 x01e8#define regCB_MRT0_EPITCH_BASE_IDX 1 #define regCB_MRT1_EPITCH 0 x01e9#define regCB_MRT1_EPITCH_BASE_IDX 1 #define regCB_MRT2_EPITCH 0 x01ea#define regCB_MRT2_EPITCH_BASE_IDX 1 #define regCB_MRT3_EPITCH 0 x01eb#define regCB_MRT3_EPITCH_BASE_IDX 1 #define regCB_MRT4_EPITCH 0 x01ec#define regCB_MRT4_EPITCH_BASE_IDX 1 #define regCB_MRT5_EPITCH 0 x01ed#define regCB_MRT5_EPITCH_BASE_IDX 1 #define regCB_MRT6_EPITCH 0 x01ee#define regCB_MRT6_EPITCH_BASE_IDX 1 #define regCB_MRT7_EPITCH 0 x01ef#define regCB_MRT7_EPITCH_BASE_IDX 1 #define regCS_COPY_STATE 0 x01f3#define regCS_COPY_STATE_BASE_IDX 1 #define regGFX_COPY_STATE 0 x01f4#define regGFX_COPY_STATE_BASE_IDX 1 #define regPA_CL_POINT_X_RAD 0 x01f5#define regPA_CL_POINT_X_RAD_BASE_IDX 1 #define regPA_CL_POINT_Y_RAD 0 x01f6#define regPA_CL_POINT_Y_RAD_BASE_IDX 1 #define regPA_CL_POINT_SIZE 0 x01f7#define regPA_CL_POINT_SIZE_BASE_IDX 1 #define regPA_CL_POINT_CULL_RAD 0 x01f8#define regPA_CL_POINT_CULL_RAD_BASE_IDX 1 #define regVGT_DMA_BASE_HI 0 x01f9#define regVGT_DMA_BASE_HI_BASE_IDX 1 #define regVGT_DMA_BASE 0 x01fa#define regVGT_DMA_BASE_BASE_IDX 1 #define regVGT_DRAW_INITIATOR 0 x01fc#define regVGT_DRAW_INITIATOR_BASE_IDX 1 #define regVGT_IMMED_DATA 0 x01fd#define regVGT_IMMED_DATA_BASE_IDX 1 #define regVGT_EVENT_ADDRESS_REG 0 x01fe#define regVGT_EVENT_ADDRESS_REG_BASE_IDX 1 #define regDB_DEPTH_CONTROL 0 x0200#define regDB_DEPTH_CONTROL_BASE_IDX 1 #define regDB_EQAA 0 x0201#define regDB_EQAA_BASE_IDX 1 #define regCB_COLOR_CONTROL 0 x0202#define regCB_COLOR_CONTROL_BASE_IDX 1 #define regDB_SHADER_CONTROL 0 x0203#define regDB_SHADER_CONTROL_BASE_IDX 1 #define regPA_CL_CLIP_CNTL 0 x0204#define regPA_CL_CLIP_CNTL_BASE_IDX 1 #define regPA_SU_SC_MODE_CNTL 0 x0205#define regPA_SU_SC_MODE_CNTL_BASE_IDX 1 #define regPA_CL_VTE_CNTL 0 x0206#define regPA_CL_VTE_CNTL_BASE_IDX 1 #define regPA_CL_VS_OUT_CNTL 0 x0207#define regPA_CL_VS_OUT_CNTL_BASE_IDX 1 #define regPA_CL_NANINF_CNTL 0 x0208#define regPA_CL_NANINF_CNTL_BASE_IDX 1 #define regPA_SU_LINE_STIPPLE_CNTL 0 x0209#define regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 #define regPA_SU_LINE_STIPPLE_SCALE 0 x020a#define regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 #define regPA_SU_PRIM_FILTER_CNTL 0 x020b#define regPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 #define regPA_SU_SMALL_PRIM_FILTER_CNTL 0 x020c#define regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 #define regPA_CL_OBJPRIM_ID_CNTL 0 x020d#define regPA_CL_OBJPRIM_ID_CNTL_BASE_IDX 1 #define regPA_CL_NGG_CNTL 0 x020e#define regPA_CL_NGG_CNTL_BASE_IDX 1 #define regPA_SU_OVER_RASTERIZATION_CNTL 0 x020f#define regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 #define regPA_STEREO_CNTL 0 x0210#define regPA_STEREO_CNTL_BASE_IDX 1 #define regPA_SU_POINT_SIZE 0 x0280#define regPA_SU_POINT_SIZE_BASE_IDX 1 #define regPA_SU_POINT_MINMAX 0 x0281#define regPA_SU_POINT_MINMAX_BASE_IDX 1 #define regPA_SU_LINE_CNTL 0 x0282#define regPA_SU_LINE_CNTL_BASE_IDX 1 #define regPA_SC_LINE_STIPPLE 0 x0283#define regPA_SC_LINE_STIPPLE_BASE_IDX 1 #define regVGT_OUTPUT_PATH_CNTL 0 x0284#define regVGT_OUTPUT_PATH_CNTL_BASE_IDX 1 #define regVGT_HOS_CNTL 0 x0285#define regVGT_HOS_CNTL_BASE_IDX 1 #define regVGT_HOS_MAX_TESS_LEVEL 0 x0286#define regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 #define regVGT_HOS_MIN_TESS_LEVEL 0 x0287#define regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 #define regVGT_HOS_REUSE_DEPTH 0 x0288#define regVGT_HOS_REUSE_DEPTH_BASE_IDX 1 #define regVGT_GROUP_PRIM_TYPE 0 x0289#define regVGT_GROUP_PRIM_TYPE_BASE_IDX 1 #define regVGT_GROUP_FIRST_DECR 0 x028a#define regVGT_GROUP_FIRST_DECR_BASE_IDX 1 #define regVGT_GROUP_DECR 0 x028b#define regVGT_GROUP_DECR_BASE_IDX 1 #define regVGT_GROUP_VECT_0_CNTL 0 x028c#define regVGT_GROUP_VECT_0_CNTL_BASE_IDX 1 #define regVGT_GROUP_VECT_1_CNTL 0 x028d#define regVGT_GROUP_VECT_1_CNTL_BASE_IDX 1 #define regVGT_GROUP_VECT_0_FMT_CNTL 0 x028e#define regVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX 1 #define regVGT_GROUP_VECT_1_FMT_CNTL 0 x028f#define regVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX 1 #define regVGT_GS_MODE 0 x0290#define regVGT_GS_MODE_BASE_IDX 1 #define regVGT_GS_ONCHIP_CNTL 0 x0291#define regVGT_GS_ONCHIP_CNTL_BASE_IDX 1 #define regPA_SC_MODE_CNTL_0 0 x0292#define regPA_SC_MODE_CNTL_0_BASE_IDX 1 #define regPA_SC_MODE_CNTL_1 0 x0293#define regPA_SC_MODE_CNTL_1_BASE_IDX 1 #define regVGT_ENHANCE 0 x0294#define regVGT_ENHANCE_BASE_IDX 1 #define regVGT_GS_PER_ES 0 x0295#define regVGT_GS_PER_ES_BASE_IDX 1 #define regVGT_ES_PER_GS 0 x0296#define regVGT_ES_PER_GS_BASE_IDX 1 #define regVGT_GS_PER_VS 0 x0297#define regVGT_GS_PER_VS_BASE_IDX 1 #define regVGT_GSVS_RING_OFFSET_1 0 x0298#define regVGT_GSVS_RING_OFFSET_1_BASE_IDX 1 #define regVGT_GSVS_RING_OFFSET_2 0 x0299#define regVGT_GSVS_RING_OFFSET_2_BASE_IDX 1 #define regVGT_GSVS_RING_OFFSET_3 0 x029a#define regVGT_GSVS_RING_OFFSET_3_BASE_IDX 1 #define regVGT_GS_OUT_PRIM_TYPE 0 x029b#define regVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 #define regIA_ENHANCE 0 x029c#define regIA_ENHANCE_BASE_IDX 1 #define regVGT_DMA_SIZE 0 x029d#define regVGT_DMA_SIZE_BASE_IDX 1 #define regVGT_DMA_MAX_SIZE 0 x029e#define regVGT_DMA_MAX_SIZE_BASE_IDX 1 #define regVGT_DMA_INDEX_TYPE 0 x029f#define regVGT_DMA_INDEX_TYPE_BASE_IDX 1 #define regWD_ENHANCE 0 x02a0#define regWD_ENHANCE_BASE_IDX 1 #define regVGT_PRIMITIVEID_EN 0 x02a1#define regVGT_PRIMITIVEID_EN_BASE_IDX 1 #define regVGT_DMA_NUM_INSTANCES 0 x02a2#define regVGT_DMA_NUM_INSTANCES_BASE_IDX 1 #define regVGT_PRIMITIVEID_RESET 0 x02a3#define regVGT_PRIMITIVEID_RESET_BASE_IDX 1 #define regVGT_EVENT_INITIATOR 0 x02a4#define regVGT_EVENT_INITIATOR_BASE_IDX 1 #define regVGT_GS_MAX_PRIMS_PER_SUBGROUP 0 x02a5#define regVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 #define regVGT_DRAW_PAYLOAD_CNTL 0 x02a6#define regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 #define regVGT_INSTANCE_STEP_RATE_0 0 x02a8#define regVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 #define regVGT_INSTANCE_STEP_RATE_1 0 x02a9#define regVGT_INSTANCE_STEP_RATE_1_BASE_IDX 1 #define regIA_MULTI_VGT_PARAM_BC 0 x02aa#define regIA_MULTI_VGT_PARAM_BC_BASE_IDX 1 #define regVGT_ESGS_RING_ITEMSIZE 0 x02ab#define regVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1 #define regVGT_GSVS_RING_ITEMSIZE 0 x02ac#define regVGT_GSVS_RING_ITEMSIZE_BASE_IDX 1 #define regVGT_REUSE_OFF 0 x02ad#define regVGT_REUSE_OFF_BASE_IDX 1 #define regVGT_VTX_CNT_EN 0 x02ae#define regVGT_VTX_CNT_EN_BASE_IDX 1 #define regDB_HTILE_SURFACE 0 x02af#define regDB_HTILE_SURFACE_BASE_IDX 1 #define regDB_SRESULTS_COMPARE_STATE0 0 x02b0#define regDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 #define regDB_SRESULTS_COMPARE_STATE1 0 x02b1#define regDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 #define regDB_PRELOAD_CONTROL 0 x02b2#define regDB_PRELOAD_CONTROL_BASE_IDX 1 #define regVGT_STRMOUT_BUFFER_SIZE_0 0 x02b4#define regVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX 1 #define regVGT_STRMOUT_VTX_STRIDE_0 0 x02b5#define regVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX 1 #define regVGT_STRMOUT_BUFFER_OFFSET_0 0 x02b7#define regVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX 1 #define regVGT_STRMOUT_BUFFER_SIZE_1 0 x02b8#define regVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX 1 #define regVGT_STRMOUT_VTX_STRIDE_1 0 x02b9#define regVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX 1 #define regVGT_STRMOUT_BUFFER_OFFSET_1 0 x02bb#define regVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX 1 #define regVGT_STRMOUT_BUFFER_SIZE_2 0 x02bc#define regVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX 1 #define regVGT_STRMOUT_VTX_STRIDE_2 0 x02bd#define regVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX 1 #define regVGT_STRMOUT_BUFFER_OFFSET_2 0 x02bf#define regVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX 1 #define regVGT_STRMOUT_BUFFER_SIZE_3 0 x02c0#define regVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX 1 #define regVGT_STRMOUT_VTX_STRIDE_3 0 x02c1#define regVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX 1 #define regVGT_STRMOUT_BUFFER_OFFSET_3 0 x02c3#define regVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX 1 #define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0 x02ca#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 #define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0 x02cb#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 #define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0 x02cc#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 #define regVGT_GS_MAX_VERT_OUT 0 x02ce#define regVGT_GS_MAX_VERT_OUT_BASE_IDX 1 #define regVGT_TESS_DISTRIBUTION 0 x02d4#define regVGT_TESS_DISTRIBUTION_BASE_IDX 1 #define regVGT_SHADER_STAGES_EN 0 x02d5#define regVGT_SHADER_STAGES_EN_BASE_IDX 1 #define regVGT_LS_HS_CONFIG 0 x02d6#define regVGT_LS_HS_CONFIG_BASE_IDX 1 #define regVGT_GS_VERT_ITEMSIZE 0 x02d7#define regVGT_GS_VERT_ITEMSIZE_BASE_IDX 1 #define regVGT_GS_VERT_ITEMSIZE_1 0 x02d8#define regVGT_GS_VERT_ITEMSIZE_1_BASE_IDX 1 #define regVGT_GS_VERT_ITEMSIZE_2 0 x02d9#define regVGT_GS_VERT_ITEMSIZE_2_BASE_IDX 1 #define regVGT_GS_VERT_ITEMSIZE_3 0 x02da#define regVGT_GS_VERT_ITEMSIZE_3_BASE_IDX 1 #define regVGT_TF_PARAM 0 x02db#define regVGT_TF_PARAM_BASE_IDX 1 #define regDB_ALPHA_TO_MASK 0 x02dc#define regDB_ALPHA_TO_MASK_BASE_IDX 1 #define regVGT_DISPATCH_DRAW_INDEX 0 x02dd#define regVGT_DISPATCH_DRAW_INDEX_BASE_IDX 1 #define regPA_SU_POLY_OFFSET_DB_FMT_CNTL 0 x02de#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 #define regPA_SU_POLY_OFFSET_CLAMP 0 x02df#define regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 #define regPA_SU_POLY_OFFSET_FRONT_SCALE 0 x02e0#define regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 #define regPA_SU_POLY_OFFSET_FRONT_OFFSET 0 x02e1#define regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 #define regPA_SU_POLY_OFFSET_BACK_SCALE 0 x02e2#define regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 #define regPA_SU_POLY_OFFSET_BACK_OFFSET 0 x02e3#define regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 #define regVGT_GS_INSTANCE_CNT 0 x02e4#define regVGT_GS_INSTANCE_CNT_BASE_IDX 1 #define regVGT_STRMOUT_CONFIG 0 x02e5#define regVGT_STRMOUT_CONFIG_BASE_IDX 1 #define regVGT_STRMOUT_BUFFER_CONFIG 0 x02e6#define regVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX 1 #define regVGT_DMA_EVENT_INITIATOR 0 x02e7#define regVGT_DMA_EVENT_INITIATOR_BASE_IDX 1 #define regPA_SC_CENTROID_PRIORITY_0 0 x02f5#define regPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 #define regPA_SC_CENTROID_PRIORITY_1 0 x02f6#define regPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 #define regPA_SC_LINE_CNTL 0 x02f7#define regPA_SC_LINE_CNTL_BASE_IDX 1 #define regPA_SC_AA_CONFIG 0 x02f8#define regPA_SC_AA_CONFIG_BASE_IDX 1 #define regPA_SU_VTX_CNTL 0 x02f9#define regPA_SU_VTX_CNTL_BASE_IDX 1 #define regPA_CL_GB_VERT_CLIP_ADJ 0 x02fa#define regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 #define regPA_CL_GB_VERT_DISC_ADJ 0 x02fb#define regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 #define regPA_CL_GB_HORZ_CLIP_ADJ 0 x02fc#define regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 #define regPA_CL_GB_HORZ_DISC_ADJ 0 x02fd#define regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0 x02fe#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0 x02ff#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0 x0300#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0 x0301#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0 x0302#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0 x0303#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0 x0304#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0 x0305#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0 x0306#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0 x0307#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0 x0308#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0 x0309#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0 x030a#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0 x030b#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0 x030c#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0 x030d#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 #define regPA_SC_AA_MASK_X0Y0_X1Y0 0 x030e#define regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 #define regPA_SC_AA_MASK_X0Y1_X1Y1 0 x030f#define regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 #define regPA_SC_SHADER_CONTROL 0 x0310#define regPA_SC_SHADER_CONTROL_BASE_IDX 1 #define regPA_SC_BINNER_CNTL_0 0 x0311#define regPA_SC_BINNER_CNTL_0_BASE_IDX 1 #define regPA_SC_BINNER_CNTL_1 0 x0312#define regPA_SC_BINNER_CNTL_1_BASE_IDX 1 #define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0 x0313#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 #define regPA_SC_NGG_MODE_CNTL 0 x0314#define regPA_SC_NGG_MODE_CNTL_BASE_IDX 1 #define regVGT_VERTEX_REUSE_BLOCK_CNTL 0 x0316#define regVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX 1 #define regVGT_OUT_DEALLOC_CNTL 0 x0317#define regVGT_OUT_DEALLOC_CNTL_BASE_IDX 1 #define regCB_COLOR0_BASE 0 x0318#define regCB_COLOR0_BASE_BASE_IDX 1 #define regCB_COLOR0_BASE_EXT 0 x0319#define regCB_COLOR0_BASE_EXT_BASE_IDX 1 #define regCB_COLOR0_ATTRIB2 0 x031a#define regCB_COLOR0_ATTRIB2_BASE_IDX 1 #define regCB_COLOR0_VIEW 0 x031b#define regCB_COLOR0_VIEW_BASE_IDX 1 #define regCB_COLOR0_INFO 0 x031c#define regCB_COLOR0_INFO_BASE_IDX 1 #define regCB_COLOR0_ATTRIB 0 x031d#define regCB_COLOR0_ATTRIB_BASE_IDX 1 #define regCB_COLOR0_DCC_CONTROL 0 x031e#define regCB_COLOR0_DCC_CONTROL_BASE_IDX 1 #define regCB_COLOR0_CMASK 0 x031f#define regCB_COLOR0_CMASK_BASE_IDX 1 #define regCB_COLOR0_CMASK_BASE_EXT 0 x0320#define regCB_COLOR0_CMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR0_FMASK 0 x0321#define regCB_COLOR0_FMASK_BASE_IDX 1 #define regCB_COLOR0_FMASK_BASE_EXT 0 x0322#define regCB_COLOR0_FMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR0_CLEAR_WORD0 0 x0323#define regCB_COLOR0_CLEAR_WORD0_BASE_IDX 1 #define regCB_COLOR0_CLEAR_WORD1 0 x0324#define regCB_COLOR0_CLEAR_WORD1_BASE_IDX 1 #define regCB_COLOR0_DCC_BASE 0 x0325#define regCB_COLOR0_DCC_BASE_BASE_IDX 1 #define regCB_COLOR0_DCC_BASE_EXT 0 x0326#define regCB_COLOR0_DCC_BASE_EXT_BASE_IDX 1 #define regCB_COLOR1_BASE 0 x0327#define regCB_COLOR1_BASE_BASE_IDX 1 #define regCB_COLOR1_BASE_EXT 0 x0328#define regCB_COLOR1_BASE_EXT_BASE_IDX 1 #define regCB_COLOR1_ATTRIB2 0 x0329#define regCB_COLOR1_ATTRIB2_BASE_IDX 1 #define regCB_COLOR1_VIEW 0 x032a#define regCB_COLOR1_VIEW_BASE_IDX 1 #define regCB_COLOR1_INFO 0 x032b#define regCB_COLOR1_INFO_BASE_IDX 1 #define regCB_COLOR1_ATTRIB 0 x032c#define regCB_COLOR1_ATTRIB_BASE_IDX 1 #define regCB_COLOR1_DCC_CONTROL 0 x032d#define regCB_COLOR1_DCC_CONTROL_BASE_IDX 1 #define regCB_COLOR1_CMASK 0 x032e#define regCB_COLOR1_CMASK_BASE_IDX 1 #define regCB_COLOR1_CMASK_BASE_EXT 0 x032f#define regCB_COLOR1_CMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR1_FMASK 0 x0330#define regCB_COLOR1_FMASK_BASE_IDX 1 #define regCB_COLOR1_FMASK_BASE_EXT 0 x0331#define regCB_COLOR1_FMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR1_CLEAR_WORD0 0 x0332#define regCB_COLOR1_CLEAR_WORD0_BASE_IDX 1 #define regCB_COLOR1_CLEAR_WORD1 0 x0333#define regCB_COLOR1_CLEAR_WORD1_BASE_IDX 1 #define regCB_COLOR1_DCC_BASE 0 x0334#define regCB_COLOR1_DCC_BASE_BASE_IDX 1 #define regCB_COLOR1_DCC_BASE_EXT 0 x0335#define regCB_COLOR1_DCC_BASE_EXT_BASE_IDX 1 #define regCB_COLOR2_BASE 0 x0336#define regCB_COLOR2_BASE_BASE_IDX 1 #define regCB_COLOR2_BASE_EXT 0 x0337#define regCB_COLOR2_BASE_EXT_BASE_IDX 1 #define regCB_COLOR2_ATTRIB2 0 x0338#define regCB_COLOR2_ATTRIB2_BASE_IDX 1 #define regCB_COLOR2_VIEW 0 x0339#define regCB_COLOR2_VIEW_BASE_IDX 1 #define regCB_COLOR2_INFO 0 x033a#define regCB_COLOR2_INFO_BASE_IDX 1 #define regCB_COLOR2_ATTRIB 0 x033b#define regCB_COLOR2_ATTRIB_BASE_IDX 1 #define regCB_COLOR2_DCC_CONTROL 0 x033c#define regCB_COLOR2_DCC_CONTROL_BASE_IDX 1 #define regCB_COLOR2_CMASK 0 x033d#define regCB_COLOR2_CMASK_BASE_IDX 1 #define regCB_COLOR2_CMASK_BASE_EXT 0 x033e#define regCB_COLOR2_CMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR2_FMASK 0 x033f#define regCB_COLOR2_FMASK_BASE_IDX 1 #define regCB_COLOR2_FMASK_BASE_EXT 0 x0340#define regCB_COLOR2_FMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR2_CLEAR_WORD0 0 x0341#define regCB_COLOR2_CLEAR_WORD0_BASE_IDX 1 #define regCB_COLOR2_CLEAR_WORD1 0 x0342#define regCB_COLOR2_CLEAR_WORD1_BASE_IDX 1 #define regCB_COLOR2_DCC_BASE 0 x0343#define regCB_COLOR2_DCC_BASE_BASE_IDX 1 #define regCB_COLOR2_DCC_BASE_EXT 0 x0344#define regCB_COLOR2_DCC_BASE_EXT_BASE_IDX 1 #define regCB_COLOR3_BASE 0 x0345#define regCB_COLOR3_BASE_BASE_IDX 1 #define regCB_COLOR3_BASE_EXT 0 x0346#define regCB_COLOR3_BASE_EXT_BASE_IDX 1 #define regCB_COLOR3_ATTRIB2 0 x0347#define regCB_COLOR3_ATTRIB2_BASE_IDX 1 #define regCB_COLOR3_VIEW 0 x0348#define regCB_COLOR3_VIEW_BASE_IDX 1 #define regCB_COLOR3_INFO 0 x0349#define regCB_COLOR3_INFO_BASE_IDX 1 #define regCB_COLOR3_ATTRIB 0 x034a#define regCB_COLOR3_ATTRIB_BASE_IDX 1 #define regCB_COLOR3_DCC_CONTROL 0 x034b#define regCB_COLOR3_DCC_CONTROL_BASE_IDX 1 #define regCB_COLOR3_CMASK 0 x034c#define regCB_COLOR3_CMASK_BASE_IDX 1 #define regCB_COLOR3_CMASK_BASE_EXT 0 x034d#define regCB_COLOR3_CMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR3_FMASK 0 x034e#define regCB_COLOR3_FMASK_BASE_IDX 1 #define regCB_COLOR3_FMASK_BASE_EXT 0 x034f#define regCB_COLOR3_FMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR3_CLEAR_WORD0 0 x0350#define regCB_COLOR3_CLEAR_WORD0_BASE_IDX 1 #define regCB_COLOR3_CLEAR_WORD1 0 x0351#define regCB_COLOR3_CLEAR_WORD1_BASE_IDX 1 #define regCB_COLOR3_DCC_BASE 0 x0352#define regCB_COLOR3_DCC_BASE_BASE_IDX 1 #define regCB_COLOR3_DCC_BASE_EXT 0 x0353#define regCB_COLOR3_DCC_BASE_EXT_BASE_IDX 1 #define regCB_COLOR4_BASE 0 x0354#define regCB_COLOR4_BASE_BASE_IDX 1 #define regCB_COLOR4_BASE_EXT 0 x0355#define regCB_COLOR4_BASE_EXT_BASE_IDX 1 #define regCB_COLOR4_ATTRIB2 0 x0356#define regCB_COLOR4_ATTRIB2_BASE_IDX 1 #define regCB_COLOR4_VIEW 0 x0357#define regCB_COLOR4_VIEW_BASE_IDX 1 #define regCB_COLOR4_INFO 0 x0358#define regCB_COLOR4_INFO_BASE_IDX 1 #define regCB_COLOR4_ATTRIB 0 x0359#define regCB_COLOR4_ATTRIB_BASE_IDX 1 #define regCB_COLOR4_DCC_CONTROL 0 x035a#define regCB_COLOR4_DCC_CONTROL_BASE_IDX 1 #define regCB_COLOR4_CMASK 0 x035b#define regCB_COLOR4_CMASK_BASE_IDX 1 #define regCB_COLOR4_CMASK_BASE_EXT 0 x035c#define regCB_COLOR4_CMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR4_FMASK 0 x035d#define regCB_COLOR4_FMASK_BASE_IDX 1 #define regCB_COLOR4_FMASK_BASE_EXT 0 x035e#define regCB_COLOR4_FMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR4_CLEAR_WORD0 0 x035f#define regCB_COLOR4_CLEAR_WORD0_BASE_IDX 1 #define regCB_COLOR4_CLEAR_WORD1 0 x0360#define regCB_COLOR4_CLEAR_WORD1_BASE_IDX 1 #define regCB_COLOR4_DCC_BASE 0 x0361#define regCB_COLOR4_DCC_BASE_BASE_IDX 1 #define regCB_COLOR4_DCC_BASE_EXT 0 x0362#define regCB_COLOR4_DCC_BASE_EXT_BASE_IDX 1 #define regCB_COLOR5_BASE 0 x0363#define regCB_COLOR5_BASE_BASE_IDX 1 #define regCB_COLOR5_BASE_EXT 0 x0364#define regCB_COLOR5_BASE_EXT_BASE_IDX 1 #define regCB_COLOR5_ATTRIB2 0 x0365#define regCB_COLOR5_ATTRIB2_BASE_IDX 1 #define regCB_COLOR5_VIEW 0 x0366#define regCB_COLOR5_VIEW_BASE_IDX 1 #define regCB_COLOR5_INFO 0 x0367#define regCB_COLOR5_INFO_BASE_IDX 1 #define regCB_COLOR5_ATTRIB 0 x0368#define regCB_COLOR5_ATTRIB_BASE_IDX 1 #define regCB_COLOR5_DCC_CONTROL 0 x0369#define regCB_COLOR5_DCC_CONTROL_BASE_IDX 1 #define regCB_COLOR5_CMASK 0 x036a#define regCB_COLOR5_CMASK_BASE_IDX 1 #define regCB_COLOR5_CMASK_BASE_EXT 0 x036b#define regCB_COLOR5_CMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR5_FMASK 0 x036c#define regCB_COLOR5_FMASK_BASE_IDX 1 #define regCB_COLOR5_FMASK_BASE_EXT 0 x036d#define regCB_COLOR5_FMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR5_CLEAR_WORD0 0 x036e#define regCB_COLOR5_CLEAR_WORD0_BASE_IDX 1 #define regCB_COLOR5_CLEAR_WORD1 0 x036f#define regCB_COLOR5_CLEAR_WORD1_BASE_IDX 1 #define regCB_COLOR5_DCC_BASE 0 x0370#define regCB_COLOR5_DCC_BASE_BASE_IDX 1 #define regCB_COLOR5_DCC_BASE_EXT 0 x0371#define regCB_COLOR5_DCC_BASE_EXT_BASE_IDX 1 #define regCB_COLOR6_BASE 0 x0372#define regCB_COLOR6_BASE_BASE_IDX 1 #define regCB_COLOR6_BASE_EXT 0 x0373#define regCB_COLOR6_BASE_EXT_BASE_IDX 1 #define regCB_COLOR6_ATTRIB2 0 x0374#define regCB_COLOR6_ATTRIB2_BASE_IDX 1 #define regCB_COLOR6_VIEW 0 x0375#define regCB_COLOR6_VIEW_BASE_IDX 1 #define regCB_COLOR6_INFO 0 x0376#define regCB_COLOR6_INFO_BASE_IDX 1 #define regCB_COLOR6_ATTRIB 0 x0377#define regCB_COLOR6_ATTRIB_BASE_IDX 1 #define regCB_COLOR6_DCC_CONTROL 0 x0378#define regCB_COLOR6_DCC_CONTROL_BASE_IDX 1 #define regCB_COLOR6_CMASK 0 x0379#define regCB_COLOR6_CMASK_BASE_IDX 1 #define regCB_COLOR6_CMASK_BASE_EXT 0 x037a#define regCB_COLOR6_CMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR6_FMASK 0 x037b#define regCB_COLOR6_FMASK_BASE_IDX 1 #define regCB_COLOR6_FMASK_BASE_EXT 0 x037c#define regCB_COLOR6_FMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR6_CLEAR_WORD0 0 x037d#define regCB_COLOR6_CLEAR_WORD0_BASE_IDX 1 #define regCB_COLOR6_CLEAR_WORD1 0 x037e#define regCB_COLOR6_CLEAR_WORD1_BASE_IDX 1 #define regCB_COLOR6_DCC_BASE 0 x037f#define regCB_COLOR6_DCC_BASE_BASE_IDX 1 #define regCB_COLOR6_DCC_BASE_EXT 0 x0380#define regCB_COLOR6_DCC_BASE_EXT_BASE_IDX 1 #define regCB_COLOR7_BASE 0 x0381#define regCB_COLOR7_BASE_BASE_IDX 1 #define regCB_COLOR7_BASE_EXT 0 x0382#define regCB_COLOR7_BASE_EXT_BASE_IDX 1 #define regCB_COLOR7_ATTRIB2 0 x0383#define regCB_COLOR7_ATTRIB2_BASE_IDX 1 #define regCB_COLOR7_VIEW 0 x0384#define regCB_COLOR7_VIEW_BASE_IDX 1 #define regCB_COLOR7_INFO 0 x0385#define regCB_COLOR7_INFO_BASE_IDX 1 #define regCB_COLOR7_ATTRIB 0 x0386#define regCB_COLOR7_ATTRIB_BASE_IDX 1 #define regCB_COLOR7_DCC_CONTROL 0 x0387#define regCB_COLOR7_DCC_CONTROL_BASE_IDX 1 #define regCB_COLOR7_CMASK 0 x0388#define regCB_COLOR7_CMASK_BASE_IDX 1 #define regCB_COLOR7_CMASK_BASE_EXT 0 x0389#define regCB_COLOR7_CMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR7_FMASK 0 x038a#define regCB_COLOR7_FMASK_BASE_IDX 1 #define regCB_COLOR7_FMASK_BASE_EXT 0 x038b#define regCB_COLOR7_FMASK_BASE_EXT_BASE_IDX 1 #define regCB_COLOR7_CLEAR_WORD0 0 x038c#define regCB_COLOR7_CLEAR_WORD0_BASE_IDX 1 #define regCB_COLOR7_CLEAR_WORD1 0 x038d#define regCB_COLOR7_CLEAR_WORD1_BASE_IDX 1 #define regCB_COLOR7_DCC_BASE 0 x038e#define regCB_COLOR7_DCC_BASE_BASE_IDX 1 #define regCB_COLOR7_DCC_BASE_EXT 0 x038f#define regCB_COLOR7_DCC_BASE_EXT_BASE_IDX 1 // addressBlock: gc_gfxudec // base address: 0x30000 #define regCP_EOP_DONE_ADDR_LO 0 x2000#define regCP_EOP_DONE_ADDR_LO_BASE_IDX 1 #define regCP_EOP_DONE_ADDR_HI 0 x2001#define regCP_EOP_DONE_ADDR_HI_BASE_IDX 1 #define regCP_EOP_DONE_DATA_LO 0 x2002#define regCP_EOP_DONE_DATA_LO_BASE_IDX 1 #define regCP_EOP_DONE_DATA_HI 0 x2003#define regCP_EOP_DONE_DATA_HI_BASE_IDX 1 #define regCP_EOP_LAST_FENCE_LO 0 x2004#define regCP_EOP_LAST_FENCE_LO_BASE_IDX 1 #define regCP_EOP_LAST_FENCE_HI 0 x2005#define regCP_EOP_LAST_FENCE_HI_BASE_IDX 1 #define regCP_STREAM_OUT_ADDR_LO 0 x2006#define regCP_STREAM_OUT_ADDR_LO_BASE_IDX 1 #define regCP_STREAM_OUT_ADDR_HI 0 x2007#define regCP_STREAM_OUT_ADDR_HI_BASE_IDX 1 #define regCP_NUM_PRIM_WRITTEN_COUNT0_LO 0 x2008#define regCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX 1 #define regCP_NUM_PRIM_WRITTEN_COUNT0_HI 0 x2009#define regCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX 1 #define regCP_NUM_PRIM_NEEDED_COUNT0_LO 0 x200a#define regCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX 1 #define regCP_NUM_PRIM_NEEDED_COUNT0_HI 0 x200b#define regCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX 1 #define regCP_NUM_PRIM_WRITTEN_COUNT1_LO 0 x200c#define regCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX 1 #define regCP_NUM_PRIM_WRITTEN_COUNT1_HI 0 x200d#define regCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX 1 #define regCP_NUM_PRIM_NEEDED_COUNT1_LO 0 x200e#define regCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX 1 #define regCP_NUM_PRIM_NEEDED_COUNT1_HI 0 x200f#define regCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX 1 #define regCP_NUM_PRIM_WRITTEN_COUNT2_LO 0 x2010#define regCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX 1 #define regCP_NUM_PRIM_WRITTEN_COUNT2_HI 0 x2011#define regCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX 1 #define regCP_NUM_PRIM_NEEDED_COUNT2_LO 0 x2012#define regCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX 1 #define regCP_NUM_PRIM_NEEDED_COUNT2_HI 0 x2013#define regCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX 1 #define regCP_NUM_PRIM_WRITTEN_COUNT3_LO 0 x2014#define regCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX 1 #define regCP_NUM_PRIM_WRITTEN_COUNT3_HI 0 x2015#define regCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX 1 #define regCP_NUM_PRIM_NEEDED_COUNT3_LO 0 x2016#define regCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX 1 #define regCP_NUM_PRIM_NEEDED_COUNT3_HI 0 x2017#define regCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX 1 #define regCP_PIPE_STATS_ADDR_LO 0 x2018#define regCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 #define regCP_PIPE_STATS_ADDR_HI 0 x2019#define regCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 #define regCP_VGT_IAVERT_COUNT_LO 0 x201a#define regCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 #define regCP_VGT_IAVERT_COUNT_HI 0 x201b#define regCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 #define regCP_VGT_IAPRIM_COUNT_LO 0 x201c#define regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 #define regCP_VGT_IAPRIM_COUNT_HI 0 x201d#define regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 #define regCP_VGT_GSPRIM_COUNT_LO 0 x201e#define regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 #define regCP_VGT_GSPRIM_COUNT_HI 0 x201f#define regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 #define regCP_VGT_VSINVOC_COUNT_LO 0 x2020#define regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 #define regCP_VGT_VSINVOC_COUNT_HI 0 x2021#define regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 #define regCP_VGT_GSINVOC_COUNT_LO 0 x2022#define regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 #define regCP_VGT_GSINVOC_COUNT_HI 0 x2023#define regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 #define regCP_VGT_HSINVOC_COUNT_LO 0 x2024#define regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 #define regCP_VGT_HSINVOC_COUNT_HI 0 x2025#define regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 #define regCP_VGT_DSINVOC_COUNT_LO 0 x2026#define regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 #define regCP_VGT_DSINVOC_COUNT_HI 0 x2027#define regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 #define regCP_PA_CINVOC_COUNT_LO 0 x2028#define regCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 #define regCP_PA_CINVOC_COUNT_HI 0 x2029#define regCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 #define regCP_PA_CPRIM_COUNT_LO 0 x202a#define regCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 #define regCP_PA_CPRIM_COUNT_HI 0 x202b#define regCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 #define regCP_SC_PSINVOC_COUNT0_LO 0 x202c#define regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 #define regCP_SC_PSINVOC_COUNT0_HI 0 x202d#define regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 #define regCP_SC_PSINVOC_COUNT1_LO 0 x202e#define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 #define regCP_SC_PSINVOC_COUNT1_HI 0 x202f#define regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 #define regCP_VGT_CSINVOC_COUNT_LO 0 x2030#define regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 #define regCP_VGT_CSINVOC_COUNT_HI 0 x2031#define regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 #define regCP_PIPE_STATS_CONTROL 0 x203d#define regCP_PIPE_STATS_CONTROL_BASE_IDX 1 #define regCP_STREAM_OUT_CONTROL 0 x203e#define regCP_STREAM_OUT_CONTROL_BASE_IDX 1 #define regCP_STRMOUT_CNTL 0 x203f#define regCP_STRMOUT_CNTL_BASE_IDX 1 #define regSCRATCH_REG0 0 x2040#define regSCRATCH_REG0_BASE_IDX 1 #define regSCRATCH_REG1 0 x2041#define regSCRATCH_REG1_BASE_IDX 1 #define regSCRATCH_REG2 0 x2042#define regSCRATCH_REG2_BASE_IDX 1 #define regSCRATCH_REG3 0 x2043#define regSCRATCH_REG3_BASE_IDX 1 #define regSCRATCH_REG4 0 x2044#define regSCRATCH_REG4_BASE_IDX 1 #define regSCRATCH_REG5 0 x2045#define regSCRATCH_REG5_BASE_IDX 1 #define regSCRATCH_REG6 0 x2046#define regSCRATCH_REG6_BASE_IDX 1 #define regSCRATCH_REG7 0 x2047#define regSCRATCH_REG7_BASE_IDX 1 #define regCP_APPEND_DATA_HI 0 x204c#define regCP_APPEND_DATA_HI_BASE_IDX 1 #define regCP_APPEND_LAST_CS_FENCE_HI 0 x204d#define regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 #define regCP_APPEND_LAST_PS_FENCE_HI 0 x204e#define regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 #define regSCRATCH_UMSK 0 x2050#define regSCRATCH_UMSK_BASE_IDX 1 #define regSCRATCH_ADDR 0 x2051#define regSCRATCH_ADDR_BASE_IDX 1 #define regCP_PFP_ATOMIC_PREOP_LO 0 x2052#define regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 #define regCP_PFP_ATOMIC_PREOP_HI 0 x2053#define regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 #define regCP_PFP_GDS_ATOMIC0_PREOP_LO 0 x2054#define regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 #define regCP_PFP_GDS_ATOMIC0_PREOP_HI 0 x2055#define regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 #define regCP_PFP_GDS_ATOMIC1_PREOP_LO 0 x2056#define regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 #define regCP_PFP_GDS_ATOMIC1_PREOP_HI 0 x2057#define regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 #define regCP_APPEND_ADDR_LO 0 x2058#define regCP_APPEND_ADDR_LO_BASE_IDX 1 #define regCP_APPEND_ADDR_HI 0 x2059#define regCP_APPEND_ADDR_HI_BASE_IDX 1 #define regCP_APPEND_DATA_LO 0 x205a#define regCP_APPEND_DATA_LO_BASE_IDX 1 #define regCP_APPEND_LAST_CS_FENCE_LO 0 x205b#define regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 #define regCP_APPEND_LAST_PS_FENCE_LO 0 x205c#define regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 #define regCP_ATOMIC_PREOP_LO 0 x205d#define regCP_ATOMIC_PREOP_LO_BASE_IDX 1 #define regCP_ME_ATOMIC_PREOP_LO 0 x205d#define regCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 #define regCP_ATOMIC_PREOP_HI 0 x205e#define regCP_ATOMIC_PREOP_HI_BASE_IDX 1 #define regCP_ME_ATOMIC_PREOP_HI 0 x205e#define regCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 #define regCP_GDS_ATOMIC0_PREOP_LO 0 x205f#define regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 #define regCP_ME_GDS_ATOMIC0_PREOP_LO 0 x205f#define regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX 1 #define regCP_GDS_ATOMIC0_PREOP_HI 0 x2060#define regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 #define regCP_ME_GDS_ATOMIC0_PREOP_HI 0 x2060#define regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX 1 #define regCP_GDS_ATOMIC1_PREOP_LO 0 x2061#define regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 #define regCP_ME_GDS_ATOMIC1_PREOP_LO 0 x2061#define regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX 1 #define regCP_GDS_ATOMIC1_PREOP_HI 0 x2062#define regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 #define regCP_ME_GDS_ATOMIC1_PREOP_HI 0 x2062#define regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX 1 #define regCP_ME_MC_WADDR_LO 0 x2069#define regCP_ME_MC_WADDR_LO_BASE_IDX 1 #define regCP_ME_MC_WADDR_HI 0 x206a#define regCP_ME_MC_WADDR_HI_BASE_IDX 1 #define regCP_ME_MC_WDATA_LO 0 x206b#define regCP_ME_MC_WDATA_LO_BASE_IDX 1 #define regCP_ME_MC_WDATA_HI 0 x206c#define regCP_ME_MC_WDATA_HI_BASE_IDX 1 #define regCP_ME_MC_RADDR_LO 0 x206d#define regCP_ME_MC_RADDR_LO_BASE_IDX 1 #define regCP_ME_MC_RADDR_HI 0 x206e#define regCP_ME_MC_RADDR_HI_BASE_IDX 1 #define regCP_SEM_WAIT_TIMER 0 x206f#define regCP_SEM_WAIT_TIMER_BASE_IDX 1 #define regCP_SIG_SEM_ADDR_LO 0 x2070#define regCP_SIG_SEM_ADDR_LO_BASE_IDX 1 #define regCP_SIG_SEM_ADDR_HI 0 x2071#define regCP_SIG_SEM_ADDR_HI_BASE_IDX 1 #define regCP_WAIT_REG_MEM_TIMEOUT 0 x2074#define regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 #define regCP_WAIT_SEM_ADDR_LO 0 x2075#define regCP_WAIT_SEM_ADDR_LO_BASE_IDX 1 #define regCP_WAIT_SEM_ADDR_HI 0 x2076#define regCP_WAIT_SEM_ADDR_HI_BASE_IDX 1 #define regCP_DMA_PFP_CONTROL 0 x2077#define regCP_DMA_PFP_CONTROL_BASE_IDX 1 #define regCP_DMA_ME_CONTROL 0 x2078#define regCP_DMA_ME_CONTROL_BASE_IDX 1 #define regCP_COHER_BASE_HI 0 x2079#define regCP_COHER_BASE_HI_BASE_IDX 1 #define regCP_COHER_START_DELAY 0 x207b#define regCP_COHER_START_DELAY_BASE_IDX 1 #define regCP_COHER_CNTL 0 x207c#define regCP_COHER_CNTL_BASE_IDX 1 #define regCP_COHER_SIZE 0 x207d#define regCP_COHER_SIZE_BASE_IDX 1 #define regCP_COHER_BASE 0 x207e#define regCP_COHER_BASE_BASE_IDX 1 #define regCP_COHER_STATUS 0 x207f#define regCP_COHER_STATUS_BASE_IDX 1 #define regCP_DMA_ME_SRC_ADDR 0 x2080#define regCP_DMA_ME_SRC_ADDR_BASE_IDX 1 #define regCP_DMA_ME_SRC_ADDR_HI 0 x2081#define regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 #define regCP_DMA_ME_DST_ADDR 0 x2082#define regCP_DMA_ME_DST_ADDR_BASE_IDX 1 #define regCP_DMA_ME_DST_ADDR_HI 0 x2083#define regCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 #define regCP_DMA_ME_COMMAND 0 x2084#define regCP_DMA_ME_COMMAND_BASE_IDX 1 #define regCP_DMA_PFP_SRC_ADDR 0 x2085#define regCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 #define regCP_DMA_PFP_SRC_ADDR_HI 0 x2086#define regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 #define regCP_DMA_PFP_DST_ADDR 0 x2087#define regCP_DMA_PFP_DST_ADDR_BASE_IDX 1 #define regCP_DMA_PFP_DST_ADDR_HI 0 x2088#define regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 #define regCP_DMA_PFP_COMMAND 0 x2089#define regCP_DMA_PFP_COMMAND_BASE_IDX 1 #define regCP_DMA_CNTL 0 x208a#define regCP_DMA_CNTL_BASE_IDX 1 #define regCP_DMA_READ_TAGS 0 x208b#define regCP_DMA_READ_TAGS_BASE_IDX 1 #define regCP_COHER_SIZE_HI 0 x208c#define regCP_COHER_SIZE_HI_BASE_IDX 1 #define regCP_PFP_IB_CONTROL 0 x208d#define regCP_PFP_IB_CONTROL_BASE_IDX 1 #define regCP_PFP_LOAD_CONTROL 0 x208e#define regCP_PFP_LOAD_CONTROL_BASE_IDX 1 #define regCP_SCRATCH_INDEX 0 x208f#define regCP_SCRATCH_INDEX_BASE_IDX 1 #define regCP_SCRATCH_DATA 0 x2090#define regCP_SCRATCH_DATA_BASE_IDX 1 #define regCP_RB_OFFSET 0 x2091#define regCP_RB_OFFSET_BASE_IDX 1 #define regCP_IB2_OFFSET 0 x2093#define regCP_IB2_OFFSET_BASE_IDX 1 #define regCP_IB2_PREAMBLE_BEGIN 0 x2096#define regCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 #define regCP_IB2_PREAMBLE_END 0 x2097#define regCP_IB2_PREAMBLE_END_BASE_IDX 1 #define regCP_CE_IB1_OFFSET 0 x2098#define regCP_CE_IB1_OFFSET_BASE_IDX 1 #define regCP_CE_IB2_OFFSET 0 x2099#define regCP_CE_IB2_OFFSET_BASE_IDX 1 #define regCP_CE_COUNTER 0 x209a#define regCP_CE_COUNTER_BASE_IDX 1 #define regCP_CE_RB_OFFSET 0 x209b#define regCP_CE_RB_OFFSET_BASE_IDX 1 #define regCP_CE_INIT_CMD_BUFSZ 0 x20bd#define regCP_CE_INIT_CMD_BUFSZ_BASE_IDX 1 #define regCP_CE_IB1_CMD_BUFSZ 0 x20be#define regCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1 #define regCP_CE_IB2_CMD_BUFSZ 0 x20bf#define regCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1 #define regCP_IB2_CMD_BUFSZ 0 x20c1#define regCP_IB2_CMD_BUFSZ_BASE_IDX 1 #define regCP_ST_CMD_BUFSZ 0 x20c2#define regCP_ST_CMD_BUFSZ_BASE_IDX 1 #define regCP_CE_INIT_BASE_LO 0 x20c3#define regCP_CE_INIT_BASE_LO_BASE_IDX 1 #define regCP_CE_INIT_BASE_HI 0 x20c4#define regCP_CE_INIT_BASE_HI_BASE_IDX 1 #define regCP_CE_INIT_BUFSZ 0 x20c5#define regCP_CE_INIT_BUFSZ_BASE_IDX 1 #define regCP_CE_IB1_BASE_LO 0 x20c6#define regCP_CE_IB1_BASE_LO_BASE_IDX 1 #define regCP_CE_IB1_BASE_HI 0 x20c7#define regCP_CE_IB1_BASE_HI_BASE_IDX 1 #define regCP_CE_IB1_BUFSZ 0 x20c8#define regCP_CE_IB1_BUFSZ_BASE_IDX 1 #define regCP_CE_IB2_BASE_LO 0 x20c9#define regCP_CE_IB2_BASE_LO_BASE_IDX 1 #define regCP_CE_IB2_BASE_HI 0 x20ca#define regCP_CE_IB2_BASE_HI_BASE_IDX 1 #define regCP_CE_IB2_BUFSZ 0 x20cb#define regCP_CE_IB2_BUFSZ_BASE_IDX 1 #define regCP_IB2_BASE_LO 0 x20cf#define regCP_IB2_BASE_LO_BASE_IDX 1 #define regCP_IB2_BASE_HI 0 x20d0#define regCP_IB2_BASE_HI_BASE_IDX 1 #define regCP_IB2_BUFSZ 0 x20d1#define regCP_IB2_BUFSZ_BASE_IDX 1 #define regCP_ST_BASE_LO 0 x20d2#define regCP_ST_BASE_LO_BASE_IDX 1 #define regCP_ST_BASE_HI 0 x20d3#define regCP_ST_BASE_HI_BASE_IDX 1 #define regCP_ST_BUFSZ 0 x20d4#define regCP_ST_BUFSZ_BASE_IDX 1 #define regCP_EOP_DONE_EVENT_CNTL 0 x20d5#define regCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 #define regCP_EOP_DONE_DATA_CNTL 0 x20d6#define regCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 #define regCP_EOP_DONE_CNTX_ID 0 x20d7#define regCP_EOP_DONE_CNTX_ID_BASE_IDX 1 #define regCP_PFP_COMPLETION_STATUS 0 x20ec#define regCP_PFP_COMPLETION_STATUS_BASE_IDX 1 #define regCP_CE_COMPLETION_STATUS 0 x20ed#define regCP_CE_COMPLETION_STATUS_BASE_IDX 1 #define regCP_PRED_NOT_VISIBLE 0 x20ee#define regCP_PRED_NOT_VISIBLE_BASE_IDX 1 #define regCP_PFP_METADATA_BASE_ADDR 0 x20f0#define regCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 #define regCP_PFP_METADATA_BASE_ADDR_HI 0 x20f1#define regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 #define regCP_CE_METADATA_BASE_ADDR 0 x20f2#define regCP_CE_METADATA_BASE_ADDR_BASE_IDX 1 #define regCP_CE_METADATA_BASE_ADDR_HI 0 x20f3#define regCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX 1 #define regCP_DRAW_INDX_INDR_ADDR 0 x20f4#define regCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 #define regCP_DRAW_INDX_INDR_ADDR_HI 0 x20f5#define regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 #define regCP_DISPATCH_INDR_ADDR 0 x20f6#define regCP_DISPATCH_INDR_ADDR_BASE_IDX 1 #define regCP_DISPATCH_INDR_ADDR_HI 0 x20f7#define regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 #define regCP_INDEX_BASE_ADDR 0 x20f8#define regCP_INDEX_BASE_ADDR_BASE_IDX 1 #define regCP_INDEX_BASE_ADDR_HI 0 x20f9#define regCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 #define regCP_INDEX_TYPE 0 x20fa#define regCP_INDEX_TYPE_BASE_IDX 1 #define regCP_GDS_BKUP_ADDR 0 x20fb#define regCP_GDS_BKUP_ADDR_BASE_IDX 1 #define regCP_GDS_BKUP_ADDR_HI 0 x20fc#define regCP_GDS_BKUP_ADDR_HI_BASE_IDX 1 #define regCP_SAMPLE_STATUS 0 x20fd#define regCP_SAMPLE_STATUS_BASE_IDX 1 #define regCP_ME_COHER_CNTL 0 x20fe#define regCP_ME_COHER_CNTL_BASE_IDX 1 #define regCP_ME_COHER_SIZE 0 x20ff#define regCP_ME_COHER_SIZE_BASE_IDX 1 #define regCP_ME_COHER_SIZE_HI 0 x2100#define regCP_ME_COHER_SIZE_HI_BASE_IDX 1 #define regCP_ME_COHER_BASE 0 x2101#define regCP_ME_COHER_BASE_BASE_IDX 1 #define regCP_ME_COHER_BASE_HI 0 x2102#define regCP_ME_COHER_BASE_HI_BASE_IDX 1 #define regCP_ME_COHER_STATUS 0 x2103#define regCP_ME_COHER_STATUS_BASE_IDX 1 #define regRLC_GPM_PERF_COUNT_0 0 x2140#define regRLC_GPM_PERF_COUNT_0_BASE_IDX 1 #define regRLC_GPM_PERF_COUNT_1 0 x2141#define regRLC_GPM_PERF_COUNT_1_BASE_IDX 1 #define regGRBM_GFX_INDEX 0 x2200#define regGRBM_GFX_INDEX_BASE_IDX 1 #define regVGT_GSVS_RING_SIZE 0 x2241#define regVGT_GSVS_RING_SIZE_BASE_IDX 1 #define regVGT_PRIMITIVE_TYPE 0 x2242#define regVGT_PRIMITIVE_TYPE_BASE_IDX 1 #define regVGT_INDEX_TYPE 0 x2243#define regVGT_INDEX_TYPE_BASE_IDX 1 #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0 x2244#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX 1 #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0 x2245#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX 1 #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0 x2246#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX 1 #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0 x2247#define regVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX 1 #define regVGT_MAX_VTX_INDX 0 x2248#define regVGT_MAX_VTX_INDX_BASE_IDX 1 #define regVGT_MIN_VTX_INDX 0 x2249#define regVGT_MIN_VTX_INDX_BASE_IDX 1 #define regVGT_INDX_OFFSET 0 x224a#define regVGT_INDX_OFFSET_BASE_IDX 1 #define regVGT_MULTI_PRIM_IB_RESET_EN 0 x224b#define regVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 #define regVGT_NUM_INDICES 0 x224c#define regVGT_NUM_INDICES_BASE_IDX 1 #define regVGT_NUM_INSTANCES 0 x224d#define regVGT_NUM_INSTANCES_BASE_IDX 1 #define regVGT_TF_RING_SIZE 0 x224e#define regVGT_TF_RING_SIZE_BASE_IDX 1 #define regVGT_HS_OFFCHIP_PARAM 0 x224f#define regVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 #define regVGT_TF_MEMORY_BASE 0 x2250#define regVGT_TF_MEMORY_BASE_BASE_IDX 1 #define regVGT_TF_MEMORY_BASE_HI 0 x2251#define regVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 #define regWD_POS_BUF_BASE 0 x2252#define regWD_POS_BUF_BASE_BASE_IDX 1 #define regWD_POS_BUF_BASE_HI 0 x2253#define regWD_POS_BUF_BASE_HI_BASE_IDX 1 #define regWD_CNTL_SB_BUF_BASE 0 x2254#define regWD_CNTL_SB_BUF_BASE_BASE_IDX 1 #define regWD_CNTL_SB_BUF_BASE_HI 0 x2255#define regWD_CNTL_SB_BUF_BASE_HI_BASE_IDX 1 #define regWD_INDEX_BUF_BASE 0 x2256#define regWD_INDEX_BUF_BASE_BASE_IDX 1 #define regWD_INDEX_BUF_BASE_HI 0 x2257#define regWD_INDEX_BUF_BASE_HI_BASE_IDX 1 #define regIA_MULTI_VGT_PARAM 0 x2258#define regIA_MULTI_VGT_PARAM_BASE_IDX 1 #define regVGT_INSTANCE_BASE_ID 0 x225a#define regVGT_INSTANCE_BASE_ID_BASE_IDX 1 #define regPA_SU_LINE_STIPPLE_VALUE 0 x2280#define regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 #define regPA_SC_LINE_STIPPLE_STATE 0 x2281#define regPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 #define regPA_SC_SCREEN_EXTENT_MIN_0 0 x2284#define regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 #define regPA_SC_SCREEN_EXTENT_MAX_0 0 x2285#define regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 #define regPA_SC_SCREEN_EXTENT_MIN_1 0 x2286#define regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 #define regPA_SC_SCREEN_EXTENT_MAX_1 0 x228b#define regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 #define regPA_SC_P3D_TRAP_SCREEN_HV_EN 0 x22a0#define regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 #define regPA_SC_P3D_TRAP_SCREEN_H 0 x22a1#define regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 #define regPA_SC_P3D_TRAP_SCREEN_V 0 x22a2#define regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 #define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0 x22a3#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 #define regPA_SC_P3D_TRAP_SCREEN_COUNT 0 x22a4#define regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 #define regPA_SC_HP3D_TRAP_SCREEN_HV_EN 0 x22a8#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 #define regPA_SC_HP3D_TRAP_SCREEN_H 0 x22a9#define regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 #define regPA_SC_HP3D_TRAP_SCREEN_V 0 x22aa#define regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 #define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0 x22ab#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 #define regPA_SC_HP3D_TRAP_SCREEN_COUNT 0 x22ac#define regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 #define regPA_SC_TRAP_SCREEN_HV_EN 0 x22b0#define regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 #define regPA_SC_TRAP_SCREEN_H 0 x22b1#define regPA_SC_TRAP_SCREEN_H_BASE_IDX 1 #define regPA_SC_TRAP_SCREEN_V 0 x22b2#define regPA_SC_TRAP_SCREEN_V_BASE_IDX 1 #define regPA_SC_TRAP_SCREEN_OCCURRENCE 0 x22b3#define regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 #define regPA_SC_TRAP_SCREEN_COUNT 0 x22b4#define regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 #define regPA_STATE_STEREO_X 0 x22b5#define regPA_STATE_STEREO_X_BASE_IDX 1 #define regSQ_THREAD_TRACE_BASE 0 x2330#define regSQ_THREAD_TRACE_BASE_BASE_IDX 1 #define regSQ_THREAD_TRACE_SIZE 0 x2331#define regSQ_THREAD_TRACE_SIZE_BASE_IDX 1 #define regSQ_THREAD_TRACE_MASK 0 x2332#define regSQ_THREAD_TRACE_MASK_BASE_IDX 1 #define regSQ_THREAD_TRACE_TOKEN_MASK 0 x2333#define regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 #define regSQ_THREAD_TRACE_PERF_MASK 0 x2334#define regSQ_THREAD_TRACE_PERF_MASK_BASE_IDX 1 #define regSQ_THREAD_TRACE_CTRL 0 x2335#define regSQ_THREAD_TRACE_CTRL_BASE_IDX 1 #define regSQ_THREAD_TRACE_MODE 0 x2336#define regSQ_THREAD_TRACE_MODE_BASE_IDX 1 #define regSQ_THREAD_TRACE_BASE2 0 x2337#define regSQ_THREAD_TRACE_BASE2_BASE_IDX 1 #define regSQ_THREAD_TRACE_TOKEN_MASK2 0 x2338#define regSQ_THREAD_TRACE_TOKEN_MASK2_BASE_IDX 1 #define regSQ_THREAD_TRACE_WPTR 0 x2339#define regSQ_THREAD_TRACE_WPTR_BASE_IDX 1 #define regSQ_THREAD_TRACE_STATUS 0 x233a#define regSQ_THREAD_TRACE_STATUS_BASE_IDX 1 #define regSQ_THREAD_TRACE_HIWATER 0 x233b#define regSQ_THREAD_TRACE_HIWATER_BASE_IDX 1 #define regSQ_THREAD_TRACE_CNTR 0 x233c#define regSQ_THREAD_TRACE_CNTR_BASE_IDX 1 #define regSQ_THREAD_TRACE_USERDATA_0 0 x2340#define regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 #define regSQ_THREAD_TRACE_USERDATA_1 0 x2341#define regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 #define regSQ_THREAD_TRACE_USERDATA_2 0 x2342#define regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 #define regSQ_THREAD_TRACE_USERDATA_3 0 x2343#define regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 #define regSQC_CACHES 0 x2348#define regSQC_CACHES_BASE_IDX 1 #define regSQC_WRITEBACK 0 x2349#define regSQC_WRITEBACK_BASE_IDX 1 #define regDB_OCCLUSION_COUNT0_LOW 0 x23c0#define regDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 #define regDB_OCCLUSION_COUNT0_HI 0 x23c1#define regDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 #define regDB_OCCLUSION_COUNT1_LOW 0 x23c2#define regDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 #define regDB_OCCLUSION_COUNT1_HI 0 x23c3#define regDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 #define regDB_OCCLUSION_COUNT2_LOW 0 x23c4#define regDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 #define regDB_OCCLUSION_COUNT2_HI 0 x23c5#define regDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 #define regDB_OCCLUSION_COUNT3_LOW 0 x23c6#define regDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 #define regDB_OCCLUSION_COUNT3_HI 0 x23c7#define regDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 #define regDB_ZPASS_COUNT_LOW 0 x23fe#define regDB_ZPASS_COUNT_LOW_BASE_IDX 1 #define regDB_ZPASS_COUNT_HI 0 x23ff#define regDB_ZPASS_COUNT_HI_BASE_IDX 1 #define regGDS_RD_ADDR 0 x2400#define regGDS_RD_ADDR_BASE_IDX 1 #define regGDS_RD_DATA 0 x2401#define regGDS_RD_DATA_BASE_IDX 1 #define regGDS_RD_BURST_ADDR 0 x2402#define regGDS_RD_BURST_ADDR_BASE_IDX 1 #define regGDS_RD_BURST_COUNT 0 x2403#define regGDS_RD_BURST_COUNT_BASE_IDX 1 #define regGDS_RD_BURST_DATA 0 x2404#define regGDS_RD_BURST_DATA_BASE_IDX 1 #define regGDS_WR_ADDR 0 x2405#define regGDS_WR_ADDR_BASE_IDX 1 #define regGDS_WR_DATA 0 x2406#define regGDS_WR_DATA_BASE_IDX 1 #define regGDS_WR_BURST_ADDR 0 x2407#define regGDS_WR_BURST_ADDR_BASE_IDX 1 #define regGDS_WR_BURST_DATA 0 x2408#define regGDS_WR_BURST_DATA_BASE_IDX 1 #define regGDS_WRITE_COMPLETE 0 x2409#define regGDS_WRITE_COMPLETE_BASE_IDX 1 #define regGDS_ATOM_CNTL 0 x240a#define regGDS_ATOM_CNTL_BASE_IDX 1 #define regGDS_ATOM_COMPLETE 0 x240b#define regGDS_ATOM_COMPLETE_BASE_IDX 1 #define regGDS_ATOM_BASE 0 x240c#define regGDS_ATOM_BASE_BASE_IDX 1 #define regGDS_ATOM_SIZE 0 x240d#define regGDS_ATOM_SIZE_BASE_IDX 1 #define regGDS_ATOM_OFFSET0 0 x240e#define regGDS_ATOM_OFFSET0_BASE_IDX 1 #define regGDS_ATOM_OFFSET1 0 x240f#define regGDS_ATOM_OFFSET1_BASE_IDX 1 #define regGDS_ATOM_DST 0 x2410#define regGDS_ATOM_DST_BASE_IDX 1 #define regGDS_ATOM_OP 0 x2411#define regGDS_ATOM_OP_BASE_IDX 1 #define regGDS_ATOM_SRC0 0 x2412#define regGDS_ATOM_SRC0_BASE_IDX 1 #define regGDS_ATOM_SRC0_U 0 x2413#define regGDS_ATOM_SRC0_U_BASE_IDX 1 #define regGDS_ATOM_SRC1 0 x2414#define regGDS_ATOM_SRC1_BASE_IDX 1 #define regGDS_ATOM_SRC1_U 0 x2415#define regGDS_ATOM_SRC1_U_BASE_IDX 1 #define regGDS_ATOM_READ0 0 x2416#define regGDS_ATOM_READ0_BASE_IDX 1 #define regGDS_ATOM_READ0_U 0 x2417#define regGDS_ATOM_READ0_U_BASE_IDX 1 #define regGDS_ATOM_READ1 0 x2418#define regGDS_ATOM_READ1_BASE_IDX 1 #define regGDS_ATOM_READ1_U 0 x2419#define regGDS_ATOM_READ1_U_BASE_IDX 1 #define regGDS_GWS_RESOURCE_CNTL 0 x241a#define regGDS_GWS_RESOURCE_CNTL_BASE_IDX 1 #define regGDS_GWS_RESOURCE 0 x241b#define regGDS_GWS_RESOURCE_BASE_IDX 1 #define regGDS_GWS_RESOURCE_CNT 0 x241c#define regGDS_GWS_RESOURCE_CNT_BASE_IDX 1 #define regGDS_OA_CNTL 0 x241d#define regGDS_OA_CNTL_BASE_IDX 1 #define regGDS_OA_COUNTER 0 x241e#define regGDS_OA_COUNTER_BASE_IDX 1 #define regGDS_OA_ADDRESS 0 x241f#define regGDS_OA_ADDRESS_BASE_IDX 1 #define regGDS_OA_INCDEC 0 x2420#define regGDS_OA_INCDEC_BASE_IDX 1 #define regGDS_OA_RING_SIZE 0 x2421#define regGDS_OA_RING_SIZE_BASE_IDX 1 #define regSPI_CONFIG_CNTL 0 x2440#define regSPI_CONFIG_CNTL_BASE_IDX 1 #define regSPI_CONFIG_CNTL_1 0 x2441#define regSPI_CONFIG_CNTL_1_BASE_IDX 1 #define regSPI_CONFIG_CNTL_2 0 x2442#define regSPI_CONFIG_CNTL_2_BASE_IDX 1 #define regSPI_WAVE_LIMIT_CNTL 0 x2443#define regSPI_WAVE_LIMIT_CNTL_BASE_IDX 1 // addressBlock: gc_grbmdec // base address: 0x8000 #define regGRBM_CNTL 0 x0000#define regGRBM_CNTL_BASE_IDX 0 #define regGRBM_SKEW_CNTL 0 x0001#define regGRBM_SKEW_CNTL_BASE_IDX 0 #define regGRBM_STATUS2 0 x0002#define regGRBM_STATUS2_BASE_IDX 0 #define regGRBM_PWR_CNTL 0 x0003#define regGRBM_PWR_CNTL_BASE_IDX 0 #define regGRBM_STATUS 0 x0004#define regGRBM_STATUS_BASE_IDX 0 #define regGRBM_STATUS_SE0 0 x0005#define regGRBM_STATUS_SE0_BASE_IDX 0 #define regGRBM_STATUS_SE1 0 x0006#define regGRBM_STATUS_SE1_BASE_IDX 0 #define regGRBM_SOFT_RESET 0 x0008#define regGRBM_SOFT_RESET_BASE_IDX 0 #define regGRBM_GFX_CLKEN_CNTL 0 x000c#define regGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 #define regGRBM_WAIT_IDLE_CLOCKS 0 x000d#define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 #define regGRBM_STATUS_SE2 0 x000e#define regGRBM_STATUS_SE2_BASE_IDX 0 #define regGRBM_STATUS_SE3 0 x000f#define regGRBM_STATUS_SE3_BASE_IDX 0 #define regGRBM_READ_ERROR 0 x0016#define regGRBM_READ_ERROR_BASE_IDX 0 #define regGRBM_READ_ERROR2 0 x0017#define regGRBM_READ_ERROR2_BASE_IDX 0 #define regGRBM_INT_CNTL 0 x0018#define regGRBM_INT_CNTL_BASE_IDX 0 #define regGRBM_TRAP_OP 0 x0019#define regGRBM_TRAP_OP_BASE_IDX 0 #define regGRBM_TRAP_ADDR 0 x001a#define regGRBM_TRAP_ADDR_BASE_IDX 0 #define regGRBM_TRAP_ADDR_MSK 0 x001b#define regGRBM_TRAP_ADDR_MSK_BASE_IDX 0 #define regGRBM_TRAP_WD 0 x001c#define regGRBM_TRAP_WD_BASE_IDX 0 #define regGRBM_TRAP_WD_MSK 0 x001d#define regGRBM_TRAP_WD_MSK_BASE_IDX 0 #define regGRBM_WRITE_ERROR 0 x001f#define regGRBM_WRITE_ERROR_BASE_IDX 0 #define regGRBM_CHIP_REVISION 0 x0021#define regGRBM_CHIP_REVISION_BASE_IDX 0 #define regGRBM_GFX_CNTL 0 x0022#define regGRBM_GFX_CNTL_BASE_IDX 0 #define regGRBM_IH_CREDIT 0 x0024#define regGRBM_IH_CREDIT_BASE_IDX 0 #define regGRBM_PWR_CNTL2 0 x0025#define regGRBM_PWR_CNTL2_BASE_IDX 0 #define regGRBM_UTCL2_INVAL_RANGE_START 0 x0026#define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 #define regGRBM_UTCL2_INVAL_RANGE_END 0 x0027#define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 #define regGRBM_CHICKEN_BITS 0 x0029#define regGRBM_CHICKEN_BITS_BASE_IDX 0 #define regGRBM_FENCE_RANGE0 0 x002a#define regGRBM_FENCE_RANGE0_BASE_IDX 0 #define regGRBM_FENCE_RANGE1 0 x002b#define regGRBM_FENCE_RANGE1_BASE_IDX 0 #define regGRBM_NOWHERE 0 x003f#define regGRBM_NOWHERE_BASE_IDX 0 #define regGRBM_SCRATCH_REG0 0 x0040#define regGRBM_SCRATCH_REG0_BASE_IDX 0 #define regGRBM_SCRATCH_REG1 0 x0041#define regGRBM_SCRATCH_REG1_BASE_IDX 0 #define regGRBM_SCRATCH_REG2 0 x0042#define regGRBM_SCRATCH_REG2_BASE_IDX 0 #define regGRBM_SCRATCH_REG3 0 x0043#define regGRBM_SCRATCH_REG3_BASE_IDX 0 #define regGRBM_SCRATCH_REG4 0 x0044#define regGRBM_SCRATCH_REG4_BASE_IDX 0 #define regGRBM_SCRATCH_REG5 0 x0045#define regGRBM_SCRATCH_REG5_BASE_IDX 0 #define regGRBM_SCRATCH_REG6 0 x0046#define regGRBM_SCRATCH_REG6_BASE_IDX 0 #define regGRBM_SCRATCH_REG7 0 x0047#define regGRBM_SCRATCH_REG7_BASE_IDX 0 #define regVIOLATION_DATA_ASYNC_VF_PROG 0 x0048#define regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX 0 // addressBlock: gc_hypdec // base address: 0x3e000 #define regCP_HYP_PFP_UCODE_ADDR 0 x5814#define regCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 #define regCP_PFP_UCODE_ADDR 0 x5814#define regCP_PFP_UCODE_ADDR_BASE_IDX 1 #define regCP_HYP_PFP_UCODE_DATA 0 x5815#define regCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 #define regCP_PFP_UCODE_DATA 0 x5815#define regCP_PFP_UCODE_DATA_BASE_IDX 1 #define regCP_HYP_ME_UCODE_ADDR 0 x5816#define regCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 #define regCP_ME_RAM_RADDR 0 x5816#define regCP_ME_RAM_RADDR_BASE_IDX 1 #define regCP_ME_RAM_WADDR 0 x5816#define regCP_ME_RAM_WADDR_BASE_IDX 1 #define regCP_HYP_ME_UCODE_DATA 0 x5817#define regCP_HYP_ME_UCODE_DATA_BASE_IDX 1 #define regCP_ME_RAM_DATA 0 x5817#define regCP_ME_RAM_DATA_BASE_IDX 1 #define regCP_CE_UCODE_ADDR 0 x5818#define regCP_CE_UCODE_ADDR_BASE_IDX 1 #define regCP_HYP_CE_UCODE_ADDR 0 x5818#define regCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 #define regCP_CE_UCODE_DATA 0 x5819#define regCP_CE_UCODE_DATA_BASE_IDX 1 #define regCP_HYP_CE_UCODE_DATA 0 x5819#define regCP_HYP_CE_UCODE_DATA_BASE_IDX 1 #define regCP_HYP_MEC1_UCODE_ADDR 0 x581a#define regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 #define regCP_MEC_ME1_UCODE_ADDR 0 x581a#define regCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 #define regCP_HYP_MEC1_UCODE_DATA 0 x581b#define regCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 #define regCP_MEC_ME1_UCODE_DATA 0 x581b#define regCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 #define regCP_HYP_MEC2_UCODE_ADDR 0 x581c#define regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX 1 #define regCP_MEC_ME2_UCODE_ADDR 0 x581c#define regCP_MEC_ME2_UCODE_ADDR_BASE_IDX 1 #define regCP_HYP_MEC2_UCODE_DATA 0 x581d#define regCP_HYP_MEC2_UCODE_DATA_BASE_IDX 1 #define regCP_MEC_ME2_UCODE_DATA 0 x581d#define regCP_MEC_ME2_UCODE_DATA_BASE_IDX 1 #define regRLC_GPM_UCODE_ADDR 0 x583c#define regRLC_GPM_UCODE_ADDR_BASE_IDX 1 #define regRLC_GPM_UCODE_DATA 0 x583d#define regRLC_GPM_UCODE_DATA_BASE_IDX 1 #define regGRBM_GFX_INDEX_SR_SELECT 0 x5a00#define regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 #define regGRBM_GFX_INDEX_SR_DATA 0 x5a01#define regGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 #define regGRBM_GFX_CNTL_SR_SELECT 0 x5a02#define regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 #define regGRBM_GFX_CNTL_SR_DATA 0 x5a03#define regGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 #define regGRBM_CAM_INDEX 0 x5a04#define regGRBM_CAM_INDEX_BASE_IDX 1 #define regGRBM_HYP_CAM_INDEX 0 x5a04#define regGRBM_HYP_CAM_INDEX_BASE_IDX 1 #define regGRBM_CAM_DATA 0 x5a05#define regGRBM_CAM_DATA_BASE_IDX 1 #define regGRBM_HYP_CAM_DATA 0 x5a05#define regGRBM_HYP_CAM_DATA_BASE_IDX 1 #define regRLC_GPU_IOV_VF_ENABLE 0 x5b00#define regRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 #define regRLC_GPU_IOV_CFG_REG6 0 x5b06#define regRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 #define regRLC_GPU_IOV_CFG_REG8 0 x5b20#define regRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 #define regRLC_RLCV_TIMER_INT_0 0 x5b25#define regRLC_RLCV_TIMER_INT_0_BASE_IDX 1 #define regRLC_RLCV_TIMER_CTRL 0 x5b26#define regRLC_RLCV_TIMER_CTRL_BASE_IDX 1 #define regRLC_RLCV_TIMER_STAT 0 x5b27#define regRLC_RLCV_TIMER_STAT_BASE_IDX 1 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS 0 x5b2a#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0 x5b2b#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0 x5b2c#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 #define regRLC_GPU_IOV_VF_MASK 0 x5b2d#define regRLC_GPU_IOV_VF_MASK_BASE_IDX 1 #define regRLC_HYP_SEMAPHORE_0 0 x5b2e#define regRLC_HYP_SEMAPHORE_0_BASE_IDX 1 #define regRLC_HYP_SEMAPHORE_1 0 x5b2f#define regRLC_HYP_SEMAPHORE_1_BASE_IDX 1 #define regRLC_CLK_CNTL 0 x5b31#define regRLC_CLK_CNTL_BASE_IDX 1 #define regRLC_GPU_IOV_SCH_BLOCK 0 x5b34#define regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 #define regRLC_GPU_IOV_CFG_REG1 0 x5b35#define regRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 #define regRLC_GPU_IOV_CFG_REG2 0 x5b36#define regRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 #define regRLC_GPU_IOV_VM_BUSY_STATUS 0 x5b37#define regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_SCH_0 0 x5b38#define regRLC_GPU_IOV_SCH_0_BASE_IDX 1 #define regRLC_GPU_IOV_ACTIVE_FCN_ID 0 x5b39#define regRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1 #define regRLC_GPU_IOV_SCH_3 0 x5b3a#define regRLC_GPU_IOV_SCH_3_BASE_IDX 1 #define regRLC_GPU_IOV_SCH_1 0 x5b3b#define regRLC_GPU_IOV_SCH_1_BASE_IDX 1 #define regRLC_GPU_IOV_SCH_2 0 x5b3c#define regRLC_GPU_IOV_SCH_2_BASE_IDX 1 #define regRLC_GPU_IOV_INT_STAT 0 x5b3f#define regRLC_GPU_IOV_INT_STAT_BASE_IDX 1 #define regRLC_RLCV_TIMER_INT_1 0 x5b40#define regRLC_RLCV_TIMER_INT_1_BASE_IDX 1 #define regRLC_GPU_IOV_UCODE_ADDR 0 x5b42#define regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX 1 #define regRLC_GPU_IOV_UCODE_DATA 0 x5b43#define regRLC_GPU_IOV_UCODE_DATA_BASE_IDX 1 #define regRLC_GPU_IOV_SCRATCH_ADDR 0 x5b44#define regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX 1 #define regRLC_GPU_IOV_SCRATCH_DATA 0 x5b45#define regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX 1 #define regRLC_GPU_IOV_F32_CNTL 0 x5b46#define regRLC_GPU_IOV_F32_CNTL_BASE_IDX 1 #define regRLC_GPU_IOV_F32_RESET 0 x5b47#define regRLC_GPU_IOV_F32_RESET_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA0_STATUS 0 x5b48#define regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA1_STATUS 0 x5b49#define regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_VIRT_RESET_REQ 0 x5b4c#define regRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1 #define regRLC_GPU_IOV_RLC_RESPONSE 0 x5b4d#define regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 #define regRLC_GPU_IOV_INT_DISABLE 0 x5b4e#define regRLC_GPU_IOV_INT_DISABLE_BASE_IDX 1 #define regRLC_GPU_IOV_INT_FORCE 0 x5b4f#define regRLC_GPU_IOV_INT_FORCE_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA0_BUSY_STATUS 0 x5b50#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA1_BUSY_STATUS 0 x5b51#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 #define regRLC_HYP_SEMAPHORE_2 0 x5b52#define regRLC_HYP_SEMAPHORE_2_BASE_IDX 1 #define regRLC_HYP_SEMAPHORE_3 0 x5b53#define regRLC_HYP_SEMAPHORE_3_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA2_STATUS 0 x5b54#define regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA3_STATUS 0 x5b55#define regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA4_STATUS 0 x5b56#define regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA5_STATUS 0 x5b57#define regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA6_STATUS 0 x5b58#define regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA7_STATUS 0 x5b59#define regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA2_BUSY_STATUS 0 x5b5a#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA3_BUSY_STATUS 0 x5b5b#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA4_BUSY_STATUS 0 x5b5c#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA5_BUSY_STATUS 0 x5b5d#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA6_BUSY_STATUS 0 x5b5e#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX 1 #define regRLC_GPU_IOV_SDMA7_BUSY_STATUS 0 x5b5f#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX 1 // addressBlock: gc_padec // base address: 0x8800 #define regVGT_VTX_VECT_EJECT_REG 0 x022c#define regVGT_VTX_VECT_EJECT_REG_BASE_IDX 0 #define regVGT_DMA_DATA_FIFO_DEPTH 0 x022d#define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 #define regVGT_DMA_REQ_FIFO_DEPTH 0 x022e#define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 #define regVGT_DRAW_INIT_FIFO_DEPTH 0 x022f#define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 #define regVGT_LAST_COPY_STATE 0 x0230#define regVGT_LAST_COPY_STATE_BASE_IDX 0 #define regVGT_CACHE_INVALIDATION 0 x0231#define regVGT_CACHE_INVALIDATION_BASE_IDX 0 #define regVGT_STRMOUT_DELAY 0 x0233#define regVGT_STRMOUT_DELAY_BASE_IDX 0 #define regVGT_FIFO_DEPTHS 0 x0234#define regVGT_FIFO_DEPTHS_BASE_IDX 0 #define regVGT_GS_VERTEX_REUSE 0 x0235#define regVGT_GS_VERTEX_REUSE_BASE_IDX 0 #define regVGT_MC_LAT_CNTL 0 x0236#define regVGT_MC_LAT_CNTL_BASE_IDX 0 #define regIA_CNTL_STATUS 0 x0237#define regIA_CNTL_STATUS_BASE_IDX 0 #define regVGT_CNTL_STATUS 0 x023c#define regVGT_CNTL_STATUS_BASE_IDX 0 #define regWD_CNTL_STATUS 0 x023f#define regWD_CNTL_STATUS_BASE_IDX 0 #define regCC_GC_PRIM_CONFIG 0 x0240#define regCC_GC_PRIM_CONFIG_BASE_IDX 0 #define regGC_USER_PRIM_CONFIG 0 x0241#define regGC_USER_PRIM_CONFIG_BASE_IDX 0 #define regWD_QOS 0 x0242#define regWD_QOS_BASE_IDX 0 #define regWD_UTCL1_CNTL 0 x0243#define regWD_UTCL1_CNTL_BASE_IDX 0 #define regWD_UTCL1_STATUS 0 x0244#define regWD_UTCL1_STATUS_BASE_IDX 0 #define regIA_UTCL1_CNTL 0 x0246#define regIA_UTCL1_CNTL_BASE_IDX 0 #define regIA_UTCL1_STATUS 0 x0247#define regIA_UTCL1_STATUS_BASE_IDX 0 #define regVGT_SYS_CONFIG 0 x0263#define regVGT_SYS_CONFIG_BASE_IDX 0 #define regVGT_VS_MAX_WAVE_ID 0 x0268#define regVGT_VS_MAX_WAVE_ID_BASE_IDX 0 #define regVGT_GS_MAX_WAVE_ID 0 x0269#define regVGT_GS_MAX_WAVE_ID_BASE_IDX 0 #define regGFX_PIPE_CONTROL 0 x026d#define regGFX_PIPE_CONTROL_BASE_IDX 0 #define regCC_GC_SHADER_ARRAY_CONFIG 0 x026f#define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 #define regGC_USER_SHADER_ARRAY_CONFIG 0 x0270#define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0 #define regVGT_DMA_PRIMITIVE_TYPE 0 x0271#define regVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0 #define regVGT_DMA_CONTROL 0 x0272#define regVGT_DMA_CONTROL_BASE_IDX 0 #define regVGT_DMA_LS_HS_CONFIG 0 x0273#define regVGT_DMA_LS_HS_CONFIG_BASE_IDX 0 #define regWD_BUF_RESOURCE_1 0 x0276#define regWD_BUF_RESOURCE_1_BASE_IDX 0 #define regWD_BUF_RESOURCE_2 0 x0277#define regWD_BUF_RESOURCE_2_BASE_IDX 0 #define regPA_CL_CNTL_STATUS 0 x0284#define regPA_CL_CNTL_STATUS_BASE_IDX 0 #define regPA_CL_ENHANCE 0 x0285#define regPA_CL_ENHANCE_BASE_IDX 0 #define regPA_SU_CNTL_STATUS 0 x0294#define regPA_SU_CNTL_STATUS_BASE_IDX 0 #define regPA_SC_FIFO_DEPTH_CNTL 0 x0295#define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 #define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0 x02c0#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 #define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0 x02c1#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 #define regPA_SC_TRAP_SCREEN_HV_LOCK 0 x02c2#define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0 #define regPA_SC_FORCE_EOV_MAX_CNTS 0 x02c9#define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0 #define regPA_SC_BINNER_EVENT_CNTL_0 0 x02cc#define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0 #define regPA_SC_BINNER_EVENT_CNTL_1 0 x02cd#define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0 #define regPA_SC_BINNER_EVENT_CNTL_2 0 x02ce#define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0 #define regPA_SC_BINNER_EVENT_CNTL_3 0 x02cf#define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0 #define regPA_SC_BINNER_TIMEOUT_COUNTER 0 x02d0#define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0 #define regPA_SC_BINNER_PERF_CNTL_0 0 x02d1#define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0 #define regPA_SC_BINNER_PERF_CNTL_1 0 x02d2#define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0 #define regPA_SC_BINNER_PERF_CNTL_2 0 x02d3#define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0 #define regPA_SC_BINNER_PERF_CNTL_3 0 x02d4#define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0 #define regPA_SC_ENHANCE_2 0 x02dc#define regPA_SC_ENHANCE_2_BASE_IDX 0 #define regPA_SC_FIFO_SIZE 0 x02f3#define regPA_SC_FIFO_SIZE_BASE_IDX 0 #define regPA_SC_IF_FIFO_SIZE 0 x02f5#define regPA_SC_IF_FIFO_SIZE_BASE_IDX 0 #define regPA_SC_PKR_WAVE_TABLE_CNTL 0 x02f8#define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0 #define regPA_UTCL1_CNTL1 0 x02f9#define regPA_UTCL1_CNTL1_BASE_IDX 0 #define regPA_UTCL1_CNTL2 0 x02fa#define regPA_UTCL1_CNTL2_BASE_IDX 0 #define regPA_SIDEBAND_REQUEST_DELAYS 0 x02fb#define regPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0 #define regPA_SC_ENHANCE 0 x02fc#define regPA_SC_ENHANCE_BASE_IDX 0 #define regPA_SC_ENHANCE_1 0 x02fd#define regPA_SC_ENHANCE_1_BASE_IDX 0 #define regPA_SC_DSM_CNTL 0 x02fe#define regPA_SC_DSM_CNTL_BASE_IDX 0 #define regPA_SC_TILE_STEERING_CREST_OVERRIDE 0 x02ff#define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0 // addressBlock: gc_perfddec // base address: 0x34000 #define regCPG_PERFCOUNTER1_LO 0 x3000#define regCPG_PERFCOUNTER1_LO_BASE_IDX 1 #define regCPG_PERFCOUNTER1_HI 0 x3001#define regCPG_PERFCOUNTER1_HI_BASE_IDX 1 #define regCPG_PERFCOUNTER0_LO 0 x3002#define regCPG_PERFCOUNTER0_LO_BASE_IDX 1 #define regCPG_PERFCOUNTER0_HI 0 x3003#define regCPG_PERFCOUNTER0_HI_BASE_IDX 1 #define regCPC_PERFCOUNTER1_LO 0 x3004#define regCPC_PERFCOUNTER1_LO_BASE_IDX 1 #define regCPC_PERFCOUNTER1_HI 0 x3005#define regCPC_PERFCOUNTER1_HI_BASE_IDX 1 #define regCPC_PERFCOUNTER0_LO 0 x3006#define regCPC_PERFCOUNTER0_LO_BASE_IDX 1 #define regCPC_PERFCOUNTER0_HI 0 x3007#define regCPC_PERFCOUNTER0_HI_BASE_IDX 1 #define regCPF_PERFCOUNTER1_LO 0 x3008#define regCPF_PERFCOUNTER1_LO_BASE_IDX 1 #define regCPF_PERFCOUNTER1_HI 0 x3009#define regCPF_PERFCOUNTER1_HI_BASE_IDX 1 #define regCPF_PERFCOUNTER0_LO 0 x300a#define regCPF_PERFCOUNTER0_LO_BASE_IDX 1 #define regCPF_PERFCOUNTER0_HI 0 x300b#define regCPF_PERFCOUNTER0_HI_BASE_IDX 1 #define regCPF_LATENCY_STATS_DATA 0 x300c#define regCPF_LATENCY_STATS_DATA_BASE_IDX 1 #define regCPG_LATENCY_STATS_DATA 0 x300d#define regCPG_LATENCY_STATS_DATA_BASE_IDX 1 #define regCPC_LATENCY_STATS_DATA 0 x300e#define regCPC_LATENCY_STATS_DATA_BASE_IDX 1 #define regGRBM_PERFCOUNTER0_LO 0 x3040#define regGRBM_PERFCOUNTER0_LO_BASE_IDX 1 #define regGRBM_PERFCOUNTER0_HI 0 x3041#define regGRBM_PERFCOUNTER0_HI_BASE_IDX 1 #define regGRBM_PERFCOUNTER1_LO 0 x3043#define regGRBM_PERFCOUNTER1_LO_BASE_IDX 1 #define regGRBM_PERFCOUNTER1_HI 0 x3044#define regGRBM_PERFCOUNTER1_HI_BASE_IDX 1 #define regGRBM_SE0_PERFCOUNTER_LO 0 x3045#define regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX 1 #define regGRBM_SE0_PERFCOUNTER_HI 0 x3046#define regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX 1 #define regGRBM_SE1_PERFCOUNTER_LO 0 x3047#define regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX 1 #define regGRBM_SE1_PERFCOUNTER_HI 0 x3048#define regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX 1 #define regGRBM_SE2_PERFCOUNTER_LO 0 x3049#define regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX 1 #define regGRBM_SE2_PERFCOUNTER_HI 0 x304a#define regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX 1 #define regGRBM_SE3_PERFCOUNTER_LO 0 x304b#define regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX 1 #define regGRBM_SE3_PERFCOUNTER_HI 0 x304c#define regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX 1 #define regWD_PERFCOUNTER0_LO 0 x3080#define regWD_PERFCOUNTER0_LO_BASE_IDX 1 #define regWD_PERFCOUNTER0_HI 0 x3081#define regWD_PERFCOUNTER0_HI_BASE_IDX 1 #define regWD_PERFCOUNTER1_LO 0 x3082#define regWD_PERFCOUNTER1_LO_BASE_IDX 1 #define regWD_PERFCOUNTER1_HI 0 x3083#define regWD_PERFCOUNTER1_HI_BASE_IDX 1 #define regWD_PERFCOUNTER2_LO 0 x3084#define regWD_PERFCOUNTER2_LO_BASE_IDX 1 #define regWD_PERFCOUNTER2_HI 0 x3085#define regWD_PERFCOUNTER2_HI_BASE_IDX 1 #define regWD_PERFCOUNTER3_LO 0 x3086#define regWD_PERFCOUNTER3_LO_BASE_IDX 1 #define regWD_PERFCOUNTER3_HI 0 x3087#define regWD_PERFCOUNTER3_HI_BASE_IDX 1 #define regIA_PERFCOUNTER0_LO 0 x3088#define regIA_PERFCOUNTER0_LO_BASE_IDX 1 #define regIA_PERFCOUNTER0_HI 0 x3089#define regIA_PERFCOUNTER0_HI_BASE_IDX 1 #define regIA_PERFCOUNTER1_LO 0 x308a#define regIA_PERFCOUNTER1_LO_BASE_IDX 1 #define regIA_PERFCOUNTER1_HI 0 x308b#define regIA_PERFCOUNTER1_HI_BASE_IDX 1 #define regIA_PERFCOUNTER2_LO 0 x308c#define regIA_PERFCOUNTER2_LO_BASE_IDX 1 #define regIA_PERFCOUNTER2_HI 0 x308d#define regIA_PERFCOUNTER2_HI_BASE_IDX 1 #define regIA_PERFCOUNTER3_LO 0 x308e#define regIA_PERFCOUNTER3_LO_BASE_IDX 1 #define regIA_PERFCOUNTER3_HI 0 x308f#define regIA_PERFCOUNTER3_HI_BASE_IDX 1 #define regVGT_PERFCOUNTER0_LO 0 x3090#define regVGT_PERFCOUNTER0_LO_BASE_IDX 1 #define regVGT_PERFCOUNTER0_HI 0 x3091#define regVGT_PERFCOUNTER0_HI_BASE_IDX 1 #define regVGT_PERFCOUNTER1_LO 0 x3092#define regVGT_PERFCOUNTER1_LO_BASE_IDX 1 #define regVGT_PERFCOUNTER1_HI 0 x3093#define regVGT_PERFCOUNTER1_HI_BASE_IDX 1 #define regVGT_PERFCOUNTER2_LO 0 x3094#define regVGT_PERFCOUNTER2_LO_BASE_IDX 1 #define regVGT_PERFCOUNTER2_HI 0 x3095#define regVGT_PERFCOUNTER2_HI_BASE_IDX 1 #define regVGT_PERFCOUNTER3_LO 0 x3096#define regVGT_PERFCOUNTER3_LO_BASE_IDX 1 #define regVGT_PERFCOUNTER3_HI 0 x3097#define regVGT_PERFCOUNTER3_HI_BASE_IDX 1 #define regPA_SU_PERFCOUNTER0_LO 0 x3100#define regPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 #define regPA_SU_PERFCOUNTER0_HI 0 x3101#define regPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 #define regPA_SU_PERFCOUNTER1_LO 0 x3102#define regPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 #define regPA_SU_PERFCOUNTER1_HI 0 x3103#define regPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 #define regPA_SU_PERFCOUNTER2_LO 0 x3104#define regPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 #define regPA_SU_PERFCOUNTER2_HI 0 x3105#define regPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 #define regPA_SU_PERFCOUNTER3_LO 0 x3106#define regPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 #define regPA_SU_PERFCOUNTER3_HI 0 x3107#define regPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 #define regPA_SC_PERFCOUNTER0_LO 0 x3140#define regPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 #define regPA_SC_PERFCOUNTER0_HI 0 x3141#define regPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 #define regPA_SC_PERFCOUNTER1_LO 0 x3142#define regPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 #define regPA_SC_PERFCOUNTER1_HI 0 x3143#define regPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 #define regPA_SC_PERFCOUNTER2_LO 0 x3144#define regPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 #define regPA_SC_PERFCOUNTER2_HI 0 x3145#define regPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 #define regPA_SC_PERFCOUNTER3_LO 0 x3146#define regPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 #define regPA_SC_PERFCOUNTER3_HI 0 x3147#define regPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 #define regPA_SC_PERFCOUNTER4_LO 0 x3148#define regPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 #define regPA_SC_PERFCOUNTER4_HI 0 x3149#define regPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 #define regPA_SC_PERFCOUNTER5_LO 0 x314a#define regPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 #define regPA_SC_PERFCOUNTER5_HI 0 x314b#define regPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 #define regPA_SC_PERFCOUNTER6_LO 0 x314c#define regPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 #define regPA_SC_PERFCOUNTER6_HI 0 x314d#define regPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 #define regPA_SC_PERFCOUNTER7_LO 0 x314e#define regPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 #define regPA_SC_PERFCOUNTER7_HI 0 x314f#define regPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 #define regSPI_PERFCOUNTER0_HI 0 x3180#define regSPI_PERFCOUNTER0_HI_BASE_IDX 1 #define regSPI_PERFCOUNTER0_LO 0 x3181#define regSPI_PERFCOUNTER0_LO_BASE_IDX 1 #define regSPI_PERFCOUNTER1_HI 0 x3182#define regSPI_PERFCOUNTER1_HI_BASE_IDX 1 #define regSPI_PERFCOUNTER1_LO 0 x3183#define regSPI_PERFCOUNTER1_LO_BASE_IDX 1 #define regSPI_PERFCOUNTER2_HI 0 x3184#define regSPI_PERFCOUNTER2_HI_BASE_IDX 1 #define regSPI_PERFCOUNTER2_LO 0 x3185#define regSPI_PERFCOUNTER2_LO_BASE_IDX 1 #define regSPI_PERFCOUNTER3_HI 0 x3186#define regSPI_PERFCOUNTER3_HI_BASE_IDX 1 #define regSPI_PERFCOUNTER3_LO 0 x3187#define regSPI_PERFCOUNTER3_LO_BASE_IDX 1 #define regSPI_PERFCOUNTER4_HI 0 x3188#define regSPI_PERFCOUNTER4_HI_BASE_IDX 1 #define regSPI_PERFCOUNTER4_LO 0 x3189#define regSPI_PERFCOUNTER4_LO_BASE_IDX 1 #define regSPI_PERFCOUNTER5_HI 0 x318a#define regSPI_PERFCOUNTER5_HI_BASE_IDX 1 #define regSPI_PERFCOUNTER5_LO 0 x318b#define regSPI_PERFCOUNTER5_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER0_LO 0 x31c0#define regSQ_PERFCOUNTER0_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER0_HI 0 x31c1#define regSQ_PERFCOUNTER0_HI_BASE_IDX 1 #define regSQ_PERFCOUNTER1_LO 0 x31c2#define regSQ_PERFCOUNTER1_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER1_HI 0 x31c3#define regSQ_PERFCOUNTER1_HI_BASE_IDX 1 #define regSQ_PERFCOUNTER2_LO 0 x31c4#define regSQ_PERFCOUNTER2_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER2_HI 0 x31c5#define regSQ_PERFCOUNTER2_HI_BASE_IDX 1 #define regSQ_PERFCOUNTER3_LO 0 x31c6#define regSQ_PERFCOUNTER3_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER3_HI 0 x31c7#define regSQ_PERFCOUNTER3_HI_BASE_IDX 1 #define regSQ_PERFCOUNTER4_LO 0 x31c8#define regSQ_PERFCOUNTER4_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER4_HI 0 x31c9#define regSQ_PERFCOUNTER4_HI_BASE_IDX 1 #define regSQ_PERFCOUNTER5_LO 0 x31ca#define regSQ_PERFCOUNTER5_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER5_HI 0 x31cb#define regSQ_PERFCOUNTER5_HI_BASE_IDX 1 #define regSQ_PERFCOUNTER6_LO 0 x31cc#define regSQ_PERFCOUNTER6_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER6_HI 0 x31cd#define regSQ_PERFCOUNTER6_HI_BASE_IDX 1 #define regSQ_PERFCOUNTER7_LO 0 x31ce#define regSQ_PERFCOUNTER7_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER7_HI 0 x31cf#define regSQ_PERFCOUNTER7_HI_BASE_IDX 1 #define regSQ_PERFCOUNTER8_LO 0 x31d0#define regSQ_PERFCOUNTER8_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER8_HI 0 x31d1#define regSQ_PERFCOUNTER8_HI_BASE_IDX 1 #define regSQ_PERFCOUNTER9_LO 0 x31d2#define regSQ_PERFCOUNTER9_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER9_HI 0 x31d3#define regSQ_PERFCOUNTER9_HI_BASE_IDX 1 #define regSQ_PERFCOUNTER10_LO 0 x31d4#define regSQ_PERFCOUNTER10_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER10_HI 0 x31d5#define regSQ_PERFCOUNTER10_HI_BASE_IDX 1 #define regSQ_PERFCOUNTER11_LO 0 x31d6#define regSQ_PERFCOUNTER11_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER11_HI 0 x31d7#define regSQ_PERFCOUNTER11_HI_BASE_IDX 1 #define regSQ_PERFCOUNTER12_LO 0 x31d8#define regSQ_PERFCOUNTER12_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER12_HI 0 x31d9#define regSQ_PERFCOUNTER12_HI_BASE_IDX 1 #define regSQ_PERFCOUNTER13_LO 0 x31da#define regSQ_PERFCOUNTER13_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER13_HI 0 x31db#define regSQ_PERFCOUNTER13_HI_BASE_IDX 1 #define regSQ_PERFCOUNTER14_LO 0 x31dc#define regSQ_PERFCOUNTER14_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER14_HI 0 x31dd#define regSQ_PERFCOUNTER14_HI_BASE_IDX 1 #define regSQ_PERFCOUNTER15_LO 0 x31de#define regSQ_PERFCOUNTER15_LO_BASE_IDX 1 #define regSQ_PERFCOUNTER15_HI 0 x31df#define regSQ_PERFCOUNTER15_HI_BASE_IDX 1 #define regSX_PERFCOUNTER0_LO 0 x3240#define regSX_PERFCOUNTER0_LO_BASE_IDX 1 #define regSX_PERFCOUNTER0_HI 0 x3241#define regSX_PERFCOUNTER0_HI_BASE_IDX 1 #define regSX_PERFCOUNTER1_LO 0 x3242#define regSX_PERFCOUNTER1_LO_BASE_IDX 1 #define regSX_PERFCOUNTER1_HI 0 x3243#define regSX_PERFCOUNTER1_HI_BASE_IDX 1 #define regSX_PERFCOUNTER2_LO 0 x3244#define regSX_PERFCOUNTER2_LO_BASE_IDX 1 #define regSX_PERFCOUNTER2_HI 0 x3245#define regSX_PERFCOUNTER2_HI_BASE_IDX 1 #define regSX_PERFCOUNTER3_LO 0 x3246#define regSX_PERFCOUNTER3_LO_BASE_IDX 1 #define regSX_PERFCOUNTER3_HI 0 x3247#define regSX_PERFCOUNTER3_HI_BASE_IDX 1 #define regGDS_PERFCOUNTER0_LO 0 x3280#define regGDS_PERFCOUNTER0_LO_BASE_IDX 1 #define regGDS_PERFCOUNTER0_HI 0 x3281#define regGDS_PERFCOUNTER0_HI_BASE_IDX 1 #define regGDS_PERFCOUNTER1_LO 0 x3282#define regGDS_PERFCOUNTER1_LO_BASE_IDX 1 #define regGDS_PERFCOUNTER1_HI 0 x3283#define regGDS_PERFCOUNTER1_HI_BASE_IDX 1 #define regGDS_PERFCOUNTER2_LO 0 x3284#define regGDS_PERFCOUNTER2_LO_BASE_IDX 1 #define regGDS_PERFCOUNTER2_HI 0 x3285#define regGDS_PERFCOUNTER2_HI_BASE_IDX 1 #define regGDS_PERFCOUNTER3_LO 0 x3286#define regGDS_PERFCOUNTER3_LO_BASE_IDX 1 #define regGDS_PERFCOUNTER3_HI 0 x3287#define regGDS_PERFCOUNTER3_HI_BASE_IDX 1 #define regTA_PERFCOUNTER0_LO 0 x32c0#define regTA_PERFCOUNTER0_LO_BASE_IDX 1 #define regTA_PERFCOUNTER0_HI 0 x32c1#define regTA_PERFCOUNTER0_HI_BASE_IDX 1 #define regTA_PERFCOUNTER1_LO 0 x32c2#define regTA_PERFCOUNTER1_LO_BASE_IDX 1 #define regTA_PERFCOUNTER1_HI 0 x32c3#define regTA_PERFCOUNTER1_HI_BASE_IDX 1 #define regTD_PERFCOUNTER0_LO 0 x3300#define regTD_PERFCOUNTER0_LO_BASE_IDX 1 #define regTD_PERFCOUNTER0_HI 0 x3301#define regTD_PERFCOUNTER0_HI_BASE_IDX 1 #define regTD_PERFCOUNTER1_LO 0 x3302#define regTD_PERFCOUNTER1_LO_BASE_IDX 1 #define regTD_PERFCOUNTER1_HI 0 x3303#define regTD_PERFCOUNTER1_HI_BASE_IDX 1 #define regTCP_PERFCOUNTER0_LO 0 x3340#define regTCP_PERFCOUNTER0_LO_BASE_IDX 1 #define regTCP_PERFCOUNTER0_HI 0 x3341#define regTCP_PERFCOUNTER0_HI_BASE_IDX 1 #define regTCP_PERFCOUNTER1_LO 0 x3342#define regTCP_PERFCOUNTER1_LO_BASE_IDX 1 #define regTCP_PERFCOUNTER1_HI 0 x3343#define regTCP_PERFCOUNTER1_HI_BASE_IDX 1 #define regTCP_PERFCOUNTER2_LO 0 x3344#define regTCP_PERFCOUNTER2_LO_BASE_IDX 1 #define regTCP_PERFCOUNTER2_HI 0 x3345#define regTCP_PERFCOUNTER2_HI_BASE_IDX 1 #define regTCP_PERFCOUNTER3_LO 0 x3346#define regTCP_PERFCOUNTER3_LO_BASE_IDX 1 #define regTCP_PERFCOUNTER3_HI 0 x3347#define regTCP_PERFCOUNTER3_HI_BASE_IDX 1 #define regTCC_PERFCOUNTER0_LO 0 x3380#define regTCC_PERFCOUNTER0_LO_BASE_IDX 1 #define regTCC_PERFCOUNTER0_HI 0 x3381#define regTCC_PERFCOUNTER0_HI_BASE_IDX 1 #define regTCC_PERFCOUNTER1_LO 0 x3382#define regTCC_PERFCOUNTER1_LO_BASE_IDX 1 #define regTCC_PERFCOUNTER1_HI 0 x3383#define regTCC_PERFCOUNTER1_HI_BASE_IDX 1 #define regTCC_PERFCOUNTER2_LO 0 x3384#define regTCC_PERFCOUNTER2_LO_BASE_IDX 1 #define regTCC_PERFCOUNTER2_HI 0 x3385#define regTCC_PERFCOUNTER2_HI_BASE_IDX 1 #define regTCC_PERFCOUNTER3_LO 0 x3386#define regTCC_PERFCOUNTER3_LO_BASE_IDX 1 #define regTCC_PERFCOUNTER3_HI 0 x3387#define regTCC_PERFCOUNTER3_HI_BASE_IDX 1 #define regTCA_PERFCOUNTER0_LO 0 x3390#define regTCA_PERFCOUNTER0_LO_BASE_IDX 1 #define regTCA_PERFCOUNTER0_HI 0 x3391#define regTCA_PERFCOUNTER0_HI_BASE_IDX 1 #define regTCA_PERFCOUNTER1_LO 0 x3392#define regTCA_PERFCOUNTER1_LO_BASE_IDX 1 #define regTCA_PERFCOUNTER1_HI 0 x3393#define regTCA_PERFCOUNTER1_HI_BASE_IDX 1 #define regTCA_PERFCOUNTER2_LO 0 x3394#define regTCA_PERFCOUNTER2_LO_BASE_IDX 1 #define regTCA_PERFCOUNTER2_HI 0 x3395#define regTCA_PERFCOUNTER2_HI_BASE_IDX 1 #define regTCA_PERFCOUNTER3_LO 0 x3396#define regTCA_PERFCOUNTER3_LO_BASE_IDX 1 #define regTCA_PERFCOUNTER3_HI 0 x3397#define regTCA_PERFCOUNTER3_HI_BASE_IDX 1 #define regCB_PERFCOUNTER0_LO 0 x3406#define regCB_PERFCOUNTER0_LO_BASE_IDX 1 #define regCB_PERFCOUNTER0_HI 0 x3407#define regCB_PERFCOUNTER0_HI_BASE_IDX 1 #define regCB_PERFCOUNTER1_LO 0 x3408#define regCB_PERFCOUNTER1_LO_BASE_IDX 1 #define regCB_PERFCOUNTER1_HI 0 x3409#define regCB_PERFCOUNTER1_HI_BASE_IDX 1 #define regCB_PERFCOUNTER2_LO 0 x340a#define regCB_PERFCOUNTER2_LO_BASE_IDX 1 #define regCB_PERFCOUNTER2_HI 0 x340b#define regCB_PERFCOUNTER2_HI_BASE_IDX 1 #define regCB_PERFCOUNTER3_LO 0 x340c#define regCB_PERFCOUNTER3_LO_BASE_IDX 1 #define regCB_PERFCOUNTER3_HI 0 x340d#define regCB_PERFCOUNTER3_HI_BASE_IDX 1 #define regDB_PERFCOUNTER0_LO 0 x3440#define regDB_PERFCOUNTER0_LO_BASE_IDX 1 #define regDB_PERFCOUNTER0_HI 0 x3441#define regDB_PERFCOUNTER0_HI_BASE_IDX 1 #define regDB_PERFCOUNTER1_LO 0 x3442#define regDB_PERFCOUNTER1_LO_BASE_IDX 1 #define regDB_PERFCOUNTER1_HI 0 x3443#define regDB_PERFCOUNTER1_HI_BASE_IDX 1 #define regDB_PERFCOUNTER2_LO 0 x3444#define regDB_PERFCOUNTER2_LO_BASE_IDX 1 #define regDB_PERFCOUNTER2_HI 0 x3445#define regDB_PERFCOUNTER2_HI_BASE_IDX 1 #define regDB_PERFCOUNTER3_LO 0 x3446#define regDB_PERFCOUNTER3_LO_BASE_IDX 1 #define regDB_PERFCOUNTER3_HI 0 x3447#define regDB_PERFCOUNTER3_HI_BASE_IDX 1 #define regRLC_PERFCOUNTER0_LO 0 x3480#define regRLC_PERFCOUNTER0_LO_BASE_IDX 1 #define regRLC_PERFCOUNTER0_HI 0 x3481#define regRLC_PERFCOUNTER0_HI_BASE_IDX 1 #define regRLC_PERFCOUNTER1_LO 0 x3482#define regRLC_PERFCOUNTER1_LO_BASE_IDX 1 #define regRLC_PERFCOUNTER1_HI 0 x3483#define regRLC_PERFCOUNTER1_HI_BASE_IDX 1 #define regRMI_PERFCOUNTER0_LO 0 x34c0#define regRMI_PERFCOUNTER0_LO_BASE_IDX 1 #define regRMI_PERFCOUNTER0_HI 0 x34c1#define regRMI_PERFCOUNTER0_HI_BASE_IDX 1 #define regRMI_PERFCOUNTER1_LO 0 x34c2#define regRMI_PERFCOUNTER1_LO_BASE_IDX 1 #define regRMI_PERFCOUNTER1_HI 0 x34c3#define regRMI_PERFCOUNTER1_HI_BASE_IDX 1 #define regRMI_PERFCOUNTER2_LO 0 x34c4#define regRMI_PERFCOUNTER2_LO_BASE_IDX 1 #define regRMI_PERFCOUNTER2_HI 0 x34c5#define regRMI_PERFCOUNTER2_HI_BASE_IDX 1 #define regRMI_PERFCOUNTER3_LO 0 x34c6#define regRMI_PERFCOUNTER3_LO_BASE_IDX 1 #define regRMI_PERFCOUNTER3_HI 0 x34c7#define regRMI_PERFCOUNTER3_HI_BASE_IDX 1 // addressBlock: gc_perfsdec // base address: 0x36000 #define regCPG_PERFCOUNTER1_SELECT 0 x3800#define regCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regCPG_PERFCOUNTER0_SELECT1 0 x3801#define regCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regCPG_PERFCOUNTER0_SELECT 0 x3802#define regCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regCPC_PERFCOUNTER1_SELECT 0 x3803#define regCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regCPC_PERFCOUNTER0_SELECT1 0 x3804#define regCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regCPF_PERFCOUNTER1_SELECT 0 x3805#define regCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regCPF_PERFCOUNTER0_SELECT1 0 x3806#define regCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regCPF_PERFCOUNTER0_SELECT 0 x3807#define regCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regCP_PERFMON_CNTL 0 x3808#define regCP_PERFMON_CNTL_BASE_IDX 1 #define regCPC_PERFCOUNTER0_SELECT 0 x3809#define regCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regCPF_TC_PERF_COUNTER_WINDOW_SELECT 0 x380a#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 #define regCPG_TC_PERF_COUNTER_WINDOW_SELECT 0 x380b#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 #define regCPF_LATENCY_STATS_SELECT 0 x380c#define regCPF_LATENCY_STATS_SELECT_BASE_IDX 1 #define regCPG_LATENCY_STATS_SELECT 0 x380d#define regCPG_LATENCY_STATS_SELECT_BASE_IDX 1 #define regCPC_LATENCY_STATS_SELECT 0 x380e#define regCPC_LATENCY_STATS_SELECT_BASE_IDX 1 #define regCP_DRAW_OBJECT 0 x3810#define regCP_DRAW_OBJECT_BASE_IDX 1 #define regCP_DRAW_OBJECT_COUNTER 0 x3811#define regCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 #define regCP_DRAW_WINDOW_MASK_HI 0 x3812#define regCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 #define regCP_DRAW_WINDOW_HI 0 x3813#define regCP_DRAW_WINDOW_HI_BASE_IDX 1 #define regCP_DRAW_WINDOW_LO 0 x3814#define regCP_DRAW_WINDOW_LO_BASE_IDX 1 #define regCP_DRAW_WINDOW_CNTL 0 x3815#define regCP_DRAW_WINDOW_CNTL_BASE_IDX 1 #define regGRBM_PERFCOUNTER0_SELECT 0 x3840#define regGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regGRBM_PERFCOUNTER1_SELECT 0 x3841#define regGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regGRBM_SE0_PERFCOUNTER_SELECT 0 x3842#define regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX 1 #define regGRBM_SE1_PERFCOUNTER_SELECT 0 x3843#define regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX 1 #define regGRBM_SE2_PERFCOUNTER_SELECT 0 x3844#define regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX 1 #define regGRBM_SE3_PERFCOUNTER_SELECT 0 x3845#define regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX 1 #define regWD_PERFCOUNTER0_SELECT 0 x3880#define regWD_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regWD_PERFCOUNTER1_SELECT 0 x3881#define regWD_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regWD_PERFCOUNTER2_SELECT 0 x3882#define regWD_PERFCOUNTER2_SELECT_BASE_IDX 1 #define regWD_PERFCOUNTER3_SELECT 0 x3883#define regWD_PERFCOUNTER3_SELECT_BASE_IDX 1 #define regIA_PERFCOUNTER0_SELECT 0 x3884#define regIA_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regIA_PERFCOUNTER1_SELECT 0 x3885#define regIA_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regIA_PERFCOUNTER2_SELECT 0 x3886#define regIA_PERFCOUNTER2_SELECT_BASE_IDX 1 #define regIA_PERFCOUNTER3_SELECT 0 x3887#define regIA_PERFCOUNTER3_SELECT_BASE_IDX 1 #define regIA_PERFCOUNTER0_SELECT1 0 x3888#define regIA_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regVGT_PERFCOUNTER0_SELECT 0 x388c#define regVGT_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regVGT_PERFCOUNTER1_SELECT 0 x388d#define regVGT_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regVGT_PERFCOUNTER2_SELECT 0 x388e#define regVGT_PERFCOUNTER2_SELECT_BASE_IDX 1 #define regVGT_PERFCOUNTER3_SELECT 0 x388f#define regVGT_PERFCOUNTER3_SELECT_BASE_IDX 1 #define regVGT_PERFCOUNTER0_SELECT1 0 x3890#define regVGT_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regVGT_PERFCOUNTER1_SELECT1 0 x3891#define regVGT_PERFCOUNTER1_SELECT1_BASE_IDX 1 #define regVGT_PERFCOUNTER_SEID_MASK 0 x3894#define regVGT_PERFCOUNTER_SEID_MASK_BASE_IDX 1 #define regPA_SU_PERFCOUNTER0_SELECT 0 x3900#define regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regPA_SU_PERFCOUNTER0_SELECT1 0 x3901#define regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regPA_SU_PERFCOUNTER1_SELECT 0 x3902#define regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regPA_SU_PERFCOUNTER1_SELECT1 0 x3903#define regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 #define regPA_SU_PERFCOUNTER2_SELECT 0 x3904#define regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 #define regPA_SU_PERFCOUNTER3_SELECT 0 x3905#define regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 #define regPA_SC_PERFCOUNTER0_SELECT 0 x3940#define regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regPA_SC_PERFCOUNTER0_SELECT1 0 x3941#define regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regPA_SC_PERFCOUNTER1_SELECT 0 x3942#define regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regPA_SC_PERFCOUNTER2_SELECT 0 x3943#define regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 #define regPA_SC_PERFCOUNTER3_SELECT 0 x3944#define regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 #define regPA_SC_PERFCOUNTER4_SELECT 0 x3945#define regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 #define regPA_SC_PERFCOUNTER5_SELECT 0 x3946#define regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 #define regPA_SC_PERFCOUNTER6_SELECT 0 x3947#define regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 #define regPA_SC_PERFCOUNTER7_SELECT 0 x3948#define regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 #define regSPI_PERFCOUNTER0_SELECT 0 x3980#define regSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regSPI_PERFCOUNTER1_SELECT 0 x3981#define regSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regSPI_PERFCOUNTER2_SELECT 0 x3982#define regSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 #define regSPI_PERFCOUNTER3_SELECT 0 x3983#define regSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 #define regSPI_PERFCOUNTER0_SELECT1 0 x3984#define regSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regSPI_PERFCOUNTER1_SELECT1 0 x3985#define regSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 #define regSPI_PERFCOUNTER2_SELECT1 0 x3986#define regSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 #define regSPI_PERFCOUNTER3_SELECT1 0 x3987#define regSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 #define regSPI_PERFCOUNTER4_SELECT 0 x3988#define regSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 #define regSPI_PERFCOUNTER5_SELECT 0 x3989#define regSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 #define regSPI_PERFCOUNTER_BINS 0 x398a#define regSPI_PERFCOUNTER_BINS_BASE_IDX 1 #define regSQ_PERFCOUNTER0_SELECT 0 x39c0#define regSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER1_SELECT 0 x39c1#define regSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER2_SELECT 0 x39c2#define regSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER3_SELECT 0 x39c3#define regSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER4_SELECT 0 x39c4#define regSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER5_SELECT 0 x39c5#define regSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER6_SELECT 0 x39c6#define regSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER7_SELECT 0 x39c7#define regSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER8_SELECT 0 x39c8#define regSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER9_SELECT 0 x39c9#define regSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER10_SELECT 0 x39ca#define regSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER11_SELECT 0 x39cb#define regSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER12_SELECT 0 x39cc#define regSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER13_SELECT 0 x39cd#define regSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER14_SELECT 0 x39ce#define regSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER15_SELECT 0 x39cf#define regSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 #define regSQ_PERFCOUNTER_CTRL 0 x39e0#define regSQ_PERFCOUNTER_CTRL_BASE_IDX 1 #define regSQ_PERFCOUNTER_MASK 0 x39e1#define regSQ_PERFCOUNTER_MASK_BASE_IDX 1 #define regSQ_PERFCOUNTER_CTRL2 0 x39e2#define regSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 #define regSX_PERFCOUNTER0_SELECT 0 x3a40#define regSX_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regSX_PERFCOUNTER1_SELECT 0 x3a41#define regSX_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regSX_PERFCOUNTER2_SELECT 0 x3a42#define regSX_PERFCOUNTER2_SELECT_BASE_IDX 1 #define regSX_PERFCOUNTER3_SELECT 0 x3a43#define regSX_PERFCOUNTER3_SELECT_BASE_IDX 1 #define regSX_PERFCOUNTER0_SELECT1 0 x3a44#define regSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regSX_PERFCOUNTER1_SELECT1 0 x3a45#define regSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 #define regGDS_PERFCOUNTER0_SELECT 0 x3a80#define regGDS_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regGDS_PERFCOUNTER1_SELECT 0 x3a81#define regGDS_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regGDS_PERFCOUNTER2_SELECT 0 x3a82#define regGDS_PERFCOUNTER2_SELECT_BASE_IDX 1 #define regGDS_PERFCOUNTER3_SELECT 0 x3a83#define regGDS_PERFCOUNTER3_SELECT_BASE_IDX 1 #define regGDS_PERFCOUNTER0_SELECT1 0 x3a84#define regGDS_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regTA_PERFCOUNTER0_SELECT 0 x3ac0#define regTA_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regTA_PERFCOUNTER0_SELECT1 0 x3ac1#define regTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regTA_PERFCOUNTER1_SELECT 0 x3ac2#define regTA_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regTD_PERFCOUNTER0_SELECT 0 x3b00#define regTD_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regTD_PERFCOUNTER0_SELECT1 0 x3b01#define regTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regTD_PERFCOUNTER1_SELECT 0 x3b02#define regTD_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regTCP_PERFCOUNTER0_SELECT 0 x3b40#define regTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regTCP_PERFCOUNTER0_SELECT1 0 x3b41#define regTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regTCP_PERFCOUNTER1_SELECT 0 x3b42#define regTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regTCP_PERFCOUNTER1_SELECT1 0 x3b43#define regTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 #define regTCP_PERFCOUNTER2_SELECT 0 x3b44#define regTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 #define regTCP_PERFCOUNTER3_SELECT 0 x3b45#define regTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 #define regTCC_PERFCOUNTER0_SELECT 0 x3b80#define regTCC_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regTCC_PERFCOUNTER0_SELECT1 0 x3b81#define regTCC_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regTCC_PERFCOUNTER1_SELECT 0 x3b82#define regTCC_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regTCC_PERFCOUNTER1_SELECT1 0 x3b83#define regTCC_PERFCOUNTER1_SELECT1_BASE_IDX 1 #define regTCC_PERFCOUNTER2_SELECT 0 x3b84#define regTCC_PERFCOUNTER2_SELECT_BASE_IDX 1 #define regTCC_PERFCOUNTER3_SELECT 0 x3b85#define regTCC_PERFCOUNTER3_SELECT_BASE_IDX 1 #define regTCA_PERFCOUNTER0_SELECT 0 x3b90#define regTCA_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regTCA_PERFCOUNTER0_SELECT1 0 x3b91#define regTCA_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regTCA_PERFCOUNTER1_SELECT 0 x3b92#define regTCA_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regTCA_PERFCOUNTER1_SELECT1 0 x3b93#define regTCA_PERFCOUNTER1_SELECT1_BASE_IDX 1 #define regTCA_PERFCOUNTER2_SELECT 0 x3b94#define regTCA_PERFCOUNTER2_SELECT_BASE_IDX 1 #define regTCA_PERFCOUNTER3_SELECT 0 x3b95#define regTCA_PERFCOUNTER3_SELECT_BASE_IDX 1 #define regCB_PERFCOUNTER_FILTER 0 x3c00#define regCB_PERFCOUNTER_FILTER_BASE_IDX 1 #define regCB_PERFCOUNTER0_SELECT 0 x3c01#define regCB_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regCB_PERFCOUNTER0_SELECT1 0 x3c02#define regCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regCB_PERFCOUNTER1_SELECT 0 x3c03#define regCB_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regCB_PERFCOUNTER2_SELECT 0 x3c04#define regCB_PERFCOUNTER2_SELECT_BASE_IDX 1 #define regCB_PERFCOUNTER3_SELECT 0 x3c05#define regCB_PERFCOUNTER3_SELECT_BASE_IDX 1 #define regDB_PERFCOUNTER0_SELECT 0 x3c40#define regDB_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regDB_PERFCOUNTER0_SELECT1 0 x3c41#define regDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regDB_PERFCOUNTER1_SELECT 0 x3c42#define regDB_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regDB_PERFCOUNTER1_SELECT1 0 x3c43#define regDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 #define regDB_PERFCOUNTER2_SELECT 0 x3c44#define regDB_PERFCOUNTER2_SELECT_BASE_IDX 1 #define regDB_PERFCOUNTER3_SELECT 0 x3c46#define regDB_PERFCOUNTER3_SELECT_BASE_IDX 1 #define regRLC_SPM_PERFMON_CNTL 0 x3c80#define regRLC_SPM_PERFMON_CNTL_BASE_IDX 1 #define regRLC_SPM_PERFMON_RING_BASE_LO 0 x3c81#define regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 #define regRLC_SPM_PERFMON_RING_BASE_HI 0 x3c82#define regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 #define regRLC_SPM_PERFMON_RING_SIZE 0 x3c83#define regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 #define regRLC_SPM_PERFMON_SEGMENT_SIZE 0 x3c84#define regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 #define regRLC_SPM_SE_MUXSEL_ADDR 0 x3c85#define regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 #define regRLC_SPM_SE_MUXSEL_DATA 0 x3c86#define regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 #define regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0 x3c87#define regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0 x3c88#define regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0 x3c89#define regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0 x3c8a#define regRLC_SPM_CB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0 x3c8b#define regRLC_SPM_DB_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0 x3c8c#define regRLC_SPM_PA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0 x3c8d#define regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0 x3c8e#define regRLC_SPM_IA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0 x3c90#define regRLC_SPM_SC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0 x3c91#define regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0 x3c92#define regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0 x3c93#define regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0 x3c94#define regRLC_SPM_TA_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0 x3c95#define regRLC_SPM_TD_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0 x3c96#define regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0 x3c97#define regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0 x3c98#define regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0 x3c9a#define regRLC_SPM_SX_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_GLOBAL_MUXSEL_ADDR 0 x3c9b#define regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 #define regRLC_SPM_GLOBAL_MUXSEL_DATA 0 x3c9c#define regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 #define regRLC_SPM_RING_RDPTR 0 x3c9d#define regRLC_SPM_RING_RDPTR_BASE_IDX 1 #define regRLC_SPM_SEGMENT_THRESHOLD 0 x3c9e#define regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 #define regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY 0 x3ca3#define regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_BASE_IDX 1 #define regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX 0 x3ca4#define regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX_BASE_IDX 1 #define regRLC_SPM_PERFMON_SEGMENT_SIZE_CORE1 0 x3caf#define regRLC_SPM_PERFMON_SEGMENT_SIZE_CORE1_BASE_IDX 1 #define regRLC_PERFMON_CLK_CNTL_UCODE 0 x3cbe#define regRLC_PERFMON_CLK_CNTL_UCODE_BASE_IDX 1 #define regRLC_PERFMON_CLK_CNTL 0 x3cbf#define regRLC_PERFMON_CLK_CNTL_BASE_IDX 1 #define regRLC_PERFMON_CNTL 0 x3cc0#define regRLC_PERFMON_CNTL_BASE_IDX 1 #define regRLC_PERFCOUNTER0_SELECT 0 x3cc1#define regRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regRLC_PERFCOUNTER1_SELECT 0 x3cc2#define regRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regRLC_GPU_IOV_PERF_CNT_CNTL 0 x3cc3#define regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 #define regRLC_GPU_IOV_PERF_CNT_WR_ADDR 0 x3cc4#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 #define regRLC_GPU_IOV_PERF_CNT_WR_DATA 0 x3cc5#define regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 #define regRLC_GPU_IOV_PERF_CNT_RD_ADDR 0 x3cc6#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 #define regRLC_GPU_IOV_PERF_CNT_RD_DATA 0 x3cc7#define regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 #define regRMI_PERFCOUNTER0_SELECT 0 x3d00#define regRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 #define regRMI_PERFCOUNTER0_SELECT1 0 x3d01#define regRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 #define regRMI_PERFCOUNTER1_SELECT 0 x3d02#define regRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 #define regRMI_PERFCOUNTER2_SELECT 0 x3d03#define regRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 #define regRMI_PERFCOUNTER2_SELECT1 0 x3d04#define regRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 #define regRMI_PERFCOUNTER3_SELECT 0 x3d05#define regRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 #define regRMI_PERF_COUNTER_CNTL 0 x3d06#define regRMI_PERF_COUNTER_CNTL_BASE_IDX 1 // addressBlock: gc_pwrdec // base address: 0x3c000 #define regCGTS_SM_CTRL_REG 0 x5000#define regCGTS_SM_CTRL_REG_BASE_IDX 1 #define regCGTS_RD_CTRL_REG 0 x5001#define regCGTS_RD_CTRL_REG_BASE_IDX 1 #define regCGTS_RD_REG 0 x5002#define regCGTS_RD_REG_BASE_IDX 1 #define regCGTS_TCC_DISABLE 0 x5003#define regCGTS_TCC_DISABLE_BASE_IDX 1 #define regCGTS_USER_TCC_DISABLE 0 x5004#define regCGTS_USER_TCC_DISABLE_BASE_IDX 1 #define regCGTS_TCC_DISABLE2 0 x5005#define regCGTS_TCC_DISABLE2_BASE_IDX 1 #define regCGTS_USER_TCC_DISABLE2 0 x5006#define regCGTS_USER_TCC_DISABLE2_BASE_IDX 1 #define regCGTS_CU0_SP0_CTRL_REG 0 x5008#define regCGTS_CU0_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU0_LDS_SQ_CTRL_REG 0 x5009#define regCGTS_CU0_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU0_TA_SQC_CTRL_REG 0 x500a#define regCGTS_CU0_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU0_SP1_CTRL_REG 0 x500b#define regCGTS_CU0_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU1_SP0_CTRL_REG 0 x500d#define regCGTS_CU1_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU1_LDS_SQ_CTRL_REG 0 x500e#define regCGTS_CU1_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU1_TA_SQC_CTRL_REG 0 x500f#define regCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU1_SP1_CTRL_REG 0 x5010#define regCGTS_CU1_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU2_SP0_CTRL_REG 0 x5012#define regCGTS_CU2_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU2_LDS_SQ_CTRL_REG 0 x5013#define regCGTS_CU2_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU2_TA_SQC_CTRL_REG 0 x5014#define regCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU2_SP1_CTRL_REG 0 x5015#define regCGTS_CU2_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU3_SP0_CTRL_REG 0 x5017#define regCGTS_CU3_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU3_LDS_SQ_CTRL_REG 0 x5018#define regCGTS_CU3_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU3_TA_SQC_CTRL_REG 0 x5019#define regCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU3_SP1_CTRL_REG 0 x501a#define regCGTS_CU3_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU4_SP0_CTRL_REG 0 x501c#define regCGTS_CU4_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU4_LDS_SQ_CTRL_REG 0 x501d#define regCGTS_CU4_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU4_TA_SQC_CTRL_REG 0 x501e#define regCGTS_CU4_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU4_SP1_CTRL_REG 0 x501f#define regCGTS_CU4_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU5_SP0_CTRL_REG 0 x5021#define regCGTS_CU5_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU5_LDS_SQ_CTRL_REG 0 x5022#define regCGTS_CU5_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU5_TA_SQC_CTRL_REG 0 x5023#define regCGTS_CU5_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU5_SP1_CTRL_REG 0 x5024#define regCGTS_CU5_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU6_SP0_CTRL_REG 0 x5026#define regCGTS_CU6_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU6_LDS_SQ_CTRL_REG 0 x5027#define regCGTS_CU6_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU6_TA_SQC_CTRL_REG 0 x5028#define regCGTS_CU6_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU6_SP1_CTRL_REG 0 x5029#define regCGTS_CU6_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU7_SP0_CTRL_REG 0 x502b#define regCGTS_CU7_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU7_LDS_SQ_CTRL_REG 0 x502c#define regCGTS_CU7_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU7_TA_SQC_CTRL_REG 0 x502d#define regCGTS_CU7_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU7_SP1_CTRL_REG 0 x502e#define regCGTS_CU7_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU8_SP0_CTRL_REG 0 x5030#define regCGTS_CU8_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU8_LDS_SQ_CTRL_REG 0 x5031#define regCGTS_CU8_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU8_TA_SQC_CTRL_REG 0 x5032#define regCGTS_CU8_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU8_SP1_CTRL_REG 0 x5033#define regCGTS_CU8_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU9_SP0_CTRL_REG 0 x5035#define regCGTS_CU9_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU9_LDS_SQ_CTRL_REG 0 x5036#define regCGTS_CU9_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU9_TA_SQC_CTRL_REG 0 x5037#define regCGTS_CU9_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU9_SP1_CTRL_REG 0 x5038#define regCGTS_CU9_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU10_SP0_CTRL_REG 0 x503a#define regCGTS_CU10_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU10_LDS_SQ_CTRL_REG 0 x503b#define regCGTS_CU10_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU10_TA_SQC_CTRL_REG 0 x503c#define regCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU10_SP1_CTRL_REG 0 x503d#define regCGTS_CU10_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU11_SP0_CTRL_REG 0 x503f#define regCGTS_CU11_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU11_LDS_SQ_CTRL_REG 0 x5040#define regCGTS_CU11_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU11_TA_SQC_CTRL_REG 0 x5041#define regCGTS_CU11_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU11_SP1_CTRL_REG 0 x5042#define regCGTS_CU11_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU12_SP0_CTRL_REG 0 x5044#define regCGTS_CU12_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU12_LDS_SQ_CTRL_REG 0 x5045#define regCGTS_CU12_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU12_TA_SQC_CTRL_REG 0 x5046#define regCGTS_CU12_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU12_SP1_CTRL_REG 0 x5047#define regCGTS_CU12_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU13_SP0_CTRL_REG 0 x5049#define regCGTS_CU13_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU13_LDS_SQ_CTRL_REG 0 x504a#define regCGTS_CU13_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU13_TA_SQC_CTRL_REG 0 x504b#define regCGTS_CU13_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU13_SP1_CTRL_REG 0 x504c#define regCGTS_CU13_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU14_SP0_CTRL_REG 0 x504e#define regCGTS_CU14_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU14_LDS_SQ_CTRL_REG 0 x504f#define regCGTS_CU14_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU14_TA_SQC_CTRL_REG 0 x5050#define regCGTS_CU14_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU14_SP1_CTRL_REG 0 x5051#define regCGTS_CU14_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU15_SP0_CTRL_REG 0 x5053#define regCGTS_CU15_SP0_CTRL_REG_BASE_IDX 1 #define regCGTS_CU15_LDS_SQ_CTRL_REG 0 x5054#define regCGTS_CU15_LDS_SQ_CTRL_REG_BASE_IDX 1 #define regCGTS_CU15_TA_SQC_CTRL_REG 0 x5055#define regCGTS_CU15_TA_SQC_CTRL_REG_BASE_IDX 1 #define regCGTS_CU15_SP1_CTRL_REG 0 x5056#define regCGTS_CU15_SP1_CTRL_REG_BASE_IDX 1 #define regCGTS_CU0_TCPI_CTRL_REG 0 x5058#define regCGTS_CU0_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTS_CU1_TCPI_CTRL_REG 0 x5059#define regCGTS_CU1_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTS_CU2_TCPI_CTRL_REG 0 x505a#define regCGTS_CU2_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTS_CU3_TCPI_CTRL_REG 0 x505b#define regCGTS_CU3_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTS_CU4_TCPI_CTRL_REG 0 x505c#define regCGTS_CU4_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTS_CU5_TCPI_CTRL_REG 0 x505d#define regCGTS_CU5_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTS_CU6_TCPI_CTRL_REG 0 x505e#define regCGTS_CU6_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTS_CU7_TCPI_CTRL_REG 0 x505f#define regCGTS_CU7_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTS_CU8_TCPI_CTRL_REG 0 x5060#define regCGTS_CU8_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTS_CU9_TCPI_CTRL_REG 0 x5061#define regCGTS_CU9_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTS_CU10_TCPI_CTRL_REG 0 x5062#define regCGTS_CU10_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTS_CU11_TCPI_CTRL_REG 0 x5063#define regCGTS_CU11_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTS_CU12_TCPI_CTRL_REG 0 x5064#define regCGTS_CU12_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTS_CU13_TCPI_CTRL_REG 0 x5065#define regCGTS_CU13_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTS_CU14_TCPI_CTRL_REG 0 x5066#define regCGTS_CU14_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTS_CU15_TCPI_CTRL_REG 0 x5067#define regCGTS_CU15_TCPI_CTRL_REG_BASE_IDX 1 #define regCGTT_SPI_PS_CLK_CTRL 0 x507d#define regCGTT_SPI_PS_CLK_CTRL_BASE_IDX 1 #define regCGTT_SPIS_CLK_CTRL 0 x507e#define regCGTT_SPIS_CLK_CTRL_BASE_IDX 1 #define regCGTT_SPI_CLK_CTRL 0 x5080#define regCGTT_SPI_CLK_CTRL_BASE_IDX 1 #define regCGTT_PC_CLK_CTRL 0 x5081#define regCGTT_PC_CLK_CTRL_BASE_IDX 1 #define regCGTT_BCI_CLK_CTRL 0 x5082#define regCGTT_BCI_CLK_CTRL_BASE_IDX 1 #define regCGTT_PA_CLK_CTRL 0 x5088#define regCGTT_PA_CLK_CTRL_BASE_IDX 1 #define regCGTT_SC_CLK_CTRL0 0 x5089#define regCGTT_SC_CLK_CTRL0_BASE_IDX 1 #define regCGTT_SC_CLK_CTRL1 0 x508a#define regCGTT_SC_CLK_CTRL1_BASE_IDX 1 #define regCGTT_SC_CLK_CTRL2 0 x508b#define regCGTT_SC_CLK_CTRL2_BASE_IDX 1 #define regCGTT_SQG_CLK_CTRL 0 x508d#define regCGTT_SQG_CLK_CTRL_BASE_IDX 1 #define regSQ_ALU_CLK_CTRL 0 x508e#define regSQ_ALU_CLK_CTRL_BASE_IDX 1 #define regSQ_TEX_CLK_CTRL 0 x508f#define regSQ_TEX_CLK_CTRL_BASE_IDX 1 #define regSQ_LDS_CLK_CTRL 0 x5090#define regSQ_LDS_CLK_CTRL_BASE_IDX 1 #define regSQ_POWER_THROTTLE 0 x5091#define regSQ_POWER_THROTTLE_BASE_IDX 1 #define regSQ_POWER_THROTTLE2 0 x5092#define regSQ_POWER_THROTTLE2_BASE_IDX 1 #define regCGTT_SX_CLK_CTRL0 0 x5094#define regCGTT_SX_CLK_CTRL0_BASE_IDX 1 #define regCGTT_SX_CLK_CTRL1 0 x5095#define regCGTT_SX_CLK_CTRL1_BASE_IDX 1 #define regCGTT_SX_CLK_CTRL2 0 x5096#define regCGTT_SX_CLK_CTRL2_BASE_IDX 1 #define regCGTT_SX_CLK_CTRL3 0 x5097#define regCGTT_SX_CLK_CTRL3_BASE_IDX 1 #define regCGTT_SX_CLK_CTRL4 0 x5098#define regCGTT_SX_CLK_CTRL4_BASE_IDX 1 #define regTD_CGTT_CTRL 0 x509c#define regTD_CGTT_CTRL_BASE_IDX 1 #define regTA_CGTT_CTRL 0 x509d#define regTA_CGTT_CTRL_BASE_IDX 1 #define regCGTT_TCI_CLK_CTRL 0 x509f#define regCGTT_TCI_CLK_CTRL_BASE_IDX 1 #define regCGTT_GDS_CLK_CTRL 0 x50a0#define regCGTT_GDS_CLK_CTRL_BASE_IDX 1 #define regCGTT_TCP_TCR_CLK_CTRL 0 x50a1#define regCGTT_TCP_TCR_CLK_CTRL_BASE_IDX 1 #define regCGTT_TCI_TCR_CLK_CTRL 0 x50a2#define regCGTT_TCI_TCR_CLK_CTRL_BASE_IDX 1 #define regTCX_CGTT_SCLK_CTRL 0 x50a3#define regTCX_CGTT_SCLK_CTRL_BASE_IDX 1 #define regDB_CGTT_CLK_CTRL_0 0 x50a4#define regDB_CGTT_CLK_CTRL_0_BASE_IDX 1 #define regCB_CGTT_SCLK_CTRL 0 x50a8#define regCB_CGTT_SCLK_CTRL_BASE_IDX 1 #define regTCC_CGTT_SCLK_CTRL 0 x50ac#define regTCC_CGTT_SCLK_CTRL_BASE_IDX 1 #define regTCC_CGTT_SCLK_CTRL2 0 x50ad#define regTCC_CGTT_SCLK_CTRL2_BASE_IDX 1 #define regTCC_CGTT_SCLK_CTRL3 0 x50ae#define regTCC_CGTT_SCLK_CTRL3_BASE_IDX 1 #define regTCA_CGTT_SCLK_CTRL 0 x50af#define regTCA_CGTT_SCLK_CTRL_BASE_IDX 1 #define regCGTT_CP_CLK_CTRL 0 x50b0#define regCGTT_CP_CLK_CTRL_BASE_IDX 1 #define regCGTT_CPF_CLK_CTRL 0 x50b1#define regCGTT_CPF_CLK_CTRL_BASE_IDX 1 #define regCGTT_CPC_CLK_CTRL 0 x50b2#define regCGTT_CPC_CLK_CTRL_BASE_IDX 1 #define regCGTT_RLC_CLK_CTRL 0 x50b5#define regCGTT_RLC_CLK_CTRL_BASE_IDX 1 #define regRLC_GFX_RM_CNTL 0 x50b6#define regRLC_GFX_RM_CNTL_BASE_IDX 1 #define regRMI_CGTT_SCLK_CTRL 0 x50c0#define regRMI_CGTT_SCLK_CTRL_BASE_IDX 1 #define regSE_CAC_CGTT_CLK_CTRL 0 x50d0#define regSE_CAC_CGTT_CLK_CTRL_BASE_IDX 1 #define regGC_CAC_CGTT_CLK_CTRL 0 x50d8#define regGC_CAC_CGTT_CLK_CTRL_BASE_IDX 1 #define regGRBM_CGTT_CLK_CNTL 0 x50e0#define regGRBM_CGTT_CLK_CNTL_BASE_IDX 1 // addressBlock: gc_rbdec // base address: 0x9800 #define regDB_DEBUG 0 x060c#define regDB_DEBUG_BASE_IDX 0 #define regDB_DEBUG2 0 x060d#define regDB_DEBUG2_BASE_IDX 0 #define regDB_DEBUG3 0 x060e#define regDB_DEBUG3_BASE_IDX 0 #define regDB_DEBUG4 0 x060f#define regDB_DEBUG4_BASE_IDX 0 #define regDB_CREDIT_LIMIT 0 x0614#define regDB_CREDIT_LIMIT_BASE_IDX 0 #define regDB_WATERMARKS 0 x0615#define regDB_WATERMARKS_BASE_IDX 0 #define regDB_SUBTILE_CONTROL 0 x0616#define regDB_SUBTILE_CONTROL_BASE_IDX 0 #define regDB_FREE_CACHELINES 0 x0617#define regDB_FREE_CACHELINES_BASE_IDX 0 #define regDB_FIFO_DEPTH1 0 x0618#define regDB_FIFO_DEPTH1_BASE_IDX 0 #define regDB_FIFO_DEPTH2 0 x0619#define regDB_FIFO_DEPTH2_BASE_IDX 0 #define regDB_EXCEPTION_CONTROL 0 x061a#define regDB_EXCEPTION_CONTROL_BASE_IDX 0 #define regDB_RING_CONTROL 0 x061b#define regDB_RING_CONTROL_BASE_IDX 0 #define regDB_MEM_ARB_WATERMARKS 0 x061c#define regDB_MEM_ARB_WATERMARKS_BASE_IDX 0 #define regDB_RMI_CACHE_POLICY 0 x061e#define regDB_RMI_CACHE_POLICY_BASE_IDX 0 #define regDB_DFSM_CONFIG 0 x0630#define regDB_DFSM_CONFIG_BASE_IDX 0 #define regDB_DFSM_WATERMARK 0 x0631#define regDB_DFSM_WATERMARK_BASE_IDX 0 #define regDB_DFSM_TILES_IN_FLIGHT 0 x0632#define regDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0 #define regDB_DFSM_PRIMS_IN_FLIGHT 0 x0633#define regDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0 #define regDB_DFSM_WATCHDOG 0 x0634#define regDB_DFSM_WATCHDOG_BASE_IDX 0 #define regDB_DFSM_FLUSH_ENABLE 0 x0635#define regDB_DFSM_FLUSH_ENABLE_BASE_IDX 0 #define regDB_DFSM_FLUSH_AUX_EVENT 0 x0636#define regDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0 #define regCC_RB_REDUNDANCY 0 x063c#define regCC_RB_REDUNDANCY_BASE_IDX 0 #define regCC_RB_BACKEND_DISABLE 0 x063d#define regCC_RB_BACKEND_DISABLE_BASE_IDX 0 #define regGB_ADDR_CONFIG 0 x063e#define regGB_ADDR_CONFIG_BASE_IDX 0 #define regGB_BACKEND_MAP 0 x063f#define regGB_BACKEND_MAP_BASE_IDX 0 #define regGB_GPU_ID 0 x0640#define regGB_GPU_ID_BASE_IDX 0 #define regCC_RB_DAISY_CHAIN 0 x0641#define regCC_RB_DAISY_CHAIN_BASE_IDX 0 #define regGB_ADDR_CONFIG_READ 0 x0642#define regGB_ADDR_CONFIG_READ_BASE_IDX 0 #define regGB_TILE_MODE0 0 x0644#define regGB_TILE_MODE0_BASE_IDX 0 #define regGB_TILE_MODE1 0 x0645#define regGB_TILE_MODE1_BASE_IDX 0 #define regGB_TILE_MODE2 0 x0646#define regGB_TILE_MODE2_BASE_IDX 0 #define regGB_TILE_MODE3 0 x0647#define regGB_TILE_MODE3_BASE_IDX 0 #define regGB_TILE_MODE4 0 x0648#define regGB_TILE_MODE4_BASE_IDX 0 #define regGB_TILE_MODE5 0 x0649#define regGB_TILE_MODE5_BASE_IDX 0 #define regGB_TILE_MODE6 0 x064a#define regGB_TILE_MODE6_BASE_IDX 0 #define regGB_TILE_MODE7 0 x064b#define regGB_TILE_MODE7_BASE_IDX 0 #define regGB_TILE_MODE8 0 x064c#define regGB_TILE_MODE8_BASE_IDX 0 #define regGB_TILE_MODE9 0 x064d#define regGB_TILE_MODE9_BASE_IDX 0 #define regGB_TILE_MODE10 0 x064e#define regGB_TILE_MODE10_BASE_IDX 0 #define regGB_TILE_MODE11 0 x064f#define regGB_TILE_MODE11_BASE_IDX 0 #define regGB_TILE_MODE12 0 x0650#define regGB_TILE_MODE12_BASE_IDX 0 #define regGB_TILE_MODE13 0 x0651#define regGB_TILE_MODE13_BASE_IDX 0 #define regGB_TILE_MODE14 0 x0652#define regGB_TILE_MODE14_BASE_IDX 0 #define regGB_TILE_MODE15 0 x0653#define regGB_TILE_MODE15_BASE_IDX 0 #define regGB_TILE_MODE16 0 x0654#define regGB_TILE_MODE16_BASE_IDX 0 #define regGB_TILE_MODE17 0 x0655#define regGB_TILE_MODE17_BASE_IDX 0 #define regGB_TILE_MODE18 0 x0656#define regGB_TILE_MODE18_BASE_IDX 0 #define regGB_TILE_MODE19 0 x0657#define regGB_TILE_MODE19_BASE_IDX 0 #define regGB_TILE_MODE20 0 x0658#define regGB_TILE_MODE20_BASE_IDX 0 #define regGB_TILE_MODE21 0 x0659#define regGB_TILE_MODE21_BASE_IDX 0 #define regGB_TILE_MODE22 0 x065a#define regGB_TILE_MODE22_BASE_IDX 0 #define regGB_TILE_MODE23 0 x065b#define regGB_TILE_MODE23_BASE_IDX 0 #define regGB_TILE_MODE24 0 x065c#define regGB_TILE_MODE24_BASE_IDX 0 #define regGB_TILE_MODE25 0 x065d#define regGB_TILE_MODE25_BASE_IDX 0 #define regGB_TILE_MODE26 0 x065e#define regGB_TILE_MODE26_BASE_IDX 0 #define regGB_TILE_MODE27 0 x065f#define regGB_TILE_MODE27_BASE_IDX 0 #define regGB_TILE_MODE28 0 x0660#define regGB_TILE_MODE28_BASE_IDX 0 #define regGB_TILE_MODE29 0 x0661#define regGB_TILE_MODE29_BASE_IDX 0 #define regGB_TILE_MODE30 0 x0662#define regGB_TILE_MODE30_BASE_IDX 0 #define regGB_TILE_MODE31 0 x0663#define regGB_TILE_MODE31_BASE_IDX 0 #define regGB_MACROTILE_MODE0 0 x0664#define regGB_MACROTILE_MODE0_BASE_IDX 0 #define regGB_MACROTILE_MODE1 0 x0665#define regGB_MACROTILE_MODE1_BASE_IDX 0 #define regGB_MACROTILE_MODE2 0 x0666#define regGB_MACROTILE_MODE2_BASE_IDX 0 #define regGB_MACROTILE_MODE3 0 x0667#define regGB_MACROTILE_MODE3_BASE_IDX 0 #define regGB_MACROTILE_MODE4 0 x0668#define regGB_MACROTILE_MODE4_BASE_IDX 0 #define regGB_MACROTILE_MODE5 0 x0669#define regGB_MACROTILE_MODE5_BASE_IDX 0 #define regGB_MACROTILE_MODE6 0 x066a#define regGB_MACROTILE_MODE6_BASE_IDX 0 #define regGB_MACROTILE_MODE7 0 x066b#define regGB_MACROTILE_MODE7_BASE_IDX 0 #define regGB_MACROTILE_MODE8 0 x066c#define regGB_MACROTILE_MODE8_BASE_IDX 0 #define regGB_MACROTILE_MODE9 0 x066d#define regGB_MACROTILE_MODE9_BASE_IDX 0 #define regGB_MACROTILE_MODE10 0 x066e#define regGB_MACROTILE_MODE10_BASE_IDX 0 #define regGB_MACROTILE_MODE11 0 x066f#define regGB_MACROTILE_MODE11_BASE_IDX 0 #define regGB_MACROTILE_MODE12 0 x0670#define regGB_MACROTILE_MODE12_BASE_IDX 0 #define regGB_MACROTILE_MODE13 0 x0671#define regGB_MACROTILE_MODE13_BASE_IDX 0 #define regGB_MACROTILE_MODE14 0 x0672#define regGB_MACROTILE_MODE14_BASE_IDX 0 #define regGB_MACROTILE_MODE15 0 x0673#define regGB_MACROTILE_MODE15_BASE_IDX 0 #define regCB_HW_CONTROL 0 x0680#define regCB_HW_CONTROL_BASE_IDX 0 #define regCB_HW_CONTROL_1 0 x0681#define regCB_HW_CONTROL_1_BASE_IDX 0 #define regCB_HW_CONTROL_2 0 x0682#define regCB_HW_CONTROL_2_BASE_IDX 0 #define regCB_HW_CONTROL_3 0 x0683#define regCB_HW_CONTROL_3_BASE_IDX 0 #define regCB_HW_MEM_ARBITER_RD 0 x0686#define regCB_HW_MEM_ARBITER_RD_BASE_IDX 0 #define regCB_HW_MEM_ARBITER_WR 0 x0687#define regCB_HW_MEM_ARBITER_WR_BASE_IDX 0 #define regCB_DCC_CONFIG 0 x0688#define regCB_DCC_CONFIG_BASE_IDX 0 #define regGC_USER_RB_REDUNDANCY 0 x06de#define regGC_USER_RB_REDUNDANCY_BASE_IDX 0 #define regGC_USER_RB_BACKEND_DISABLE 0 x06df#define regGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0 // addressBlock: gc_rlcpdec // base address: 0x3b000 #define regRLC_CNTL 0 x4c00#define regRLC_CNTL_BASE_IDX 1 #define regRLC_STAT 0 x4c04#define regRLC_STAT_BASE_IDX 1 #define regRLC_SAFE_MODE 0 x4c05#define regRLC_SAFE_MODE_BASE_IDX 1 #define regRLC_MEM_SLP_CNTL 0 x4c06#define regRLC_MEM_SLP_CNTL_BASE_IDX 1 #define regRLC_RLCV_SAFE_MODE 0 x4c08#define regRLC_RLCV_SAFE_MODE_BASE_IDX 1 #define regRLC_RLCV_COMMAND 0 x4c0a#define regRLC_RLCV_COMMAND_BASE_IDX 1 #define regRLC_REFCLOCK_TIMESTAMP_LSB 0 x4c0c#define regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 #define regRLC_REFCLOCK_TIMESTAMP_MSB 0 x4c0d#define regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 #define regRLC_GPM_TIMER_INT_0 0 x4c0e#define regRLC_GPM_TIMER_INT_0_BASE_IDX 1 #define regRLC_GPM_TIMER_INT_1 0 x4c0f#define regRLC_GPM_TIMER_INT_1_BASE_IDX 1 #define regRLC_GPM_TIMER_INT_2 0 x4c10#define regRLC_GPM_TIMER_INT_2_BASE_IDX 1 #define regRLC_GPM_TIMER_CTRL 0 x4c11#define regRLC_GPM_TIMER_CTRL_BASE_IDX 1 #define regRLC_LB_CNTR_MAX 0 x4c12#define regRLC_LB_CNTR_MAX_BASE_IDX 1 #define regRLC_GPM_TIMER_STAT 0 x4c13#define regRLC_GPM_TIMER_STAT_BASE_IDX 1 #define regRLC_GPM_TIMER_INT_3 0 x4c15#define regRLC_GPM_TIMER_INT_3_BASE_IDX 1 #define regRLC_SERDES_WR_NONCU_MASTER_MASK_1 0 x4c16#define regRLC_SERDES_WR_NONCU_MASTER_MASK_1_BASE_IDX 1 #define regRLC_SERDES_NONCU_MASTER_BUSY_1 0 x4c17
Messung V0.5 in Prozent C=98 H=100 G=98
¤ Dauer der Verarbeitung: 0.552 Sekunden
(vorverarbeitet am 2026-06-06)
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