/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef _gc_9_2_1_OFFSET_HEADER#define _gc_9_2_1_OFFSET_HEADER#define mmSQ_DEBUG_STS_GLOBAL 0x0309#define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0#define mmSQ_DEBUG_STS_GLOBAL2 0x0310#define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0#define mmSQ_DEBUG_STS_GLOBAL3 0x0311#define mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0// addressBlock: gc_grbmdec // base address: 0x8000 #define mmGRBM_CNTL 0x0000#define mmGRBM_CNTL_BASE_IDX 0#define mmGRBM_SKEW_CNTL 0x0001#define mmGRBM_SKEW_CNTL_BASE_IDX 0#define mmGRBM_STATUS2 0x0002#define mmGRBM_STATUS2_BASE_IDX 0#define mmGRBM_PWR_CNTL 0x0003#define mmGRBM_PWR_CNTL_BASE_IDX 0#define mmGRBM_STATUS 0x0004#define mmGRBM_STATUS_BASE_IDX 0#define mmGRBM_STATUS_SE0 0x0005#define mmGRBM_STATUS_SE0_BASE_IDX 0#define mmGRBM_STATUS_SE1 0x0006#define mmGRBM_STATUS_SE1_BASE_IDX 0#define mmGRBM_SOFT_RESET 0x0008#define mmGRBM_SOFT_RESET_BASE_IDX 0#define mmGRBM_GFX_CLKEN_CNTL 0x000c#define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX 0#define mmGRBM_WAIT_IDLE_CLOCKS 0x000d#define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0#define mmGRBM_STATUS_SE2 0x000e#define mmGRBM_STATUS_SE2_BASE_IDX 0#define mmGRBM_STATUS_SE3 0x000f#define mmGRBM_STATUS_SE3_BASE_IDX 0#define mmGRBM_READ_ERROR 0x0016#define mmGRBM_READ_ERROR_BASE_IDX 0#define mmGRBM_READ_ERROR2 0x0017#define mmGRBM_READ_ERROR2_BASE_IDX 0#define mmGRBM_INT_CNTL 0x0018#define mmGRBM_INT_CNTL_BASE_IDX 0#define mmGRBM_TRAP_OP 0x0019#define mmGRBM_TRAP_OP_BASE_IDX 0#define mmGRBM_TRAP_ADDR 0x001a#define mmGRBM_TRAP_ADDR_BASE_IDX 0#define mmGRBM_TRAP_ADDR_MSK 0x001b#define mmGRBM_TRAP_ADDR_MSK_BASE_IDX 0#define mmGRBM_TRAP_WD 0x001c#define mmGRBM_TRAP_WD_BASE_IDX 0#define mmGRBM_TRAP_WD_MSK 0x001d#define mmGRBM_TRAP_WD_MSK_BASE_IDX 0#define mmGRBM_DSM_BYPASS 0x001e#define mmGRBM_DSM_BYPASS_BASE_IDX 0#define mmGRBM_WRITE_ERROR 0x001f#define mmGRBM_WRITE_ERROR_BASE_IDX 0#define mmGRBM_IOV_ERROR 0x0020#define mmGRBM_IOV_ERROR_BASE_IDX 0#define mmGRBM_CHIP_REVISION 0x0021#define mmGRBM_CHIP_REVISION_BASE_IDX 0#define mmGRBM_GFX_CNTL 0x0022#define mmGRBM_GFX_CNTL_BASE_IDX 0#define mmGRBM_RSMU_CFG 0x0023#define mmGRBM_RSMU_CFG_BASE_IDX 0#define mmGRBM_IH_CREDIT 0x0024#define mmGRBM_IH_CREDIT_BASE_IDX 0#define mmGRBM_PWR_CNTL2 0x0025#define mmGRBM_PWR_CNTL2_BASE_IDX 0#define mmGRBM_UTCL2_INVAL_RANGE_START 0x0026#define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0#define mmGRBM_UTCL2_INVAL_RANGE_END 0x0027#define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0#define mmGRBM_RSMU_READ_ERROR 0x0028#define mmGRBM_RSMU_READ_ERROR_BASE_IDX 0#define mmGRBM_CHICKEN_BITS 0x0029#define mmGRBM_CHICKEN_BITS_BASE_IDX 0#define mmGRBM_FENCE_RANGE0 0x002a#define mmGRBM_FENCE_RANGE0_BASE_IDX 0#define mmGRBM_FENCE_RANGE1 0x002b#define mmGRBM_FENCE_RANGE1_BASE_IDX 0#define mmGRBM_NOWHERE 0x003f#define mmGRBM_NOWHERE_BASE_IDX 0#define mmGRBM_SCRATCH_REG0 0x0040#define mmGRBM_SCRATCH_REG0_BASE_IDX 0#define mmGRBM_SCRATCH_REG1 0x0041#define mmGRBM_SCRATCH_REG1_BASE_IDX 0#define mmGRBM_SCRATCH_REG2 0x0042#define mmGRBM_SCRATCH_REG2_BASE_IDX 0#define mmGRBM_SCRATCH_REG3 0x0043#define mmGRBM_SCRATCH_REG3_BASE_IDX 0#define mmGRBM_SCRATCH_REG4 0x0044#define mmGRBM_SCRATCH_REG4_BASE_IDX 0#define mmGRBM_SCRATCH_REG5 0x0045#define mmGRBM_SCRATCH_REG5_BASE_IDX 0#define mmGRBM_SCRATCH_REG6 0x0046#define mmGRBM_SCRATCH_REG6_BASE_IDX 0#define mmGRBM_SCRATCH_REG7 0x0047#define mmGRBM_SCRATCH_REG7_BASE_IDX 0// addressBlock: gc_cpdec // base address: 0x8200 #define mmCP_CPC_STATUS 0x0084#define mmCP_CPC_STATUS_BASE_IDX 0#define mmCP_CPC_BUSY_STAT 0x0085#define mmCP_CPC_BUSY_STAT_BASE_IDX 0#define mmCP_CPC_STALLED_STAT1 0x0086#define mmCP_CPC_STALLED_STAT1_BASE_IDX 0#define mmCP_CPF_STATUS 0x0087#define mmCP_CPF_STATUS_BASE_IDX 0#define mmCP_CPF_BUSY_STAT 0x0088#define mmCP_CPF_BUSY_STAT_BASE_IDX 0#define mmCP_CPF_STALLED_STAT1 0x0089#define mmCP_CPF_STALLED_STAT1_BASE_IDX 0#define mmCP_CPC_GRBM_FREE_COUNT 0x008b#define mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0#define mmCP_MEC_CNTL 0x008d#define mmCP_MEC_CNTL_BASE_IDX 0#define mmCP_MEC_ME1_HEADER_DUMP 0x008e#define mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0#define mmCP_MEC_ME2_HEADER_DUMP 0x008f#define mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0#define mmCP_CPC_SCRATCH_INDEX 0x0090#define mmCP_CPC_SCRATCH_INDEX_BASE_IDX 0#define mmCP_CPC_SCRATCH_DATA 0x0091#define mmCP_CPC_SCRATCH_DATA_BASE_IDX 0#define mmCP_CPF_GRBM_FREE_COUNT 0x0092#define mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0#define mmCP_CPC_HALT_HYST_COUNT 0x00a7#define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX 0#define mmCP_CE_COMPARE_COUNT 0x00c0#define mmCP_CE_COMPARE_COUNT_BASE_IDX 0#define mmCP_CE_DE_COUNT 0x00c1#define mmCP_CE_DE_COUNT_BASE_IDX 0#define mmCP_DE_CE_COUNT 0x00c2#define mmCP_DE_CE_COUNT_BASE_IDX 0#define mmCP_DE_LAST_INVAL_COUNT 0x00c3#define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX 0#define mmCP_DE_DE_COUNT 0x00c4#define mmCP_DE_DE_COUNT_BASE_IDX 0#define mmCP_STALLED_STAT3 0x019c#define mmCP_STALLED_STAT3_BASE_IDX 0#define mmCP_STALLED_STAT1 0x019d#define mmCP_STALLED_STAT1_BASE_IDX 0#define mmCP_STALLED_STAT2 0x019e#define mmCP_STALLED_STAT2_BASE_IDX 0#define mmCP_BUSY_STAT 0x019f#define mmCP_BUSY_STAT_BASE_IDX 0#define mmCP_STAT 0x01a0#define mmCP_STAT_BASE_IDX 0#define mmCP_ME_HEADER_DUMP 0x01a1#define mmCP_ME_HEADER_DUMP_BASE_IDX 0#define mmCP_PFP_HEADER_DUMP 0x01a2#define mmCP_PFP_HEADER_DUMP_BASE_IDX 0#define mmCP_GRBM_FREE_COUNT 0x01a3#define mmCP_GRBM_FREE_COUNT_BASE_IDX 0#define mmCP_CE_HEADER_DUMP 0x01a4#define mmCP_CE_HEADER_DUMP_BASE_IDX 0#define mmCP_PFP_INSTR_PNTR 0x01a5#define mmCP_PFP_INSTR_PNTR_BASE_IDX 0#define mmCP_ME_INSTR_PNTR 0x01a6#define mmCP_ME_INSTR_PNTR_BASE_IDX 0#define mmCP_CE_INSTR_PNTR 0x01a7#define mmCP_CE_INSTR_PNTR_BASE_IDX 0#define mmCP_MEC1_INSTR_PNTR 0x01a8#define mmCP_MEC1_INSTR_PNTR_BASE_IDX 0#define mmCP_MEC2_INSTR_PNTR 0x01a9#define mmCP_MEC2_INSTR_PNTR_BASE_IDX 0#define mmCP_CSF_STAT 0x01b4#define mmCP_CSF_STAT_BASE_IDX 0#define mmCP_ME_CNTL 0x01b6#define mmCP_ME_CNTL_BASE_IDX 0#define mmCP_CNTX_STAT 0x01b8#define mmCP_CNTX_STAT_BASE_IDX 0#define mmCP_ME_PREEMPTION 0x01b9#define mmCP_ME_PREEMPTION_BASE_IDX 0#define mmCP_ROQ_THRESHOLDS 0x01bc#define mmCP_ROQ_THRESHOLDS_BASE_IDX 0#define mmCP_MEQ_STQ_THRESHOLD 0x01bd#define mmCP_MEQ_STQ_THRESHOLD_BASE_IDX 0#define mmCP_RB2_RPTR 0x01be#define mmCP_RB2_RPTR_BASE_IDX 0#define mmCP_RB1_RPTR 0x01bf#define mmCP_RB1_RPTR_BASE_IDX 0#define mmCP_RB0_RPTR 0x01c0#define mmCP_RB0_RPTR_BASE_IDX 0#define mmCP_RB_RPTR 0x01c0#define mmCP_RB_RPTR_BASE_IDX 0#define mmCP_RB_WPTR_DELAY 0x01c1#define mmCP_RB_WPTR_DELAY_BASE_IDX 0#define mmCP_RB_WPTR_POLL_CNTL 0x01c2#define mmCP_RB_WPTR_POLL_CNTL_BASE_IDX 0#define mmCP_ROQ1_THRESHOLDS 0x01d5#define mmCP_ROQ1_THRESHOLDS_BASE_IDX 0#define mmCP_ROQ2_THRESHOLDS 0x01d6#define mmCP_ROQ2_THRESHOLDS_BASE_IDX 0#define mmCP_STQ_THRESHOLDS 0x01d7#define mmCP_STQ_THRESHOLDS_BASE_IDX 0#define mmCP_QUEUE_THRESHOLDS 0x01d8#define mmCP_QUEUE_THRESHOLDS_BASE_IDX 0#define mmCP_MEQ_THRESHOLDS 0x01d9#define mmCP_MEQ_THRESHOLDS_BASE_IDX 0#define mmCP_ROQ_AVAIL 0x01da#define mmCP_ROQ_AVAIL_BASE_IDX 0#define mmCP_STQ_AVAIL 0x01db#define mmCP_STQ_AVAIL_BASE_IDX 0#define mmCP_ROQ2_AVAIL 0x01dc#define mmCP_ROQ2_AVAIL_BASE_IDX 0#define mmCP_MEQ_AVAIL 0x01dd#define mmCP_MEQ_AVAIL_BASE_IDX 0#define mmCP_CMD_INDEX 0x01de#define mmCP_CMD_INDEX_BASE_IDX 0#define mmCP_CMD_DATA 0x01df#define mmCP_CMD_DATA_BASE_IDX 0#define mmCP_ROQ_RB_STAT 0x01e0#define mmCP_ROQ_RB_STAT_BASE_IDX 0#define mmCP_ROQ_IB1_STAT 0x01e1#define mmCP_ROQ_IB1_STAT_BASE_IDX 0#define mmCP_ROQ_IB2_STAT 0x01e2#define mmCP_ROQ_IB2_STAT_BASE_IDX 0#define mmCP_STQ_STAT 0x01e3#define mmCP_STQ_STAT_BASE_IDX 0#define mmCP_STQ_WR_STAT 0x01e4#define mmCP_STQ_WR_STAT_BASE_IDX 0#define mmCP_MEQ_STAT 0x01e5#define mmCP_MEQ_STAT_BASE_IDX 0#define mmCP_CEQ1_AVAIL 0x01e6#define mmCP_CEQ1_AVAIL_BASE_IDX 0#define mmCP_CEQ2_AVAIL 0x01e7#define mmCP_CEQ2_AVAIL_BASE_IDX 0#define mmCP_CE_ROQ_RB_STAT 0x01e8#define mmCP_CE_ROQ_RB_STAT_BASE_IDX 0#define mmCP_CE_ROQ_IB1_STAT 0x01e9#define mmCP_CE_ROQ_IB1_STAT_BASE_IDX 0#define mmCP_CE_ROQ_IB2_STAT 0x01ea#define mmCP_CE_ROQ_IB2_STAT_BASE_IDX 0// addressBlock: gc_padec // base address: 0x8800 #define mmVGT_VTX_VECT_EJECT_REG 0x022c#define mmVGT_VTX_VECT_EJECT_REG_BASE_IDX 0#define mmVGT_DMA_DATA_FIFO_DEPTH 0x022d#define mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0#define mmVGT_DMA_REQ_FIFO_DEPTH 0x022e#define mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x022f#define mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0#define mmVGT_LAST_COPY_STATE 0x0230#define mmVGT_LAST_COPY_STATE_BASE_IDX 0#define mmVGT_CACHE_INVALIDATION 0x0231#define mmVGT_CACHE_INVALIDATION_BASE_IDX 0#define mmVGT_STRMOUT_DELAY 0x0233#define mmVGT_STRMOUT_DELAY_BASE_IDX 0#define mmVGT_FIFO_DEPTHS 0x0234#define mmVGT_FIFO_DEPTHS_BASE_IDX 0#define mmVGT_GS_VERTEX_REUSE 0x0235#define mmVGT_GS_VERTEX_REUSE_BASE_IDX 0#define mmVGT_MC_LAT_CNTL 0x0236#define mmVGT_MC_LAT_CNTL_BASE_IDX 0#define mmIA_CNTL_STATUS 0x0237#define mmIA_CNTL_STATUS_BASE_IDX 0#define mmVGT_CNTL_STATUS 0x023c#define mmVGT_CNTL_STATUS_BASE_IDX 0#define mmWD_CNTL_STATUS 0x023f#define mmWD_CNTL_STATUS_BASE_IDX 0#define mmCC_GC_PRIM_CONFIG 0x0240#define mmCC_GC_PRIM_CONFIG_BASE_IDX 0#define mmGC_USER_PRIM_CONFIG 0x0241#define mmGC_USER_PRIM_CONFIG_BASE_IDX 0#define mmWD_QOS 0x0242#define mmWD_QOS_BASE_IDX 0#define mmWD_UTCL1_CNTL 0x0243#define mmWD_UTCL1_CNTL_BASE_IDX 0#define mmWD_UTCL1_STATUS 0x0244#define mmWD_UTCL1_STATUS_BASE_IDX 0#define mmIA_UTCL1_CNTL 0x0246#define mmIA_UTCL1_CNTL_BASE_IDX 0#define mmIA_UTCL1_STATUS 0x0247#define mmIA_UTCL1_STATUS_BASE_IDX 0#define mmVGT_SYS_CONFIG 0x0263#define mmVGT_SYS_CONFIG_BASE_IDX 0#define mmVGT_VS_MAX_WAVE_ID 0x0268#define mmVGT_VS_MAX_WAVE_ID_BASE_IDX 0#define mmVGT_GS_MAX_WAVE_ID 0x0269#define mmVGT_GS_MAX_WAVE_ID_BASE_IDX 0#define mmGFX_PIPE_CONTROL 0x026d#define mmGFX_PIPE_CONTROL_BASE_IDX 0#define mmCC_GC_SHADER_ARRAY_CONFIG 0x026f#define mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0#define mmGC_USER_SHADER_ARRAY_CONFIG 0x0270#define mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0#define mmVGT_DMA_PRIMITIVE_TYPE 0x0271#define mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0#define mmVGT_DMA_CONTROL 0x0272#define mmVGT_DMA_CONTROL_BASE_IDX 0#define mmVGT_DMA_LS_HS_CONFIG 0x0273#define mmVGT_DMA_LS_HS_CONFIG_BASE_IDX 0#define mmWD_BUF_RESOURCE_1 0x0276#define mmWD_BUF_RESOURCE_1_BASE_IDX 0#define mmWD_BUF_RESOURCE_2 0x0277#define mmWD_BUF_RESOURCE_2_BASE_IDX 0#define mmPA_CL_CNTL_STATUS 0x0284#define mmPA_CL_CNTL_STATUS_BASE_IDX 0#define mmPA_CL_ENHANCE 0x0285#define mmPA_CL_ENHANCE_BASE_IDX 0#define mmPA_SU_CNTL_STATUS 0x0294#define mmPA_SU_CNTL_STATUS_BASE_IDX 0#define mmPA_SC_FIFO_DEPTH_CNTL 0x0295#define mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x02c0#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x02c1#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x02c2#define mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x02c9#define mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0#define mmPA_SC_BINNER_EVENT_CNTL_0 0x02cc#define mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0#define mmPA_SC_BINNER_EVENT_CNTL_1 0x02cd#define mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0#define mmPA_SC_BINNER_EVENT_CNTL_2 0x02ce#define mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0#define mmPA_SC_BINNER_EVENT_CNTL_3 0x02cf#define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0#define mmPA_SC_BINNER_TIMEOUT_COUNTER 0x02d0#define mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0#define mmPA_SC_BINNER_PERF_CNTL_0 0x02d1#define mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0#define mmPA_SC_BINNER_PERF_CNTL_1 0x02d2#define mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0#define mmPA_SC_BINNER_PERF_CNTL_2 0x02d3#define mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0#define mmPA_SC_BINNER_PERF_CNTL_3 0x02d4#define mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0#define mmPA_SC_ENHANCE_2 0x02dc#define mmPA_SC_ENHANCE_2_BASE_IDX 0#define mmPA_SC_FIFO_SIZE 0x02f3#define mmPA_SC_FIFO_SIZE_BASE_IDX 0#define mmPA_SC_IF_FIFO_SIZE 0x02f5#define mmPA_SC_IF_FIFO_SIZE_BASE_IDX 0#define mmPA_SC_PKR_WAVE_TABLE_CNTL 0x02f8#define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0#define mmPA_UTCL1_CNTL1 0x02f9#define mmPA_UTCL1_CNTL1_BASE_IDX 0#define mmPA_UTCL1_CNTL2 0x02fa#define mmPA_UTCL1_CNTL2_BASE_IDX 0#define mmPA_SIDEBAND_REQUEST_DELAYS 0x02fb#define mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0#define mmPA_SC_ENHANCE 0x02fc#define mmPA_SC_ENHANCE_BASE_IDX 0#define mmPA_SC_ENHANCE_1 0x02fd#define mmPA_SC_ENHANCE_1_BASE_IDX 0#define mmPA_SC_DSM_CNTL 0x02fe#define mmPA_SC_DSM_CNTL_BASE_IDX 0#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE 0x02ff#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0// addressBlock: gc_sqdec // base address: 0x8c00 #define mmSQ_CONFIG 0x0300#define mmSQ_CONFIG_BASE_IDX 0#define mmSQC_CONFIG 0x0301#define mmSQC_CONFIG_BASE_IDX 0#define mmLDS_CONFIG 0x0302#define mmLDS_CONFIG_BASE_IDX 0#define mmSQ_RANDOM_WAVE_PRI 0x0303#define mmSQ_RANDOM_WAVE_PRI_BASE_IDX 0#define mmSQ_REG_CREDITS 0x0304#define mmSQ_REG_CREDITS_BASE_IDX 0#define mmSQ_FIFO_SIZES 0x0305#define mmSQ_FIFO_SIZES_BASE_IDX 0#define mmSQ_DSM_CNTL 0x0306#define mmSQ_DSM_CNTL_BASE_IDX 0#define mmSQ_DSM_CNTL2 0x0307#define mmSQ_DSM_CNTL2_BASE_IDX 0#define mmSQ_RUNTIME_CONFIG 0x0308#define mmSQ_RUNTIME_CONFIG_BASE_IDX 0#define mmSH_MEM_BASES 0x030a#define mmSH_MEM_BASES_BASE_IDX 0#define mmSH_MEM_CONFIG 0x030d#define mmSH_MEM_CONFIG_BASE_IDX 0#define mmCC_GC_SHADER_RATE_CONFIG 0x0312#define mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0#define mmGC_USER_SHADER_RATE_CONFIG 0x0313#define mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0#define mmSQ_INTERRUPT_AUTO_MASK 0x0314#define mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0#define mmSQ_INTERRUPT_MSG_CTRL 0x0315#define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0#define mmSQ_UTCL1_CNTL1 0x0317#define mmSQ_UTCL1_CNTL1_BASE_IDX 0#define mmSQ_UTCL1_CNTL2 0x0318#define mmSQ_UTCL1_CNTL2_BASE_IDX 0#define mmSQ_UTCL1_STATUS 0x0319#define mmSQ_UTCL1_STATUS_BASE_IDX 0#define mmSQ_SHADER_TBA_LO 0x031c#define mmSQ_SHADER_TBA_LO_BASE_IDX 0#define mmSQ_SHADER_TBA_HI 0x031d#define mmSQ_SHADER_TBA_HI_BASE_IDX 0#define mmSQ_SHADER_TMA_LO 0x031e#define mmSQ_SHADER_TMA_LO_BASE_IDX 0#define mmSQ_SHADER_TMA_HI 0x031f#define mmSQ_SHADER_TMA_HI_BASE_IDX 0#define mmSQC_DSM_CNTL 0x0320#define mmSQC_DSM_CNTL_BASE_IDX 0#define mmSQC_DSM_CNTLA 0x0321#define mmSQC_DSM_CNTLA_BASE_IDX 0#define mmSQC_DSM_CNTLB 0x0322#define mmSQC_DSM_CNTLB_BASE_IDX 0#define mmSQC_DSM_CNTL2 0x0325#define mmSQC_DSM_CNTL2_BASE_IDX 0#define mmSQC_DSM_CNTL2A 0x0326#define mmSQC_DSM_CNTL2A_BASE_IDX 0#define mmSQC_DSM_CNTL2B 0x0327#define mmSQC_DSM_CNTL2B_BASE_IDX 0#define mmSQ_REG_TIMESTAMP 0x0374#define mmSQ_REG_TIMESTAMP_BASE_IDX 0#define mmSQ_CMD_TIMESTAMP 0x0375#define mmSQ_CMD_TIMESTAMP_BASE_IDX 0#define mmSQ_IND_INDEX 0x0378#define mmSQ_IND_INDEX_BASE_IDX 0#define mmSQ_IND_DATA 0x0379#define mmSQ_IND_DATA_BASE_IDX 0#define mmSQ_CMD 0x037b#define mmSQ_CMD_BASE_IDX 0#define mmSQ_TIME_HI 0x037c#define mmSQ_TIME_HI_BASE_IDX 0#define mmSQ_TIME_LO 0x037d#define mmSQ_TIME_LO_BASE_IDX 0#define mmSQ_DS_0 0x037f#define mmSQ_DS_0_BASE_IDX 0#define mmSQ_DS_1 0x037f#define mmSQ_DS_1_BASE_IDX 0#define mmSQ_EXP_0 0x037f#define mmSQ_EXP_0_BASE_IDX 0#define mmSQ_EXP_1 0x037f#define mmSQ_EXP_1_BASE_IDX 0#define mmSQ_FLAT_0 0x037f#define mmSQ_FLAT_0_BASE_IDX 0#define mmSQ_FLAT_1 0x037f#define mmSQ_FLAT_1_BASE_IDX 0#define mmSQ_GLBL_0 0x037f#define mmSQ_GLBL_0_BASE_IDX 0#define mmSQ_GLBL_1 0x037f#define mmSQ_GLBL_1_BASE_IDX 0#define mmSQ_INST 0x037f#define mmSQ_INST_BASE_IDX 0#define mmSQ_MIMG_0 0x037f#define mmSQ_MIMG_0_BASE_IDX 0#define mmSQ_MIMG_1 0x037f#define mmSQ_MIMG_1_BASE_IDX 0#define mmSQ_MTBUF_0 0x037f#define mmSQ_MTBUF_0_BASE_IDX 0#define mmSQ_MTBUF_1 0x037f#define mmSQ_MTBUF_1_BASE_IDX 0#define mmSQ_MUBUF_0 0x037f#define mmSQ_MUBUF_0_BASE_IDX 0#define mmSQ_MUBUF_1 0x037f#define mmSQ_MUBUF_1_BASE_IDX 0#define mmSQ_SCRATCH_0 0x037f#define mmSQ_SCRATCH_0_BASE_IDX 0#define mmSQ_SCRATCH_1 0x037f#define mmSQ_SCRATCH_1_BASE_IDX 0#define mmSQ_SMEM_0 0x037f#define mmSQ_SMEM_0_BASE_IDX 0#define mmSQ_SMEM_1 0x037f#define mmSQ_SMEM_1_BASE_IDX 0#define mmSQ_SOP1 0x037f#define mmSQ_SOP1_BASE_IDX 0#define mmSQ_SOP2 0x037f#define mmSQ_SOP2_BASE_IDX 0#define mmSQ_SOPC 0x037f#define mmSQ_SOPC_BASE_IDX 0#define mmSQ_SOPK 0x037f#define mmSQ_SOPK_BASE_IDX 0#define mmSQ_SOPP 0x037f#define mmSQ_SOPP_BASE_IDX 0#define mmSQ_VINTRP 0x037f#define mmSQ_VINTRP_BASE_IDX 0#define mmSQ_VOP1 0x037f#define mmSQ_VOP1_BASE_IDX 0#define mmSQ_VOP2 0x037f#define mmSQ_VOP2_BASE_IDX 0#define mmSQ_VOP3P_0 0x037f#define mmSQ_VOP3P_0_BASE_IDX 0#define mmSQ_VOP3P_1 0x037f#define mmSQ_VOP3P_1_BASE_IDX 0#define mmSQ_VOP3_0 0x037f#define mmSQ_VOP3_0_BASE_IDX 0#define mmSQ_VOP3_0_SDST_ENC 0x037f#define mmSQ_VOP3_0_SDST_ENC_BASE_IDX 0#define mmSQ_VOP3_1 0x037f#define mmSQ_VOP3_1_BASE_IDX 0#define mmSQ_VOPC 0x037f#define mmSQ_VOPC_BASE_IDX 0#define mmSQ_VOP_DPP 0x037f#define mmSQ_VOP_DPP_BASE_IDX 0#define mmSQ_VOP_SDWA 0x037f#define mmSQ_VOP_SDWA_BASE_IDX 0#define mmSQ_VOP_SDWA_SDST_ENC 0x037f#define mmSQ_VOP_SDWA_SDST_ENC_BASE_IDX 0#define mmSQ_LB_CTR_CTRL 0x0398#define mmSQ_LB_CTR_CTRL_BASE_IDX 0#define mmSQ_LB_DATA0 0x0399#define mmSQ_LB_DATA0_BASE_IDX 0#define mmSQ_LB_DATA1 0x039a#define mmSQ_LB_DATA1_BASE_IDX 0#define mmSQ_LB_DATA2 0x039b#define mmSQ_LB_DATA2_BASE_IDX 0#define mmSQ_LB_DATA3 0x039c#define mmSQ_LB_DATA3_BASE_IDX 0#define mmSQ_LB_CTR_SEL 0x039d#define mmSQ_LB_CTR_SEL_BASE_IDX 0#define mmSQ_LB_CTR0_CU 0x039e#define mmSQ_LB_CTR0_CU_BASE_IDX 0#define mmSQ_LB_CTR1_CU 0x039f#define mmSQ_LB_CTR1_CU_BASE_IDX 0#define mmSQ_LB_CTR2_CU 0x03a0#define mmSQ_LB_CTR2_CU_BASE_IDX 0#define mmSQ_LB_CTR3_CU 0x03a1#define mmSQ_LB_CTR3_CU_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_CMN 0x03b0#define mmSQ_THREAD_TRACE_WORD_CMN_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_EVENT 0x03b0#define mmSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_INST 0x03b0#define mmSQ_THREAD_TRACE_WORD_INST_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x03b0#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x03b0#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x03b0#define mmSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_MISC 0x03b0#define mmSQ_THREAD_TRACE_WORD_MISC_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x03b0#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x03b0#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x03b0#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x03b0#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x03b0#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x03b0#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_WAVE 0x03b0#define mmSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x03b0#define mmSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x03b1#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x03b1#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x03b1#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX 0#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x03b1#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX 0#define mmSQ_WREXEC_EXEC_HI 0x03b1#define mmSQ_WREXEC_EXEC_HI_BASE_IDX 0#define mmSQ_WREXEC_EXEC_LO 0x03b1#define mmSQ_WREXEC_EXEC_LO_BASE_IDX 0#define mmSQ_BUF_RSRC_WORD0 0x03c0#define mmSQ_BUF_RSRC_WORD0_BASE_IDX 0#define mmSQ_BUF_RSRC_WORD1 0x03c1#define mmSQ_BUF_RSRC_WORD1_BASE_IDX 0#define mmSQ_BUF_RSRC_WORD2 0x03c2#define mmSQ_BUF_RSRC_WORD2_BASE_IDX 0#define mmSQ_BUF_RSRC_WORD3 0x03c3#define mmSQ_BUF_RSRC_WORD3_BASE_IDX 0#define mmSQ_IMG_RSRC_WORD0 0x03c4#define mmSQ_IMG_RSRC_WORD0_BASE_IDX 0#define mmSQ_IMG_RSRC_WORD1 0x03c5#define mmSQ_IMG_RSRC_WORD1_BASE_IDX 0#define mmSQ_IMG_RSRC_WORD2 0x03c6#define mmSQ_IMG_RSRC_WORD2_BASE_IDX 0#define mmSQ_IMG_RSRC_WORD3 0x03c7#define mmSQ_IMG_RSRC_WORD3_BASE_IDX 0#define mmSQ_IMG_RSRC_WORD4 0x03c8#define mmSQ_IMG_RSRC_WORD4_BASE_IDX 0#define mmSQ_IMG_RSRC_WORD5 0x03c9#define mmSQ_IMG_RSRC_WORD5_BASE_IDX 0#define mmSQ_IMG_RSRC_WORD6 0x03ca#define mmSQ_IMG_RSRC_WORD6_BASE_IDX 0#define mmSQ_IMG_RSRC_WORD7 0x03cb#define mmSQ_IMG_RSRC_WORD7_BASE_IDX 0#define mmSQ_IMG_SAMP_WORD0 0x03cc#define mmSQ_IMG_SAMP_WORD0_BASE_IDX 0#define mmSQ_IMG_SAMP_WORD1 0x03cd#define mmSQ_IMG_SAMP_WORD1_BASE_IDX 0#define mmSQ_IMG_SAMP_WORD2 0x03ce#define mmSQ_IMG_SAMP_WORD2_BASE_IDX 0#define mmSQ_IMG_SAMP_WORD3 0x03cf#define mmSQ_IMG_SAMP_WORD3_BASE_IDX 0#define mmSQ_FLAT_SCRATCH_WORD0 0x03d0#define mmSQ_FLAT_SCRATCH_WORD0_BASE_IDX 0#define mmSQ_FLAT_SCRATCH_WORD1 0x03d1#define mmSQ_FLAT_SCRATCH_WORD1_BASE_IDX 0#define mmSQ_M0_GPR_IDX_WORD 0x03d2#define mmSQ_M0_GPR_IDX_WORD_BASE_IDX 0#define mmSQC_ICACHE_UTCL1_CNTL1 0x03d3#define mmSQC_ICACHE_UTCL1_CNTL1_BASE_IDX 0#define mmSQC_ICACHE_UTCL1_CNTL2 0x03d4#define mmSQC_ICACHE_UTCL1_CNTL2_BASE_IDX 0#define mmSQC_DCACHE_UTCL1_CNTL1 0x03d5#define mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX 0#define mmSQC_DCACHE_UTCL1_CNTL2 0x03d6#define mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX 0#define mmSQC_ICACHE_UTCL1_STATUS 0x03d7#define mmSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0
Messung V0.5 C=85 H=86 G=85
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(vorverarbeitet)
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