// SPDX-License-Identifier: MIT
//
// Copyright 2024 Advanced Micro Devices, Inc.
#ifndef DALSMC_H
#define DALSMC_H
#define DALSMC_VERSION 0 x1
// SMU Response Codes:
#define DALSMC_Result_OK 0 x1
#define DALSMC_Result_Failed 0 xFF
#define DALSMC_Result_UnknownCmd 0 xFE
#define DALSMC_Result_CmdRejectedPrereq 0 xFD
#define DALSMC_Result_CmdRejectedBusy 0 xFC
// Message Definitions:
#define DALSMC_MSG_TestMessage 0 x1
#define DALSMC_MSG_GetSmuVersion 0 x2
#define DALSMC_MSG_GetDriverIfVersion 0 x3
#define DALSMC_MSG_GetMsgHeaderVersion 0 x4
#define DALSMC_MSG_SetDalDramAddrHigh 0 x5
#define DALSMC_MSG_SetDalDramAddrLow 0 x6
#define DALSMC_MSG_TransferTableSmu2Dram 0 x7
#define DALSMC_MSG_TransferTableDram2Smu 0 x8
#define DALSMC_MSG_SetHardMinByFreq 0 x9
#define DALSMC_MSG_SetHardMaxByFreq 0 xA
#define DALSMC_MSG_GetDpmFreqByIndex 0 xB
#define DALSMC_MSG_GetDcModeMaxDpmFreq 0 xC
#define DALSMC_MSG_SetMinDeepSleepDcfclk 0 xD
#define DALSMC_MSG_NumOfDisplays 0 xE
#define DALSMC_MSG_SetExternalClientDfCstateAllow 0 xF
#define DALSMC_MSG_BacoAudioD3PME 0 x10
#define DALSMC_MSG_SetFclkSwitchAllow 0 x11
#define DALSMC_MSG_SetCabForUclkPstate 0 x12
#define DALSMC_MSG_SetWorstCaseUclkLatency 0 x13
#define DALSMC_MSG_DcnExitReset 0 x14
#define DALSMC_MSG_ReturnHardMinStatus 0 x15
#define DALSMC_MSG_SetAlwaysWaitDmcubResp 0 x16
#define DALSMC_MSG_IndicateDrrStatus 0 x17 // PMFW 15811
#define DALSMC_MSG_ActiveUclkFclk 0 x18
#define DALSMC_MSG_IdleUclkFclk 0 x19
#define DALSMC_MSG_SetUclkPstateAllow 0 x1A
#define DALSMC_MSG_SubvpUclkFclk 0 x1B
#define DALSMC_MSG_GetNumUmcChannels 0 x1C
#define DALSMC_Message_Count 0 x1D
typedef enum {
FCLK_SWITCH_DISALLOW,
FCLK_SWITCH_ALLOW,
} FclkSwitchAllow_e;
#endif
Messung V0.5 in Prozent C=94 H=95 G=94
¤ Dauer der Verarbeitung: 0.9 Sekunden
(vorverarbeitet am 2026-06-08)
¤
*© Formatika GbR, Deutschland