/* * Copyright 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * #ifndef VI_H#define VI_H#define SDMA0_REGISTER_OFFSET 0 x0 /* not a register */ #define SDMA1_REGISTER_OFFSET 0 x200 /* not a register */ #define SDMA_MAX_INSTANCE 2 #define KFD_VI_SDMA_QUEUE_OFFSET 0 x80 /* not a register */ /* crtc instance offsets */ #define CRTC0_REGISTER_OFFSET (0 x1b9c - 0 x1b9c)#define CRTC1_REGISTER_OFFSET (0 x1d9c - 0 x1b9c)#define CRTC2_REGISTER_OFFSET (0 x1f9c - 0 x1b9c)#define CRTC3_REGISTER_OFFSET (0 x419c - 0 x1b9c)#define CRTC4_REGISTER_OFFSET (0 x439c - 0 x1b9c)#define CRTC5_REGISTER_OFFSET (0 x459c - 0 x1b9c)#define CRTC6_REGISTER_OFFSET (0 x479c - 0 x1b9c)/* dig instance offsets */ #define DIG0_REGISTER_OFFSET (0 x4a00 - 0 x4a00)#define DIG1_REGISTER_OFFSET (0 x4b00 - 0 x4a00)#define DIG2_REGISTER_OFFSET (0 x4c00 - 0 x4a00)#define DIG3_REGISTER_OFFSET (0 x4d00 - 0 x4a00)#define DIG4_REGISTER_OFFSET (0 x4e00 - 0 x4a00)#define DIG5_REGISTER_OFFSET (0 x4f00 - 0 x4a00)#define DIG6_REGISTER_OFFSET (0 x5400 - 0 x4a00)#define DIG7_REGISTER_OFFSET (0 x5600 - 0 x4a00)#define DIG8_REGISTER_OFFSET (0 x5700 - 0 x4a00)/* audio endpt instance offsets */ #define AUD0_REGISTER_OFFSET (0 x17a8 - 0 x17a8)#define AUD1_REGISTER_OFFSET (0 x17ac - 0 x17a8)#define AUD2_REGISTER_OFFSET (0 x17b0 - 0 x17a8)#define AUD3_REGISTER_OFFSET (0 x17b4 - 0 x17a8)#define AUD4_REGISTER_OFFSET (0 x17b8 - 0 x17a8)#define AUD5_REGISTER_OFFSET (0 x17bc - 0 x17a8)#define AUD6_REGISTER_OFFSET (0 x17c0 - 0 x17a8)#define AUD7_REGISTER_OFFSET (0 x17c4 - 0 x17a8)/* hpd instance offsets */ #define HPD0_REGISTER_OFFSET (0 x1898 - 0 x1898)#define HPD1_REGISTER_OFFSET (0 x18a0 - 0 x1898)#define HPD2_REGISTER_OFFSET (0 x18a8 - 0 x1898)#define HPD3_REGISTER_OFFSET (0 x18b0 - 0 x1898)#define HPD4_REGISTER_OFFSET (0 x18b8 - 0 x1898)#define HPD5_REGISTER_OFFSET (0 x18c0 - 0 x1898)#define PIPEID(x) ((x) << 0 )#define MEID(x) ((x) << 2 )#define VMID(x) ((x) << 4 )#define QUEUEID(x) ((x) << 8 )#define MC_SEQ_MISC0__MT__MASK 0 xf0000000#define MC_SEQ_MISC0__MT__GDDR1 0 x10000000#define MC_SEQ_MISC0__MT__DDR2 0 x20000000#define MC_SEQ_MISC0__MT__GDDR3 0 x30000000#define MC_SEQ_MISC0__MT__GDDR4 0 x40000000#define MC_SEQ_MISC0__MT__GDDR5 0 x50000000#define MC_SEQ_MISC0__MT__HBM 0 x60000000#define MC_SEQ_MISC0__MT__DDR3 0 xB0000000/* * PM4 #define PACKET_TYPE0 0 #define PACKET_TYPE1 1 #define PACKET_TYPE2 2 #define PACKET_TYPE3 3 #define CP_PACKET_GET_TYPE(h) (((h) >> 30 ) & 3 )#define CP_PACKET_GET_COUNT(h) (((h) >> 16 ) & 0 x3FFF)#define CP_PACKET0_GET_REG(h) ((h) & 0 xFFFF)#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8 ) & 0 xFF)#define PACKET0(reg, n) ((PACKET_TYPE0 << 30 ) | \0 xFFFF) | \0 x3FFF) << 16 )#define CP_PACKET2 0 x80000000#define PACKET2_PAD_SHIFT 0 #define PACKET2_PAD_MASK (0 x3fffffff << 0 )#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))#define PACKET3(op, n) ((PACKET_TYPE3 << 30 ) | \0 xFF) << 8 ) | \0 x3FFF) << 16 )#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1 )/* Packet 3 types */ #define PACKET3_NOP 0 x10#define PACKET3_SET_BASE 0 x11#define PACKET3_BASE_INDEX(x) ((x) << 0 )#define CE_PARTITION_BASE 3 #define PACKET3_CLEAR_STATE 0 x12#define PACKET3_INDEX_BUFFER_SIZE 0 x13#define PACKET3_DISPATCH_DIRECT 0 x15#define PACKET3_DISPATCH_INDIRECT 0 x16#define PACKET3_ATOMIC_GDS 0 x1D#define PACKET3_ATOMIC_MEM 0 x1E#define PACKET3_OCCLUSION_QUERY 0 x1F#define PACKET3_SET_PREDICATION 0 x20#define PACKET3_REG_RMW 0 x21#define PACKET3_COND_EXEC 0 x22#define PACKET3_PRED_EXEC 0 x23#define PACKET3_DRAW_INDIRECT 0 x24#define PACKET3_DRAW_INDEX_INDIRECT 0 x25#define PACKET3_INDEX_BASE 0 x26#define PACKET3_DRAW_INDEX_2 0 x27#define PACKET3_CONTEXT_CONTROL 0 x28#define PACKET3_INDEX_TYPE 0 x2A#define PACKET3_DRAW_INDIRECT_MULTI 0 x2C#define PACKET3_DRAW_INDEX_AUTO 0 x2D#define PACKET3_NUM_INSTANCES 0 x2F#define PACKET3_DRAW_INDEX_MULTI_AUTO 0 x30#define PACKET3_INDIRECT_BUFFER_CONST 0 x33#define PACKET3_STRMOUT_BUFFER_UPDATE 0 x34#define PACKET3_DRAW_INDEX_OFFSET_2 0 x35#define PACKET3_DRAW_PREAMBLE 0 x36#define PACKET3_WRITE_DATA 0 x37#define WRITE_DATA_DST_SEL(x) ((x) << 8 )/* 0 - register * 1 - memory (sync - via GRBM) * 2 - gl2 * 3 - gds * 4 - reserved * 5 - memory (async - direct) #define WR_ONE_ADDR (1 << 16 )#define WR_CONFIRM (1 << 20 )#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25 )/* 0 - LRU * 1 - Stream #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30 )/* 0 - me * 1 - pfp * 2 - ce #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0 x38#define PACKET3_MEM_SEMAPHORE 0 x39# define PACKET3_SEM_USE_MAILBOX (0 x1 << 16 )# define PACKET3_SEM_SEL_SIGNAL_TYPE (0 x1 << 20 ) /* 0 = increment, 1 = write 1 */ # define PACKET3_SEM_CLIENT_CODE ((x) << 24 ) /* 0 = CP, 1 = CB, 2 = DB */ # define PACKET3_SEM_SEL_SIGNAL (0 x6 << 29 )# define PACKET3_SEM_SEL_WAIT (0 x7 << 29 )#define PACKET3_WAIT_REG_MEM 0 x3C#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0 )/* 0 - always * 1 - < * 2 - <= * 3 - == * 4 - != * 5 - >= * 6 - > #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4 )/* 0 - reg * 1 - mem #define WAIT_REG_MEM_OPERATION(x) ((x) << 6 )/* 0 - wait_reg_mem * 1 - wr_wait_wr_reg #define WAIT_REG_MEM_ENGINE(x) ((x) << 8 )/* 0 - me * 1 - pfp #define PACKET3_INDIRECT_BUFFER 0 x3F#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22 )#define INDIRECT_BUFFER_VALID (1 << 23 )#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28 )/* 0 - LRU * 1 - Stream * 2 - Bypass #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21 )#define PACKET3_COPY_DATA 0 x40#define PACKET3_PFP_SYNC_ME 0 x42#define PACKET3_SURFACE_SYNC 0 x43# define PACKET3_DEST_BASE_0_ENA (1 << 0 )# define PACKET3_DEST_BASE_1_ENA (1 << 1 )# define PACKET3_CB0_DEST_BASE_ENA (1 << 6 )# define PACKET3_CB1_DEST_BASE_ENA (1 << 7 )# define PACKET3_CB2_DEST_BASE_ENA (1 << 8 )# define PACKET3_CB3_DEST_BASE_ENA (1 << 9 )# define PACKET3_CB4_DEST_BASE_ENA (1 << 10 )# define PACKET3_CB5_DEST_BASE_ENA (1 << 11 )# define PACKET3_CB6_DEST_BASE_ENA (1 << 12 )# define PACKET3_CB7_DEST_BASE_ENA (1 << 13 )# define PACKET3_DB_DEST_BASE_ENA (1 << 14 )# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15 )# define PACKET3_TC_VOL_ACTION_ENA (1 << 16 ) /* L2 */ # define PACKET3_TC_WB_ACTION_ENA (1 << 18 ) /* L2 */ # define PACKET3_DEST_BASE_2_ENA (1 << 19 )# define PACKET3_DEST_BASE_3_ENA (1 << 21 )# define PACKET3_TCL1_ACTION_ENA (1 << 22 )# define PACKET3_TC_ACTION_ENA (1 << 23 ) /* L2 */ # define PACKET3_CB_ACTION_ENA (1 << 25 )# define PACKET3_DB_ACTION_ENA (1 << 26 )# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27 )# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28 )# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29 )#define PACKET3_COND_WRITE 0 x45#define PACKET3_EVENT_WRITE 0 x46#define EVENT_TYPE(x) ((x) << 0 )#define EVENT_INDEX(x) ((x) << 8 )/* 0 - any non-TS event * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* * 2 - SAMPLE_PIPELINESTAT * 3 - SAMPLE_STREAMOUTSTAT* * 4 - *S_PARTIAL_FLUSH * 5 - EOP events * 6 - EOS events #define PACKET3_EVENT_WRITE_EOP 0 x47#define EOP_TCL1_VOL_ACTION_EN (1 << 12 )#define EOP_TC_VOL_ACTION_EN (1 << 13 ) /* L2 */ #define EOP_TC_WB_ACTION_EN (1 << 15 ) /* L2 */ #define EOP_TCL1_ACTION_EN (1 << 16 )#define EOP_TC_ACTION_EN (1 << 17 ) /* L2 */ #define EOP_TCL2_VOLATILE (1 << 24 )#define EOP_CACHE_POLICY(x) ((x) << 25 )/* 0 - LRU * 1 - Stream * 2 - Bypass #define EOP_EXEC (1 << 28 ) /* For Trailing Fence */ #define DATA_SEL(x) ((x) << 29 )/* 0 - discard * 1 - send low 32bit data * 2 - send 64bit data * 3 - send 64bit GPU counter value * 4 - send 64bit sys counter value #define INT_SEL(x) ((x) << 24 )/* 0 - none * 1 - interrupt only (DATA_SEL = 0) * 2 - interrupt when data write is confirmed #define DST_SEL(x) ((x) << 16 )/* 0 - MC * 1 - TC/L2 #define PACKET3_EVENT_WRITE_EOS 0 x48#define PACKET3_RELEASE_MEM 0 x49#define PACKET3_PREAMBLE_CNTL 0 x4A# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28 )# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28 )#define PACKET3_DMA_DATA 0 x50/* 1. header * 2. CONTROL * 3. SRC_ADDR_LO or DATA [31:0] * 4. SRC_ADDR_HI [31:0] * 5. DST_ADDR_LO [31:0] * 6. DST_ADDR_HI [7:0] * 7. COMMAND [30:21] | BYTE_COUNT [20:0] /* CONTROL */ # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0 )/* 0 - ME * 1 - PFP # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13 )/* 0 - LRU * 1 - Stream * 2 - Bypass # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15 )# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20 )/* 0 - DST_ADDR using DAS * 1 - GDS * 3 - DST_ADDR using L2 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25 )/* 0 - LRU * 1 - Stream * 2 - Bypass # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27 )# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29 )/* 0 - SRC_ADDR using SAS * 1 - GDS * 2 - DATA * 3 - SRC_ADDR using L2 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31 )/* COMMAND */ # define PACKET3_DMA_DATA_DIS_WC (1 << 21 )# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22 )/* 0 - none * 1 - 8 in 16 * 2 - 8 in 32 * 3 - 8 in 64 # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24 )/* 0 - none * 1 - 8 in 16 * 2 - 8 in 32 * 3 - 8 in 64 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26 )/* 0 - memory * 1 - register # define PACKET3_DMA_DATA_CMD_DAS (1 << 27 )/* 0 - memory * 1 - register # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28 )# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29 )# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30 )#define PACKET3_ACQUIRE_MEM 0 x58#define PACKET3_REWIND 0 x59#define PACKET3_LOAD_UCONFIG_REG 0 x5E#define PACKET3_LOAD_SH_REG 0 x5F#define PACKET3_LOAD_CONFIG_REG 0 x60#define PACKET3_LOAD_CONTEXT_REG 0 x61#define PACKET3_SET_CONFIG_REG 0 x68#define PACKET3_SET_CONFIG_REG_START 0 x00002000#define PACKET3_SET_CONFIG_REG_END 0 x00002c00#define PACKET3_SET_CONTEXT_REG 0 x69#define PACKET3_SET_CONTEXT_REG_START 0 x0000a000#define PACKET3_SET_CONTEXT_REG_END 0 x0000a400#define PACKET3_SET_CONTEXT_REG_INDIRECT 0 x73#define PACKET3_SET_SH_REG 0 x76#define PACKET3_SET_SH_REG_START 0 x00002c00#define PACKET3_SET_SH_REG_END 0 x00003000#define PACKET3_SET_SH_REG_OFFSET 0 x77#define PACKET3_SET_QUEUE_REG 0 x78#define PACKET3_SET_UCONFIG_REG 0 x79#define PACKET3_SET_UCONFIG_REG_START 0 x0000c000#define PACKET3_SET_UCONFIG_REG_END 0 x0000c400#define PACKET3_SCRATCH_RAM_WRITE 0 x7D#define PACKET3_SCRATCH_RAM_READ 0 x7E#define PACKET3_LOAD_CONST_RAM 0 x80#define PACKET3_WRITE_CONST_RAM 0 x81#define PACKET3_DUMP_CONST_RAM 0 x83#define PACKET3_INCREMENT_CE_COUNTER 0 x84#define PACKET3_INCREMENT_DE_COUNTER 0 x85#define PACKET3_WAIT_ON_CE_COUNTER 0 x86#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0 x88#define PACKET3_SWITCH_BUFFER 0 x8B#define PACKET3_FRAME_CONTROL 0 x90# define FRAME_CMD(x) ((x) << 28 )/* * x=0: tmz_begin * x=1: tmz_end #define PACKET3_SET_RESOURCES 0 xA0/* 1. header * 2. CONTROL * 3. QUEUE_MASK_LO [31:0] * 4. QUEUE_MASK_HI [31:0] * 5. GWS_MASK_LO [31:0] * 6. GWS_MASK_HI [31:0] * 7. OAC_MASK [15:0] * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0 )# define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16 )# define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29 )#define PACKET3_MAP_QUEUES 0 xA2/* 1. header * 2. CONTROL * 3. CONTROL2 * 4. MQD_ADDR_LO [31:0] * 5. MQD_ADDR_HI [31:0] * 6. WPTR_ADDR_LO [31:0] * 7. WPTR_ADDR_HI [31:0] /* CONTROL */ # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4 )# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8 )# define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21 )# define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24 )# define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26 )# define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29 )/* CONTROL2 */ # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1 )# define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2 )# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 26 )# define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 29 )# define PACKET3_MAP_QUEUES_ME(x) ((x) << 31 )#define PACKET3_UNMAP_QUEUES 0 xA3/* 1. header * 2. CONTROL * 3. CONTROL2 * 4. CONTROL3 * 5. CONTROL4 * 6. CONTROL5 /* CONTROL */ # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0 )/* 0 - PREEMPT_QUEUES * 1 - RESET_QUEUES * 2 - DISABLE_PROCESS_QUEUES * 3 - PREEMPT_QUEUES_NO_UNMAP # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4 )# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26 )# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29 )/* CONTROL2a */ # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0 )/* CONTROL2b */ # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2 )/* CONTROL3a */ # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2 )/* CONTROL3b */ # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0 )/* CONTROL4 */ # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2 )/* CONTROL5 */ # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2 )#define PACKET3_QUERY_STATUS 0 xA4/* 1. header * 2. CONTROL * 3. CONTROL2 * 4. ADDR_LO [31:0] * 5. ADDR_HI [31:0] * 6. DATA_LO [31:0] * 7. DATA_HI [31:0] /* CONTROL */ # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0 )# define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28 )# define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30 )/* CONTROL2a */ # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0 )/* CONTROL2b */ # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2 )# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25 )#define VCE_CMD_NO_OP 0 x00000000#define VCE_CMD_END 0 x00000001#define VCE_CMD_IB 0 x00000002#define VCE_CMD_FENCE 0 x00000003#define VCE_CMD_TRAP 0 x00000004#define VCE_CMD_IB_AUTO 0 x00000005#define VCE_CMD_SEMAPHORE 0 x00000006#define VCE_CMD_IB_VM 0 x00000102#define VCE_CMD_WAIT_GE 0 x00000106#define VCE_CMD_UPDATE_PTB 0 x00000107#define VCE_CMD_FLUSH_TLB 0 x00000108/* HEVC ENC */ #define HEVC_ENC_CMD_NO_OP 0 x00000000#define HEVC_ENC_CMD_END 0 x00000001#define HEVC_ENC_CMD_FENCE 0 x00000003#define HEVC_ENC_CMD_TRAP 0 x00000004#define HEVC_ENC_CMD_IB_VM 0 x00000102#define HEVC_ENC_CMD_WAIT_GE 0 x00000106#define HEVC_ENC_CMD_UPDATE_PTB 0 x00000107#define HEVC_ENC_CMD_FLUSH_TLB 0 x00000108/* mmPA_SC_RASTER_CONFIG mask */ #define RB_MAP_PKR0(x) ((x) << 0 )#define RB_MAP_PKR0_MASK (0 x3 << 0 )#define RB_MAP_PKR1(x) ((x) << 2 )#define RB_MAP_PKR1_MASK (0 x3 << 2 )#define RB_XSEL2(x) ((x) << 4 )#define RB_XSEL2_MASK (0 x3 << 4 )#define RB_XSEL (1 << 6 )#define RB_YSEL (1 << 7 )#define PKR_MAP(x) ((x) << 8 )#define PKR_MAP_MASK (0 x3 << 8 )#define PKR_XSEL(x) ((x) << 10 )#define PKR_XSEL_MASK (0 x3 << 10 )#define PKR_YSEL(x) ((x) << 12 )#define PKR_YSEL_MASK (0 x3 << 12 )#define SC_MAP(x) ((x) << 16 )#define SC_MAP_MASK (0 x3 << 16 )#define SC_XSEL(x) ((x) << 18 )#define SC_XSEL_MASK (0 x3 << 18 )#define SC_YSEL(x) ((x) << 20 )#define SC_YSEL_MASK (0 x3 << 20 )#define SE_MAP(x) ((x) << 24 )#define SE_MAP_MASK (0 x3 << 24 )#define SE_XSEL(x) ((x) << 26 )#define SE_XSEL_MASK (0 x3 << 26 )#define SE_YSEL(x) ((x) << 28 )#define SE_YSEL_MASK (0 x3 << 28 )/* mmPA_SC_RASTER_CONFIG_1 mask */ #define SE_PAIR_MAP(x) ((x) << 0 )#define SE_PAIR_MAP_MASK (0 x3 << 0 )#define SE_PAIR_XSEL(x) ((x) << 2 )#define SE_PAIR_XSEL_MASK (0 x3 << 2 )#define SE_PAIR_YSEL(x) ((x) << 4 )#define SE_PAIR_YSEL_MASK (0 x3 << 4 )#endif
Messung V0.5 in Prozent C=95 H=93 G=93
¤ Dauer der Verarbeitung: 0.12 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
