/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
*/
#ifndef STM32MP25_RCC_H
#define STM32MP25_RCC_H
#define RCC_SECCFGR0 0 x0
#define RCC_SECCFGR1 0 x4
#define RCC_SECCFGR2 0 x8
#define RCC_SECCFGR3 0 xC
#define RCC_PRIVCFGR0 0 x10
#define RCC_PRIVCFGR1 0 x14
#define RCC_PRIVCFGR2 0 x18
#define RCC_PRIVCFGR3 0 x1C
#define RCC_RCFGLOCKR0 0 x20
#define RCC_RCFGLOCKR1 0 x24
#define RCC_RCFGLOCKR2 0 x28
#define RCC_RCFGLOCKR3 0 x2C
#define RCC_R0CIDCFGR 0 x30
#define RCC_R0SEMCR 0 x34
#define RCC_R1CIDCFGR 0 x38
#define RCC_R1SEMCR 0 x3C
#define RCC_R2CIDCFGR 0 x40
#define RCC_R2SEMCR 0 x44
#define RCC_R3CIDCFGR 0 x48
#define RCC_R3SEMCR 0 x4C
#define RCC_R4CIDCFGR 0 x50
#define RCC_R4SEMCR 0 x54
#define RCC_R5CIDCFGR 0 x58
#define RCC_R5SEMCR 0 x5C
#define RCC_R6CIDCFGR 0 x60
#define RCC_R6SEMCR 0 x64
#define RCC_R7CIDCFGR 0 x68
#define RCC_R7SEMCR 0 x6C
#define RCC_R8CIDCFGR 0 x70
#define RCC_R8SEMCR 0 x74
#define RCC_R9CIDCFGR 0 x78
#define RCC_R9SEMCR 0 x7C
#define RCC_R10CIDCFGR 0 x80
#define RCC_R10SEMCR 0 x84
#define RCC_R11CIDCFGR 0 x88
#define RCC_R11SEMCR 0 x8C
#define RCC_R12CIDCFGR 0 x90
#define RCC_R12SEMCR 0 x94
#define RCC_R13CIDCFGR 0 x98
#define RCC_R13SEMCR 0 x9C
#define RCC_R14CIDCFGR 0 xA0
#define RCC_R14SEMCR 0 xA4
#define RCC_R15CIDCFGR 0 xA8
#define RCC_R15SEMCR 0 xAC
#define RCC_R16CIDCFGR 0 xB0
#define RCC_R16SEMCR 0 xB4
#define RCC_R17CIDCFGR 0 xB8
#define RCC_R17SEMCR 0 xBC
#define RCC_R18CIDCFGR 0 xC0
#define RCC_R18SEMCR 0 xC4
#define RCC_R19CIDCFGR 0 xC8
#define RCC_R19SEMCR 0 xCC
#define RCC_R20CIDCFGR 0 xD0
#define RCC_R20SEMCR 0 xD4
#define RCC_R21CIDCFGR 0 xD8
#define RCC_R21SEMCR 0 xDC
#define RCC_R22CIDCFGR 0 xE0
#define RCC_R22SEMCR 0 xE4
#define RCC_R23CIDCFGR 0 xE8
#define RCC_R23SEMCR 0 xEC
#define RCC_R24CIDCFGR 0 xF0
#define RCC_R24SEMCR 0 xF4
#define RCC_R25CIDCFGR 0 xF8
#define RCC_R25SEMCR 0 xFC
#define RCC_R26CIDCFGR 0 x100
#define RCC_R26SEMCR 0 x104
#define RCC_R27CIDCFGR 0 x108
#define RCC_R27SEMCR 0 x10C
#define RCC_R28CIDCFGR 0 x110
#define RCC_R28SEMCR 0 x114
#define RCC_R29CIDCFGR 0 x118
#define RCC_R29SEMCR 0 x11C
#define RCC_R30CIDCFGR 0 x120
#define RCC_R30SEMCR 0 x124
#define RCC_R31CIDCFGR 0 x128
#define RCC_R31SEMCR 0 x12C
#define RCC_R32CIDCFGR 0 x130
#define RCC_R32SEMCR 0 x134
#define RCC_R33CIDCFGR 0 x138
#define RCC_R33SEMCR 0 x13C
#define RCC_R34CIDCFGR 0 x140
#define RCC_R34SEMCR 0 x144
#define RCC_R35CIDCFGR 0 x148
#define RCC_R35SEMCR 0 x14C
#define RCC_R36CIDCFGR 0 x150
#define RCC_R36SEMCR 0 x154
#define RCC_R37CIDCFGR 0 x158
#define RCC_R37SEMCR 0 x15C
#define RCC_R38CIDCFGR 0 x160
#define RCC_R38SEMCR 0 x164
#define RCC_R39CIDCFGR 0 x168
#define RCC_R39SEMCR 0 x16C
#define RCC_R40CIDCFGR 0 x170
#define RCC_R40SEMCR 0 x174
#define RCC_R41CIDCFGR 0 x178
#define RCC_R41SEMCR 0 x17C
#define RCC_R42CIDCFGR 0 x180
#define RCC_R42SEMCR 0 x184
#define RCC_R43CIDCFGR 0 x188
#define RCC_R43SEMCR 0 x18C
#define RCC_R44CIDCFGR 0 x190
#define RCC_R44SEMCR 0 x194
#define RCC_R45CIDCFGR 0 x198
#define RCC_R45SEMCR 0 x19C
#define RCC_R46CIDCFGR 0 x1A0
#define RCC_R46SEMCR 0 x1A4
#define RCC_R47CIDCFGR 0 x1A8
#define RCC_R47SEMCR 0 x1AC
#define RCC_R48CIDCFGR 0 x1B0
#define RCC_R48SEMCR 0 x1B4
#define RCC_R49CIDCFGR 0 x1B8
#define RCC_R49SEMCR 0 x1BC
#define RCC_R50CIDCFGR 0 x1C0
#define RCC_R50SEMCR 0 x1C4
#define RCC_R51CIDCFGR 0 x1C8
#define RCC_R51SEMCR 0 x1CC
#define RCC_R52CIDCFGR 0 x1D0
#define RCC_R52SEMCR 0 x1D4
#define RCC_R53CIDCFGR 0 x1D8
#define RCC_R53SEMCR 0 x1DC
#define RCC_R54CIDCFGR 0 x1E0
#define RCC_R54SEMCR 0 x1E4
#define RCC_R55CIDCFGR 0 x1E8
#define RCC_R55SEMCR 0 x1EC
#define RCC_R56CIDCFGR 0 x1F0
#define RCC_R56SEMCR 0 x1F4
#define RCC_R57CIDCFGR 0 x1F8
#define RCC_R57SEMCR 0 x1FC
#define RCC_R58CIDCFGR 0 x200
#define RCC_R58SEMCR 0 x204
#define RCC_R59CIDCFGR 0 x208
#define RCC_R59SEMCR 0 x20C
#define RCC_R60CIDCFGR 0 x210
#define RCC_R60SEMCR 0 x214
#define RCC_R61CIDCFGR 0 x218
#define RCC_R61SEMCR 0 x21C
#define RCC_R62CIDCFGR 0 x220
#define RCC_R62SEMCR 0 x224
#define RCC_R63CIDCFGR 0 x228
#define RCC_R63SEMCR 0 x22C
#define RCC_R64CIDCFGR 0 x230
#define RCC_R64SEMCR 0 x234
#define RCC_R65CIDCFGR 0 x238
#define RCC_R65SEMCR 0 x23C
#define RCC_R66CIDCFGR 0 x240
#define RCC_R66SEMCR 0 x244
#define RCC_R67CIDCFGR 0 x248
#define RCC_R67SEMCR 0 x24C
#define RCC_R68CIDCFGR 0 x250
#define RCC_R68SEMCR 0 x254
#define RCC_R69CIDCFGR 0 x258
#define RCC_R69SEMCR 0 x25C
#define RCC_R70CIDCFGR 0 x260
#define RCC_R70SEMCR 0 x264
#define RCC_R71CIDCFGR 0 x268
#define RCC_R71SEMCR 0 x26C
#define RCC_R72CIDCFGR 0 x270
#define RCC_R72SEMCR 0 x274
#define RCC_R73CIDCFGR 0 x278
#define RCC_R73SEMCR 0 x27C
#define RCC_R74CIDCFGR 0 x280
#define RCC_R74SEMCR 0 x284
#define RCC_R75CIDCFGR 0 x288
#define RCC_R75SEMCR 0 x28C
#define RCC_R76CIDCFGR 0 x290
#define RCC_R76SEMCR 0 x294
#define RCC_R77CIDCFGR 0 x298
#define RCC_R77SEMCR 0 x29C
#define RCC_R78CIDCFGR 0 x2A0
#define RCC_R78SEMCR 0 x2A4
#define RCC_R79CIDCFGR 0 x2A8
#define RCC_R79SEMCR 0 x2AC
#define RCC_R80CIDCFGR 0 x2B0
#define RCC_R80SEMCR 0 x2B4
#define RCC_R81CIDCFGR 0 x2B8
#define RCC_R81SEMCR 0 x2BC
#define RCC_R82CIDCFGR 0 x2C0
#define RCC_R82SEMCR 0 x2C4
#define RCC_R83CIDCFGR 0 x2C8
#define RCC_R83SEMCR 0 x2CC
#define RCC_R84CIDCFGR 0 x2D0
#define RCC_R84SEMCR 0 x2D4
#define RCC_R85CIDCFGR 0 x2D8
#define RCC_R85SEMCR 0 x2DC
#define RCC_R86CIDCFGR 0 x2E0
#define RCC_R86SEMCR 0 x2E4
#define RCC_R87CIDCFGR 0 x2E8
#define RCC_R87SEMCR 0 x2EC
#define RCC_R88CIDCFGR 0 x2F0
#define RCC_R88SEMCR 0 x2F4
#define RCC_R89CIDCFGR 0 x2F8
#define RCC_R89SEMCR 0 x2FC
#define RCC_R90CIDCFGR 0 x300
#define RCC_R90SEMCR 0 x304
#define RCC_R91CIDCFGR 0 x308
#define RCC_R91SEMCR 0 x30C
#define RCC_R92CIDCFGR 0 x310
#define RCC_R92SEMCR 0 x314
#define RCC_R93CIDCFGR 0 x318
#define RCC_R93SEMCR 0 x31C
#define RCC_R94CIDCFGR 0 x320
#define RCC_R94SEMCR 0 x324
#define RCC_R95CIDCFGR 0 x328
#define RCC_R95SEMCR 0 x32C
#define RCC_R96CIDCFGR 0 x330
#define RCC_R96SEMCR 0 x334
#define RCC_R97CIDCFGR 0 x338
#define RCC_R97SEMCR 0 x33C
#define RCC_R98CIDCFGR 0 x340
#define RCC_R98SEMCR 0 x344
#define RCC_R99CIDCFGR 0 x348
#define RCC_R99SEMCR 0 x34C
#define RCC_R100CIDCFGR 0 x350
#define RCC_R100SEMCR 0 x354
#define RCC_R101CIDCFGR 0 x358
#define RCC_R101SEMCR 0 x35C
#define RCC_R102CIDCFGR 0 x360
#define RCC_R102SEMCR 0 x364
#define RCC_R103CIDCFGR 0 x368
#define RCC_R103SEMCR 0 x36C
#define RCC_R104CIDCFGR 0 x370
#define RCC_R104SEMCR 0 x374
#define RCC_R105CIDCFGR 0 x378
#define RCC_R105SEMCR 0 x37C
#define RCC_R106CIDCFGR 0 x380
#define RCC_R106SEMCR 0 x384
#define RCC_R107CIDCFGR 0 x388
#define RCC_R107SEMCR 0 x38C
#define RCC_R108CIDCFGR 0 x390
#define RCC_R108SEMCR 0 x394
#define RCC_R109CIDCFGR 0 x398
#define RCC_R109SEMCR 0 x39C
#define RCC_R110CIDCFGR 0 x3A0
#define RCC_R110SEMCR 0 x3A4
#define RCC_R111CIDCFGR 0 x3A8
#define RCC_R111SEMCR 0 x3AC
#define RCC_R112CIDCFGR 0 x3B0
#define RCC_R112SEMCR 0 x3B4
#define RCC_R113CIDCFGR 0 x3B8
#define RCC_R113SEMCR 0 x3BC
#define RCC_GRSTCSETR 0 x400
#define RCC_C1RSTCSETR 0 x404
#define RCC_C1P1RSTCSETR 0 x408
#define RCC_C2RSTCSETR 0 x40C
#define RCC_HWRSTSCLRR 0 x410
#define RCC_C1HWRSTSCLRR 0 x414
#define RCC_C2HWRSTSCLRR 0 x418
#define RCC_C1BOOTRSTSSETR 0 x41C
#define RCC_C1BOOTRSTSCLRR 0 x420
#define RCC_C2BOOTRSTSSETR 0 x424
#define RCC_C2BOOTRSTSCLRR 0 x428
#define RCC_C1SREQSETR 0 x42C
#define RCC_C1SREQCLRR 0 x430
#define RCC_CPUBOOTCR 0 x434
#define RCC_STBYBOOTCR 0 x438
#define RCC_LEGBOOTCR 0 x43C
#define RCC_BDCR 0 x440
#define RCC_D3DCR 0 x444
#define RCC_D3DSR 0 x448
#define RCC_RDCR 0 x44C
#define RCC_C1MSRDCR 0 x450
#define RCC_PWRLPDLYCR 0 x454
#define RCC_C1CIESETR 0 x458
#define RCC_C1CIFCLRR 0 x45C
#define RCC_C2CIESETR 0 x460
#define RCC_C2CIFCLRR 0 x464
#define RCC_IWDGC1FZSETR 0 x468
#define RCC_IWDGC1FZCLRR 0 x46C
#define RCC_IWDGC1CFGSETR 0 x470
#define RCC_IWDGC1CFGCLRR 0 x474
#define RCC_IWDGC2FZSETR 0 x478
#define RCC_IWDGC2FZCLRR 0 x47C
#define RCC_IWDGC2CFGSETR 0 x480
#define RCC_IWDGC2CFGCLRR 0 x484
#define RCC_IWDGC3CFGSETR 0 x488
#define RCC_IWDGC3CFGCLRR 0 x48C
#define RCC_C3CFGR 0 x490
#define RCC_MCO1CFGR 0 x494
#define RCC_MCO2CFGR 0 x498
#define RCC_OCENSETR 0 x49C
#define RCC_OCENCLRR 0 x4A0
#define RCC_OCRDYR 0 x4A4
#define RCC_HSICFGR 0 x4A8
#define RCC_MSICFGR 0 x4AC
#define RCC_RTCDIVR 0 x4B0
#define RCC_APB1DIVR 0 x4B4
#define RCC_APB2DIVR 0 x4B8
#define RCC_APB3DIVR 0 x4BC
#define RCC_APB4DIVR 0 x4C0
#define RCC_APBDBGDIVR 0 x4C4
#define RCC_TIMG1PRER 0 x4C8
#define RCC_TIMG2PRER 0 x4CC
#define RCC_LSMCUDIVR 0 x4D0
#define RCC_DDRCPCFGR 0 x4D4
#define RCC_DDRCAPBCFGR 0 x4D8
#define RCC_DDRPHYCAPBCFGR 0 x4DC
#define RCC_DDRPHYCCFGR 0 x4E0
#define RCC_DDRCFGR 0 x4E4
#define RCC_DDRITFCFGR 0 x4E8
#define RCC_SYSRAMCFGR 0 x4F0
#define RCC_VDERAMCFGR 0 x4F4
#define RCC_SRAM1CFGR 0 x4F8
#define RCC_SRAM2CFGR 0 x4FC
#define RCC_RETRAMCFGR 0 x500
#define RCC_BKPSRAMCFGR 0 x504
#define RCC_LPSRAM1CFGR 0 x508
#define RCC_LPSRAM2CFGR 0 x50C
#define RCC_LPSRAM3CFGR 0 x510
#define RCC_OSPI1CFGR 0 x514
#define RCC_OSPI2CFGR 0 x518
#define RCC_FMCCFGR 0 x51C
#define RCC_DBGCFGR 0 x520
#define RCC_STM500CFGR 0 x524
#define RCC_ETRCFGR 0 x528
#define RCC_GPIOACFGR 0 x52C
#define RCC_GPIOBCFGR 0 x530
#define RCC_GPIOCCFGR 0 x534
#define RCC_GPIODCFGR 0 x538
#define RCC_GPIOECFGR 0 x53C
#define RCC_GPIOFCFGR 0 x540
#define RCC_GPIOGCFGR 0 x544
#define RCC_GPIOHCFGR 0 x548
#define RCC_GPIOICFGR 0 x54C
#define RCC_GPIOJCFGR 0 x550
#define RCC_GPIOKCFGR 0 x554
#define RCC_GPIOZCFGR 0 x558
#define RCC_HPDMA1CFGR 0 x55C
#define RCC_HPDMA2CFGR 0 x560
#define RCC_HPDMA3CFGR 0 x564
#define RCC_LPDMACFGR 0 x568
#define RCC_HSEMCFGR 0 x56C
#define RCC_IPCC1CFGR 0 x570
#define RCC_IPCC2CFGR 0 x574
#define RCC_RTCCFGR 0 x578
#define RCC_SYSCPU1CFGR 0 x580
#define RCC_BSECCFGR 0 x584
#define RCC_IS2MCFGR 0 x58C
#define RCC_PLL2CFGR1 0 x590
#define RCC_PLL2CFGR2 0 x594
#define RCC_PLL2CFGR3 0 x598
#define RCC_PLL2CFGR4 0 x59C
#define RCC_PLL2CFGR5 0 x5A0
#define RCC_PLL2CFGR6 0 x5A8
#define RCC_PLL2CFGR7 0 x5AC
#define RCC_PLL3CFGR1 0 x5B8
#define RCC_PLL3CFGR2 0 x5BC
#define RCC_PLL3CFGR3 0 x5C0
#define RCC_PLL3CFGR4 0 x5C4
#define RCC_PLL3CFGR5 0 x5C8
#define RCC_PLL3CFGR6 0 x5D0
#define RCC_PLL3CFGR7 0 x5D4
#define RCC_HSIFMONCR 0 x5E0
#define RCC_HSIFVALR 0 x5E4
#define RCC_TIM1CFGR 0 x700
#define RCC_TIM2CFGR 0 x704
#define RCC_TIM3CFGR 0 x708
#define RCC_TIM4CFGR 0 x70C
#define RCC_TIM5CFGR 0 x710
#define RCC_TIM6CFGR 0 x714
#define RCC_TIM7CFGR 0 x718
#define RCC_TIM8CFGR 0 x71C
#define RCC_TIM10CFGR 0 x720
#define RCC_TIM11CFGR 0 x724
#define RCC_TIM12CFGR 0 x728
#define RCC_TIM13CFGR 0 x72C
#define RCC_TIM14CFGR 0 x730
#define RCC_TIM15CFGR 0 x734
#define RCC_TIM16CFGR 0 x738
#define RCC_TIM17CFGR 0 x73C
#define RCC_TIM20CFGR 0 x740
#define RCC_LPTIM1CFGR 0 x744
#define RCC_LPTIM2CFGR 0 x748
#define RCC_LPTIM3CFGR 0 x74C
#define RCC_LPTIM4CFGR 0 x750
#define RCC_LPTIM5CFGR 0 x754
#define RCC_SPI1CFGR 0 x758
#define RCC_SPI2CFGR 0 x75C
#define RCC_SPI3CFGR 0 x760
#define RCC_SPI4CFGR 0 x764
#define RCC_SPI5CFGR 0 x768
#define RCC_SPI6CFGR 0 x76C
#define RCC_SPI7CFGR 0 x770
#define RCC_SPI8CFGR 0 x774
#define RCC_SPDIFRXCFGR 0 x778
#define RCC_USART1CFGR 0 x77C
#define RCC_USART2CFGR 0 x780
#define RCC_USART3CFGR 0 x784
#define RCC_UART4CFGR 0 x788
#define RCC_UART5CFGR 0 x78C
#define RCC_USART6CFGR 0 x790
#define RCC_UART7CFGR 0 x794
#define RCC_UART8CFGR 0 x798
#define RCC_UART9CFGR 0 x79C
#define RCC_LPUART1CFGR 0 x7A0
#define RCC_I2C1CFGR 0 x7A4
#define RCC_I2C2CFGR 0 x7A8
#define RCC_I2C3CFGR 0 x7AC
#define RCC_I2C4CFGR 0 x7B0
#define RCC_I2C5CFGR 0 x7B4
#define RCC_I2C6CFGR 0 x7B8
#define RCC_I2C7CFGR 0 x7BC
#define RCC_I2C8CFGR 0 x7C0
#define RCC_SAI1CFGR 0 x7C4
#define RCC_SAI2CFGR 0 x7C8
#define RCC_SAI3CFGR 0 x7CC
#define RCC_SAI4CFGR 0 x7D0
#define RCC_MDF1CFGR 0 x7D8
#define RCC_ADF1CFGR 0 x7DC
#define RCC_FDCANCFGR 0 x7E0
#define RCC_HDPCFGR 0 x7E4
#define RCC_ADC12CFGR 0 x7E8
#define RCC_ADC3CFGR 0 x7EC
#define RCC_ETH1CFGR 0 x7F0
#define RCC_ETH2CFGR 0 x7F4
#define RCC_USBHCFGR 0 x7FC
#define RCC_USB2PHY1CFGR 0 x800
#define RCC_USB2PHY2CFGR 0 x804
#define RCC_USB3DRCFGR 0 x808
#define RCC_USB3PCIEPHYCFGR 0 x80C
#define RCC_PCIECFGR 0 x810
#define RCC_USBTCCFGR 0 x814
#define RCC_ETHSWCFGR 0 x818
#define RCC_ETHSWACMCFGR 0 x81C
#define RCC_ETHSWACMMSGCFGR 0 x820
#define RCC_STGENCFGR 0 x824
#define RCC_SDMMC1CFGR 0 x830
#define RCC_SDMMC2CFGR 0 x834
#define RCC_SDMMC3CFGR 0 x838
#define RCC_GPUCFGR 0 x83C
#define RCC_LTDCCFGR 0 x840
#define RCC_DSICFGR 0 x844
#define RCC_LVDSCFGR 0 x850
#define RCC_CSICFGR 0 x858
#define RCC_DCMIPPCFGR 0 x85C
#define RCC_CCICFGR 0 x860
#define RCC_VDECCFGR 0 x864
#define RCC_VENCCFGR 0 x868
#define RCC_RNGCFGR 0 x870
#define RCC_PKACFGR 0 x874
#define RCC_SAESCFGR 0 x878
#define RCC_HASHCFGR 0 x87C
#define RCC_CRYP1CFGR 0 x880
#define RCC_CRYP2CFGR 0 x884
#define RCC_IWDG1CFGR 0 x888
#define RCC_IWDG2CFGR 0 x88C
#define RCC_IWDG3CFGR 0 x890
#define RCC_IWDG4CFGR 0 x894
#define RCC_IWDG5CFGR 0 x898
#define RCC_WWDG1CFGR 0 x89C
#define RCC_WWDG2CFGR 0 x8A0
#define RCC_VREFCFGR 0 x8A8
#define RCC_DTSCFGR 0 x8AC
#define RCC_CRCCFGR 0 x8B4
#define RCC_SERCCFGR 0 x8B8
#define RCC_OSPIIOMCFGR 0 x8BC
#define RCC_GICV2MCFGR 0 x8C0
#define RCC_I3C1CFGR 0 x8C8
#define RCC_I3C2CFGR 0 x8CC
#define RCC_I3C3CFGR 0 x8D0
#define RCC_I3C4CFGR 0 x8D4
#define RCC_MUXSELCFGR 0 x1000
#define RCC_XBAR0CFGR 0 x1018
#define RCC_XBAR1CFGR 0 x101C
#define RCC_XBAR2CFGR 0 x1020
#define RCC_XBAR3CFGR 0 x1024
#define RCC_XBAR4CFGR 0 x1028
#define RCC_XBAR5CFGR 0 x102C
#define RCC_XBAR6CFGR 0 x1030
#define RCC_XBAR7CFGR 0 x1034
#define RCC_XBAR8CFGR 0 x1038
#define RCC_XBAR9CFGR 0 x103C
#define RCC_XBAR10CFGR 0 x1040
#define RCC_XBAR11CFGR 0 x1044
#define RCC_XBAR12CFGR 0 x1048
#define RCC_XBAR13CFGR 0 x104C
#define RCC_XBAR14CFGR 0 x1050
#define RCC_XBAR15CFGR 0 x1054
#define RCC_XBAR16CFGR 0 x1058
#define RCC_XBAR17CFGR 0 x105C
#define RCC_XBAR18CFGR 0 x1060
#define RCC_XBAR19CFGR 0 x1064
#define RCC_XBAR20CFGR 0 x1068
#define RCC_XBAR21CFGR 0 x106C
#define RCC_XBAR22CFGR 0 x1070
#define RCC_XBAR23CFGR 0 x1074
#define RCC_XBAR24CFGR 0 x1078
#define RCC_XBAR25CFGR 0 x107C
#define RCC_XBAR26CFGR 0 x1080
#define RCC_XBAR27CFGR 0 x1084
#define RCC_XBAR28CFGR 0 x1088
#define RCC_XBAR29CFGR 0 x108C
#define RCC_XBAR30CFGR 0 x1090
#define RCC_XBAR31CFGR 0 x1094
#define RCC_XBAR32CFGR 0 x1098
#define RCC_XBAR33CFGR 0 x109C
#define RCC_XBAR34CFGR 0 x10A0
#define RCC_XBAR35CFGR 0 x10A4
#define RCC_XBAR36CFGR 0 x10A8
#define RCC_XBAR37CFGR 0 x10AC
#define RCC_XBAR38CFGR 0 x10B0
#define RCC_XBAR39CFGR 0 x10B4
#define RCC_XBAR40CFGR 0 x10B8
#define RCC_XBAR41CFGR 0 x10BC
#define RCC_XBAR42CFGR 0 x10C0
#define RCC_XBAR43CFGR 0 x10C4
#define RCC_XBAR44CFGR 0 x10C8
#define RCC_XBAR45CFGR 0 x10CC
#define RCC_XBAR46CFGR 0 x10D0
#define RCC_XBAR47CFGR 0 x10D4
#define RCC_XBAR48CFGR 0 x10D8
#define RCC_XBAR49CFGR 0 x10DC
#define RCC_XBAR50CFGR 0 x10E0
#define RCC_XBAR51CFGR 0 x10E4
#define RCC_XBAR52CFGR 0 x10E8
#define RCC_XBAR53CFGR 0 x10EC
#define RCC_XBAR54CFGR 0 x10F0
#define RCC_XBAR55CFGR 0 x10F4
#define RCC_XBAR56CFGR 0 x10F8
#define RCC_XBAR57CFGR 0 x10FC
#define RCC_XBAR58CFGR 0 x1100
#define RCC_XBAR59CFGR 0 x1104
#define RCC_XBAR60CFGR 0 x1108
#define RCC_XBAR61CFGR 0 x110C
#define RCC_XBAR62CFGR 0 x1110
#define RCC_XBAR63CFGR 0 x1114
#define RCC_PREDIV0CFGR 0 x1118
#define RCC_PREDIV1CFGR 0 x111C
#define RCC_PREDIV2CFGR 0 x1120
#define RCC_PREDIV3CFGR 0 x1124
#define RCC_PREDIV4CFGR 0 x1128
#define RCC_PREDIV5CFGR 0 x112C
#define RCC_PREDIV6CFGR 0 x1130
#define RCC_PREDIV7CFGR 0 x1134
#define RCC_PREDIV8CFGR 0 x1138
#define RCC_PREDIV9CFGR 0 x113C
#define RCC_PREDIV10CFGR 0 x1140
#define RCC_PREDIV11CFGR 0 x1144
#define RCC_PREDIV12CFGR 0 x1148
#define RCC_PREDIV13CFGR 0 x114C
#define RCC_PREDIV14CFGR 0 x1150
#define RCC_PREDIV15CFGR 0 x1154
#define RCC_PREDIV16CFGR 0 x1158
#define RCC_PREDIV17CFGR 0 x115C
#define RCC_PREDIV18CFGR 0 x1160
#define RCC_PREDIV19CFGR 0 x1164
#define RCC_PREDIV20CFGR 0 x1168
#define RCC_PREDIV21CFGR 0 x116C
#define RCC_PREDIV22CFGR 0 x1170
#define RCC_PREDIV23CFGR 0 x1174
#define RCC_PREDIV24CFGR 0 x1178
#define RCC_PREDIV25CFGR 0 x117C
#define RCC_PREDIV26CFGR 0 x1180
#define RCC_PREDIV27CFGR 0 x1184
#define RCC_PREDIV28CFGR 0 x1188
#define RCC_PREDIV29CFGR 0 x118C
#define RCC_PREDIV30CFGR 0 x1190
#define RCC_PREDIV31CFGR 0 x1194
#define RCC_PREDIV32CFGR 0 x1198
#define RCC_PREDIV33CFGR 0 x119C
#define RCC_PREDIV34CFGR 0 x11A0
#define RCC_PREDIV35CFGR 0 x11A4
#define RCC_PREDIV36CFGR 0 x11A8
#define RCC_PREDIV37CFGR 0 x11AC
#define RCC_PREDIV38CFGR 0 x11B0
#define RCC_PREDIV39CFGR 0 x11B4
#define RCC_PREDIV40CFGR 0 x11B8
#define RCC_PREDIV41CFGR 0 x11BC
#define RCC_PREDIV42CFGR 0 x11C0
#define RCC_PREDIV43CFGR 0 x11C4
#define RCC_PREDIV44CFGR 0 x11C8
#define RCC_PREDIV45CFGR 0 x11CC
#define RCC_PREDIV46CFGR 0 x11D0
#define RCC_PREDIV47CFGR 0 x11D4
#define RCC_PREDIV48CFGR 0 x11D8
#define RCC_PREDIV49CFGR 0 x11DC
#define RCC_PREDIV50CFGR 0 x11E0
#define RCC_PREDIV51CFGR 0 x11E4
#define RCC_PREDIV52CFGR 0 x11E8
#define RCC_PREDIV53CFGR 0 x11EC
#define RCC_PREDIV54CFGR 0 x11F0
#define RCC_PREDIV55CFGR 0 x11F4
#define RCC_PREDIV56CFGR 0 x11F8
#define RCC_PREDIV57CFGR 0 x11FC
#define RCC_PREDIV58CFGR 0 x1200
#define RCC_PREDIV59CFGR 0 x1204
#define RCC_PREDIV60CFGR 0 x1208
#define RCC_PREDIV61CFGR 0 x120C
#define RCC_PREDIV62CFGR 0 x1210
#define RCC_PREDIV63CFGR 0 x1214
#define RCC_PREDIVSR1 0 x1218
#define RCC_PREDIVSR2 0 x121C
#define RCC_FINDIV0CFGR 0 x1224
#define RCC_FINDIV1CFGR 0 x1228
#define RCC_FINDIV2CFGR 0 x122C
#define RCC_FINDIV3CFGR 0 x1230
#define RCC_FINDIV4CFGR 0 x1234
#define RCC_FINDIV5CFGR 0 x1238
#define RCC_FINDIV6CFGR 0 x123C
#define RCC_FINDIV7CFGR 0 x1240
#define RCC_FINDIV8CFGR 0 x1244
#define RCC_FINDIV9CFGR 0 x1248
#define RCC_FINDIV10CFGR 0 x124C
#define RCC_FINDIV11CFGR 0 x1250
#define RCC_FINDIV12CFGR 0 x1254
#define RCC_FINDIV13CFGR 0 x1258
#define RCC_FINDIV14CFGR 0 x125C
#define RCC_FINDIV15CFGR 0 x1260
#define RCC_FINDIV16CFGR 0 x1264
#define RCC_FINDIV17CFGR 0 x1268
#define RCC_FINDIV18CFGR 0 x126C
#define RCC_FINDIV19CFGR 0 x1270
#define RCC_FINDIV20CFGR 0 x1274
#define RCC_FINDIV21CFGR 0 x1278
#define RCC_FINDIV22CFGR 0 x127C
#define RCC_FINDIV23CFGR 0 x1280
#define RCC_FINDIV24CFGR 0 x1284
#define RCC_FINDIV25CFGR 0 x1288
#define RCC_FINDIV26CFGR 0 x128C
#define RCC_FINDIV27CFGR 0 x1290
#define RCC_FINDIV28CFGR 0 x1294
#define RCC_FINDIV29CFGR 0 x1298
#define RCC_FINDIV30CFGR 0 x129C
#define RCC_FINDIV31CFGR 0 x12A0
#define RCC_FINDIV32CFGR 0 x12A4
#define RCC_FINDIV33CFGR 0 x12A8
#define RCC_FINDIV34CFGR 0 x12AC
#define RCC_FINDIV35CFGR 0 x12B0
#define RCC_FINDIV36CFGR 0 x12B4
#define RCC_FINDIV37CFGR 0 x12B8
#define RCC_FINDIV38CFGR 0 x12BC
#define RCC_FINDIV39CFGR 0 x12C0
#define RCC_FINDIV40CFGR 0 x12C4
#define RCC_FINDIV41CFGR 0 x12C8
#define RCC_FINDIV42CFGR 0 x12CC
#define RCC_FINDIV43CFGR 0 x12D0
#define RCC_FINDIV44CFGR 0 x12D4
#define RCC_FINDIV45CFGR 0 x12D8
#define RCC_FINDIV46CFGR 0 x12DC
#define RCC_FINDIV47CFGR 0 x12E0
#define RCC_FINDIV48CFGR 0 x12E4
#define RCC_FINDIV49CFGR 0 x12E8
#define RCC_FINDIV50CFGR 0 x12EC
#define RCC_FINDIV51CFGR 0 x12F0
#define RCC_FINDIV52CFGR 0 x12F4
#define RCC_FINDIV53CFGR 0 x12F8
#define RCC_FINDIV54CFGR 0 x12FC
#define RCC_FINDIV55CFGR 0 x1300
#define RCC_FINDIV56CFGR 0 x1304
#define RCC_FINDIV57CFGR 0 x1308
#define RCC_FINDIV58CFGR 0 x130C
#define RCC_FINDIV59CFGR 0 x1310
#define RCC_FINDIV60CFGR 0 x1314
#define RCC_FINDIV61CFGR 0 x1318
#define RCC_FINDIV62CFGR 0 x131C
#define RCC_FINDIV63CFGR 0 x1320
#define RCC_FINDIVSR1 0 x1324
#define RCC_FINDIVSR2 0 x1328
#define RCC_FCALCOBS0CFGR 0 x1340
#define RCC_FCALCOBS1CFGR 0 x1344
#define RCC_FCALCREFCFGR 0 x1348
#define RCC_FCALCCR1 0 x134C
#define RCC_FCALCCR2 0 x1354
#define RCC_FCALCSR 0 x1358
#define RCC_PLL4CFGR1 0 x1360
#define RCC_PLL4CFGR2 0 x1364
#define RCC_PLL4CFGR3 0 x1368
#define RCC_PLL4CFGR4 0 x136C
#define RCC_PLL4CFGR5 0 x1370
#define RCC_PLL4CFGR6 0 x1378
#define RCC_PLL4CFGR7 0 x137C
#define RCC_PLL5CFGR1 0 x1388
#define RCC_PLL5CFGR2 0 x138C
#define RCC_PLL5CFGR3 0 x1390
#define RCC_PLL5CFGR4 0 x1394
#define RCC_PLL5CFGR5 0 x1398
#define RCC_PLL5CFGR6 0 x13A0
#define RCC_PLL5CFGR7 0 x13A4
#define RCC_PLL6CFGR1 0 x13B0
#define RCC_PLL6CFGR2 0 x13B4
#define RCC_PLL6CFGR3 0 x13B8
#define RCC_PLL6CFGR4 0 x13BC
#define RCC_PLL6CFGR5 0 x13C0
#define RCC_PLL6CFGR6 0 x13C8
#define RCC_PLL6CFGR7 0 x13CC
#define RCC_PLL7CFGR1 0 x13D8
#define RCC_PLL7CFGR2 0 x13DC
#define RCC_PLL7CFGR3 0 x13E0
#define RCC_PLL7CFGR4 0 x13E4
#define RCC_PLL7CFGR5 0 x13E8
#define RCC_PLL7CFGR6 0 x13F0
#define RCC_PLL7CFGR7 0 x13F4
#define RCC_PLL8CFGR1 0 x1400
#define RCC_PLL8CFGR2 0 x1404
#define RCC_PLL8CFGR3 0 x1408
#define RCC_PLL8CFGR4 0 x140C
#define RCC_PLL8CFGR5 0 x1410
#define RCC_PLL8CFGR6 0 x1418
#define RCC_PLL8CFGR7 0 x141C
#define RCC_VERR 0 xFFF4
#define RCC_IDR 0 xFFF8
#define RCC_SIDR 0 xFFFC
#endif /* STM32MP25_RCC_H */
Messung V0.5 in Prozent C=98 H=97 G=97
¤ Dauer der Verarbeitung: 0.14 Sekunden
(vorverarbeitet am 2026-06-07)
¤
*© Formatika GbR, Deutschland