// SPDX-License-Identifier: GPL-2.0 /* * StarFive JH7100 Clock Generator Driver * * Copyright 2021 Ahmad Fatoum, Pengutronix * Copyright (C) 2021 Glider bv * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> #include <linux/clk-provider.h>#include <linux/device.h>#include <linux/init.h>#include <linux/mod_devicetable.h>#include <linux/platform_device.h>#include <dt-bindings/clock/starfive-jh7100.h>#include "clk-starfive-jh71x0.h" /* external clocks */ #define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0 )#define JH7100_CLK_OSC_AUD (JH7100_CLK_END + 1 )#define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2 )#define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3 )static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {"cpundbus_root" , 0 , 4 ,"dla_root" , 0 , 3 ,"dsp_root" , 0 , 4 ,"gmacusb_root" , 0 , 3 ,"perh0_root" , 0 , 2 ,"perh1_root" , 0 , 2 ,"vin_root" , 0 , 3 ,"vout_root" , 0 , 3 ,"audio_root" , 0 , 8 , JH7100_CLK_PLL0_OUT),"cdechifi4_root" , 0 , 3 ,"cdec_root" , 0 , 3 ,"voutbus_root" , 0 , 3 ,"cpunbus_root_div" , 2 , JH7100_CLK_CPUNDBUS_ROOT),"dsp_root_div" , 4 , JH7100_CLK_DSP_ROOT),"perh0_src" , 4 , JH7100_CLK_PERH0_ROOT),"perh1_src" , 4 , JH7100_CLK_PERH1_ROOT),"pll0_testout" , 0 , 31 , JH7100_CLK_PERH0_SRC),"pll1_testout" , 0 , 31 , JH7100_CLK_DLA_ROOT),"pll2_testout" , 0 , 31 , JH7100_CLK_PERH1_SRC),"pll2_refclk" , 0 , 2 ,"cpu_core" , 8 , JH7100_CLK_CPUNBUS_ROOT_DIV),"cpu_axi" , 8 , JH7100_CLK_CPU_CORE),"ahb_bus" , 8 , JH7100_CLK_CPUNBUS_ROOT_DIV),"apb1_bus" , 8 , JH7100_CLK_AHB_BUS),"apb2_bus" , 8 , JH7100_CLK_AHB_BUS),"dom3ahb_bus" , CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),"dom7ahb_bus" , CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),"u74_core0" , CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),"u74_core1" , CLK_IS_CRITICAL, 8 , JH7100_CLK_CPU_CORE),"u74_axi" , CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),"u74rtc_toggle" , CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),"sgdma2p_axi" , 0 , JH7100_CLK_CPU_AXI),"dma2pnoc_axi" , 0 , JH7100_CLK_CPU_AXI),"sgdma2p_ahb" , 0 , JH7100_CLK_AHB_BUS),"dla_bus" , 4 , JH7100_CLK_DLA_ROOT),"dla_axi" , 0 , JH7100_CLK_DLA_BUS),"dlanoc_axi" , 0 , JH7100_CLK_DLA_BUS),"dla_apb" , 0 , JH7100_CLK_APB1_BUS),"vp6_core" , 0 , 4 , JH7100_CLK_DSP_ROOT_DIV),"vp6bus_src" , 4 , JH7100_CLK_DSP_ROOT),"vp6_axi" , 0 , 4 , JH7100_CLK_VP6BUS_SRC),"vcdecbus_src" , 4 , JH7100_CLK_CDECHIFI4_ROOT),"vdec_bus" , 8 , JH7100_CLK_VCDECBUS_SRC),"vdec_axi" , 0 , JH7100_CLK_VDEC_BUS),"vdecbrg_mainclk" , 0 , JH7100_CLK_VDEC_BUS),"vdec_bclk" , 0 , 8 , JH7100_CLK_VCDECBUS_SRC),"vdec_cclk" , 0 , 8 , JH7100_CLK_CDEC_ROOT),"vdec_apb" , 0 , JH7100_CLK_APB1_BUS),"jpeg_axi" , 0 , 8 , JH7100_CLK_CPUNBUS_ROOT_DIV),"jpeg_cclk" , 0 , 8 , JH7100_CLK_CPUNBUS_ROOT_DIV),"jpeg_apb" , 0 , JH7100_CLK_APB1_BUS),"gc300_2x" , 0 , 8 , JH7100_CLK_CDECHIFI4_ROOT),"gc300_ahb" , 0 , JH7100_CLK_AHB_BUS),"jpcgc300_axibus" , 8 , JH7100_CLK_VCDECBUS_SRC),"gc300_axi" , 0 , JH7100_CLK_JPCGC300_AXIBUS),"jpcgc300_mainclk" , 0 , JH7100_CLK_JPCGC300_AXIBUS),"venc_bus" , 8 , JH7100_CLK_VCDECBUS_SRC),"venc_axi" , 0 , JH7100_CLK_VENC_BUS),"vencbrg_mainclk" , 0 , JH7100_CLK_VENC_BUS),"venc_bclk" , 0 , 8 , JH7100_CLK_VCDECBUS_SRC),"venc_cclk" , 0 , 8 , JH7100_CLK_CDEC_ROOT),"venc_apb" , 0 , JH7100_CLK_APB1_BUS),"ddrpll_div2" , CLK_IS_CRITICAL, 2 , JH7100_CLK_PLL1_OUT),"ddrpll_div4" , CLK_IS_CRITICAL, 2 ,"ddrpll_div8" , CLK_IS_CRITICAL, 2 ,"ddrosc_div2" , CLK_IS_CRITICAL, 2 , JH7100_CLK_OSC_SYS),"ddrc0" , CLK_IS_CRITICAL, 4 ,"ddrc1" , CLK_IS_CRITICAL, 4 ,"ddrphy_apb" , 0 , JH7100_CLK_APB1_BUS),"noc_rob" , 8 , JH7100_CLK_CPUNBUS_ROOT_DIV),"noc_cog" , 8 , JH7100_CLK_DLA_ROOT),"nne_ahb" , 0 , JH7100_CLK_AHB_BUS),"nnebus_src1" , 4 , JH7100_CLK_DSP_ROOT),"nne_bus" , 0 , 2 ,"nne_axi" , 0 , JH7100_CLK_NNE_BUS),"nnenoc_axi" , 0 , JH7100_CLK_NNE_BUS),"dlaslv_axi" , 0 , JH7100_CLK_NNE_BUS),"dspx2c_axi" , CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),"hifi4_src" , 4 , JH7100_CLK_CDECHIFI4_ROOT),"hifi4_corefree" , 8 , JH7100_CLK_HIFI4_SRC),"hifi4_core" , 0 , JH7100_CLK_HIFI4_COREFREE),"hifi4_bus" , 8 , JH7100_CLK_HIFI4_COREFREE),"hifi4_axi" , 0 , JH7100_CLK_HIFI4_BUS),"hifi4noc_axi" , 0 , JH7100_CLK_HIFI4_BUS),"sgdma1p_bus" , 8 , JH7100_CLK_CPUNBUS_ROOT_DIV),"sgdma1p_axi" , 0 , JH7100_CLK_SGDMA1P_BUS),"dma1p_axi" , 0 , JH7100_CLK_SGDMA1P_BUS),"x2c_axi" , CLK_IS_CRITICAL, 8 , JH7100_CLK_CPUNBUS_ROOT_DIV),"usb_bus" , 8 , JH7100_CLK_CPUNBUS_ROOT_DIV),"usb_axi" , 0 , JH7100_CLK_USB_BUS),"usbnoc_axi" , 0 , JH7100_CLK_USB_BUS),"usbphy_rootdiv" , 4 , JH7100_CLK_GMACUSB_ROOT),"usbphy_125m" , 0 , 8 , JH7100_CLK_USBPHY_ROOTDIV),"usbphy_plldiv25m" , 0 , 32 ,"usbphy_25m" , 0 , 2 ,"audio_div" , JH7100_CLK_AUDIO_ROOT),"audio_src" , 0 , JH7100_CLK_AUDIO_DIV),"audio_12288" , 0 , JH7100_CLK_OSC_AUD),"vin_src" , 0 , 4 , JH7100_CLK_VIN_ROOT),"isp0_bus" , 8 , JH7100_CLK_VIN_SRC),"isp0_axi" , 0 , JH7100_CLK_ISP0_BUS),"isp0noc_axi" , 0 , JH7100_CLK_ISP0_BUS),"ispslv_axi" , 0 , JH7100_CLK_ISP0_BUS),"isp1_bus" , 8 , JH7100_CLK_VIN_SRC),"isp1_axi" , 0 , JH7100_CLK_ISP1_BUS),"isp1noc_axi" , 0 , JH7100_CLK_ISP1_BUS),"vin_bus" , 8 , JH7100_CLK_VIN_SRC),"vin_axi" , 0 , JH7100_CLK_VIN_BUS),"vinnoc_axi" , 0 , JH7100_CLK_VIN_BUS),"vout_src" , 0 , 4 , JH7100_CLK_VOUT_ROOT),"dispbus_src" , 4 , JH7100_CLK_VOUTBUS_ROOT),"disp_bus" , 4 , JH7100_CLK_DISPBUS_SRC),"disp_axi" , 0 , JH7100_CLK_DISP_BUS),"dispnoc_axi" , 0 , JH7100_CLK_DISP_BUS),"sdio0_ahb" , 0 , JH7100_CLK_AHB_BUS),"sdio0_cclkint" , 0 , 24 , JH7100_CLK_PERH0_SRC),"sdio0_cclkint_inv" , JH7100_CLK_SDIO0_CCLKINT),"sdio1_ahb" , 0 , JH7100_CLK_AHB_BUS),"sdio1_cclkint" , 0 , 24 , JH7100_CLK_PERH1_SRC),"sdio1_cclkint_inv" , JH7100_CLK_SDIO1_CCLKINT),"gmac_ahb" , 0 , JH7100_CLK_AHB_BUS),"gmac_root_div" , 8 , JH7100_CLK_GMACUSB_ROOT),"gmac_ptp_refclk" , 0 , 31 , JH7100_CLK_GMAC_ROOT_DIV),"gmac_gtxclk" , 0 , 255 , JH7100_CLK_GMAC_ROOT_DIV),"gmac_rmii_txclk" , 0 , 8 , JH7100_CLK_GMAC_RMII_REF),"gmac_rmii_rxclk" , 0 , 8 , JH7100_CLK_GMAC_RMII_REF),"gmac_tx" , CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 3 ,"gmac_tx_inv" , JH7100_CLK_GMAC_TX),"gmac_rx_pre" , 0 , 2 ,"gmac_rx_inv" , JH7100_CLK_GMAC_RX_PRE),"gmac_rmii" , 0 , JH7100_CLK_GMAC_RMII_REF),"gmac_tophyref" , 0 , 127 , JH7100_CLK_GMAC_ROOT_DIV),"spi2ahb_ahb" , 0 , JH7100_CLK_AHB_BUS),"spi2ahb_core" , 0 , 31 , JH7100_CLK_PERH0_SRC),"ezmaster_ahb" , 0 , JH7100_CLK_AHB_BUS),"e24_ahb" , 0 , JH7100_CLK_AHB_BUS),"e24rtc_toggle" , 0 , JH7100_CLK_OSC_SYS),"qspi_ahb" , 0 , JH7100_CLK_AHB_BUS),"qspi_apb" , 0 , JH7100_CLK_APB1_BUS),"qspi_refclk" , 0 , 31 , JH7100_CLK_PERH0_SRC),"sec_ahb" , 0 , JH7100_CLK_AHB_BUS),"aes_clk" , 0 , JH7100_CLK_SEC_AHB),"sha_clk" , 0 , JH7100_CLK_SEC_AHB),"pka_clk" , 0 , JH7100_CLK_SEC_AHB),"trng_apb" , 0 , JH7100_CLK_APB1_BUS),"otp_apb" , 0 , JH7100_CLK_APB1_BUS),"uart0_apb" , 0 , JH7100_CLK_APB1_BUS),"uart0_core" , 0 , 63 , JH7100_CLK_PERH1_SRC),"uart1_apb" , 0 , JH7100_CLK_APB1_BUS),"uart1_core" , 0 , 63 , JH7100_CLK_PERH1_SRC),"spi0_apb" , 0 , JH7100_CLK_APB1_BUS),"spi0_core" , 0 , 63 , JH7100_CLK_PERH1_SRC),"spi1_apb" , 0 , JH7100_CLK_APB1_BUS),"spi1_core" , 0 , 63 , JH7100_CLK_PERH1_SRC),"i2c0_apb" , 0 , JH7100_CLK_APB1_BUS),"i2c0_core" , 0 , 63 , JH7100_CLK_PERH1_SRC),"i2c1_apb" , 0 , JH7100_CLK_APB1_BUS),"i2c1_core" , 0 , 63 , JH7100_CLK_PERH1_SRC),"gpio_apb" , 0 , JH7100_CLK_APB1_BUS),"uart2_apb" , 0 , JH7100_CLK_APB2_BUS),"uart2_core" , 0 , 63 , JH7100_CLK_PERH0_SRC),"uart3_apb" , 0 , JH7100_CLK_APB2_BUS),"uart3_core" , 0 , 63 , JH7100_CLK_PERH0_SRC),"spi2_apb" , 0 , JH7100_CLK_APB2_BUS),"spi2_core" , 0 , 63 , JH7100_CLK_PERH0_SRC),"spi3_apb" , 0 , JH7100_CLK_APB2_BUS),"spi3_core" , 0 , 63 , JH7100_CLK_PERH0_SRC),"i2c2_apb" , 0 , JH7100_CLK_APB2_BUS),"i2c2_core" , 0 , 63 , JH7100_CLK_PERH0_SRC),"i2c3_apb" , 0 , JH7100_CLK_APB2_BUS),"i2c3_core" , 0 , 63 , JH7100_CLK_PERH0_SRC),"wdtimer_apb" , 0 , JH7100_CLK_APB2_BUS),"wdt_coreclk" , 0 , 63 , JH7100_CLK_PERH0_SRC),"timer0_coreclk" , 0 , 63 , JH7100_CLK_PERH0_SRC),"timer1_coreclk" , 0 , 63 , JH7100_CLK_PERH0_SRC),"timer2_coreclk" , 0 , 63 , JH7100_CLK_PERH0_SRC),"timer3_coreclk" , 0 , 63 , JH7100_CLK_PERH0_SRC),"timer4_coreclk" , 0 , 63 , JH7100_CLK_PERH0_SRC),"timer5_coreclk" , 0 , 63 , JH7100_CLK_PERH0_SRC),"timer6_coreclk" , 0 , 63 , JH7100_CLK_PERH0_SRC),"vp6intc_apb" , 0 , JH7100_CLK_APB2_BUS),"pwm_apb" , 0 , JH7100_CLK_APB2_BUS),"msi_apb" , 0 , JH7100_CLK_APB2_BUS),"temp_apb" , 0 , JH7100_CLK_APB2_BUS),"temp_sense" , 0 , 31 , JH7100_CLK_OSC_SYS),"syserr_apb" , 0 , JH7100_CLK_APB2_BUS),static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)struct jh71x0_clk_priv *priv = data;unsigned int idx = clkspec->args[0 ];if (idx < JH7100_CLK_PLL0_OUT)return &priv->reg[idx].hw;if (idx < JH7100_CLK_END)return priv->pll[idx - JH7100_CLK_PLL0_OUT];return ERR_PTR(-EINVAL);static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)struct jh71x0_clk_priv *priv;unsigned int idx;int ret;if (!priv)return -ENOMEM;0 );if (IS_ERR(priv->base))return PTR_ERR(priv->base);0 ] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out" ,"osc_sys" , 0 , 40 , 1 );if (IS_ERR(priv->pll[0 ]))return PTR_ERR(priv->pll[0 ]);1 ] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out" ,"osc_sys" , 0 , 64 , 1 );if (IS_ERR(priv->pll[1 ]))return PTR_ERR(priv->pll[1 ]);2 ] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out" ,"pll2_refclk" , 0 , 55 , 1 );if (IS_ERR(priv->pll[2 ]))return PTR_ERR(priv->pll[2 ]);for (idx = 0 ; idx < JH7100_CLK_PLL0_OUT; idx++) {struct clk_parent_data parents[4 ] = {};struct clk_init_data init = {1 ,struct jh71x0_clk *clk = &priv->reg[idx];unsigned int i;for (i = 0 ; i < init.num_parents; i++) {unsigned int pidx = jh7100_clk_data[idx].parents[i];if (pidx < JH7100_CLK_PLL0_OUT)else if (pidx < JH7100_CLK_END)else if (pidx == JH7100_CLK_OSC_SYS)"osc_sys" ;else if (pidx == JH7100_CLK_OSC_AUD)"osc_aud" ;else if (pidx == JH7100_CLK_GMAC_RMII_REF)"gmac_rmii_ref" ;else if (pidx == JH7100_CLK_GMAC_GR_MII_RX)"gmac_gr_mii_rxclk" ;if (ret)return ret;return devm_of_clk_add_hw_provider(priv->dev, jh7100_clk_get, priv);static const struct of_device_id clk_starfive_jh7100_match[] = {"starfive,jh7100-clkgen" },/* sentinel */ } static struct platform_driver clk_starfive_jh7100_driver = {"clk-starfive-jh7100" ,true ,be);
Messung V0.5 in Prozent C=95 H=96 G=95
¤ Dauer der Verarbeitung: 0.11 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
