// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Copyright (c) 2013 Linaro Ltd. * Author: Thomas Abraham <thomas.ab@samsung.com> * * Common Clock Framework support for Exynos5250 SoC. #include <dt-bindings/clock/exynos5250.h>#include <linux/clk-provider.h>#include <linux/io.h>#include <linux/mod_devicetable.h>#include <linux/of.h>#include <linux/of_address.h>#include "clk.h" #include "clk-cpu.h" #include "clk-exynos5-subcmu.h" #define APLL_LOCK 0 x0#define APLL_CON0 0 x100#define SRC_CPU 0 x200#define DIV_CPU0 0 x500#define PWR_CTRL1 0 x1020#define PWR_CTRL2 0 x1024#define MPLL_LOCK 0 x4000#define MPLL_CON0 0 x4100#define SRC_CORE1 0 x4204#define GATE_IP_ACP 0 x8800#define GATE_IP_ISP0 0 xc800#define GATE_IP_ISP1 0 xc804#define CPLL_LOCK 0 x10020#define EPLL_LOCK 0 x10030#define VPLL_LOCK 0 x10040#define GPLL_LOCK 0 x10050#define CPLL_CON0 0 x10120#define EPLL_CON0 0 x10130#define VPLL_CON0 0 x10140#define GPLL_CON0 0 x10150#define SRC_TOP0 0 x10210#define SRC_TOP1 0 x10214#define SRC_TOP2 0 x10218#define SRC_TOP3 0 x1021c#define SRC_GSCL 0 x10220#define SRC_DISP1_0 0 x1022c#define SRC_MAU 0 x10240#define SRC_FSYS 0 x10244#define SRC_GEN 0 x10248#define SRC_PERIC0 0 x10250#define SRC_PERIC1 0 x10254#define SRC_MASK_GSCL 0 x10320#define SRC_MASK_DISP1_0 0 x1032c#define SRC_MASK_MAU 0 x10334#define SRC_MASK_FSYS 0 x10340#define SRC_MASK_GEN 0 x10344#define SRC_MASK_PERIC0 0 x10350#define SRC_MASK_PERIC1 0 x10354#define DIV_TOP0 0 x10510#define DIV_TOP1 0 x10514#define DIV_GSCL 0 x10520#define DIV_DISP1_0 0 x1052c#define DIV_GEN 0 x1053c#define DIV_MAU 0 x10544#define DIV_FSYS0 0 x10548#define DIV_FSYS1 0 x1054c#define DIV_FSYS2 0 x10550#define DIV_PERIC0 0 x10558#define DIV_PERIC1 0 x1055c#define DIV_PERIC2 0 x10560#define DIV_PERIC3 0 x10564#define DIV_PERIC4 0 x10568#define DIV_PERIC5 0 x1056c#define GATE_IP_GSCL 0 x10920#define GATE_IP_DISP1 0 x10928#define GATE_IP_MFC 0 x1092c#define GATE_IP_G3D 0 x10930#define GATE_IP_GEN 0 x10934#define GATE_IP_FSYS 0 x10944#define GATE_IP_PERIC 0 x10950#define GATE_IP_PERIS 0 x10960#define BPLL_LOCK 0 x20010#define BPLL_CON0 0 x20110#define SRC_CDREX 0 x20200#define PLL_DIV2_SEL 0 x20a24/*Below definitions are used for PWR_CTRL settings*/ #define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28 )#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16 )#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9 )#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8 )#define PWR_CTRL1_USE_CORE1_WFE (1 << 5 )#define PWR_CTRL1_USE_CORE0_WFE (1 << 4 )#define PWR_CTRL1_USE_CORE1_WFI (1 << 1 )#define PWR_CTRL1_USE_CORE0_WFI (1 << 0 )#define PWR_CTRL2_DIV2_UP_EN (1 << 25 )#define PWR_CTRL2_DIV1_UP_EN (1 << 24 )#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16 )#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8 )#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4 )#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0 )/* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR (CLK_MOUT_VPLLSRC + 1 )/* list of PLLs to be registered */ enum exynos5250_plls {/* number of PLLs */ static void __iomem *reg_base;/* * list of controller registers to be saved and restored during a * suspend/resume cycle. static const unsigned long exynos5250_clk_regs[] __initconst = {/* list of all parent clock list */ "fin_pll" , "fout_apll" , };"mout_apll" , "mout_mpll" , };"fout_mplldiv2" , "fout_mpll" };"fin_pll" , "mout_mpll_fout" };"fout_bplldiv2" , "fout_bpll" };"fin_pll" , "mout_bpll_fout" };"fin_pll" , "sclk_hdmi27m" };"mout_vpllsrc" , "fout_vpll" };"fin_pll" , "fout_cpll" };"fin_pll" , "fout_epll" };"fin_pll" , "fout_gpll" };"fin_pll" , "mout_mpll" };"fin_pll" , "mout_bpll" };"mout_cpll" , "mout_mpll_user" };"mout_mpll_user" , "mout_bpll_user" };"mout_aclk300_disp1_mid" ,"mout_aclk300_disp1_mid1" };"mout_aclk400_g3d_mid" , "mout_gpll" };"fin_pll" , "div_aclk200" };"fin_pll" , "div_aclk266" };"fin_pll" , "div_aclk300_disp" };"mout_vpll" , "mout_cpll" };"fin_pll" , "div_aclk333" };"fin_pll" , "div_aclk400_isp" };"div_hdmi_pixel" , "sclk_hdmiphy" };"mout_mpll_user" , "mout_cpll" };"fin_pll" , "fin_pll" , "sclk_hdmi27m" ,"sclk_dptxphy" , "sclk_uhostphy" , "sclk_hdmiphy" ,"mout_mpll_user" , "mout_epll" , "mout_vpll" ,"mout_cpll" , "none" , "none" ,"none" , "none" , "none" ,"none" };"cdclk0" , "fin_pll" , "sclk_hdmi27m" , "sclk_dptxphy" ,"sclk_uhostphy" , "fin_pll" ,"mout_mpll_user" , "mout_epll" , "mout_vpll" ,"mout_cpll" , "none" , "none" ,"none" , "none" , "none" ,"none" };"cdclk1" , "fin_pll" , "sclk_hdmi27m" , "sclk_dptxphy" ,"sclk_uhostphy" , "fin_pll" ,"mout_mpll_user" , "mout_epll" , "mout_vpll" ,"mout_cpll" , "none" , "none" ,"none" , "none" , "none" ,"none" };"cdclk2" , "fin_pll" , "sclk_hdmi27m" , "sclk_dptxphy" ,"sclk_uhostphy" , "fin_pll" ,"mout_mpll_user" , "mout_epll" , "mout_vpll" ,"mout_cpll" , "none" , "none" ,"none" , "none" , "none" ,"none" };"sclk_audio0" , "sclk_audio1" , "sclk_audio2" ,"spdif_extclk" };/* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {"fin_pll" , NULL, 0 , 0 ),/* fixed rate clocks generated inside the soc */ static const struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initconst = {"sclk_hdmiphy" , NULL, 0 , 24000000 ),0 , "sclk_hdmi27m" , NULL, 0 , 27000000 ),0 , "sclk_dptxphy" , NULL, 0 , 24000000 ),0 , "sclk_uhostphy" , NULL, 0 , 48000000 ),static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initconst = {0 , "fout_mplldiv2" , "fout_mpll" , 1 , 2 , 0 ),0 , "fout_bplldiv2" , "fout_bpll" , 1 , 2 , 0 ),static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = {"mout_vpllsrc" , mout_vpllsrc_p, SRC_TOP2, 0 , 1 ),static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {/* * NOTE: Following table is sorted by (clock domain, register address, * bitfield shift) triplet in ascending order. When adding new entries, * please make sure that the order is kept, to avoid merge conflicts * and make further work with defined data easier. /* * CMU_CPU "mout_apll" , mout_apll_p, SRC_CPU, 0 , 1 ,0 ),0 , "mout_cpu" , mout_cpu_p, SRC_CPU, 16 , 1 ),/* * CMU_CORE "mout_mpll" , mout_mpll_p, SRC_CORE1, 8 , 1 ),/* * CMU_TOP 0 , "mout_aclk166" , mout_aclk166_p, SRC_TOP0, 8 , 1 ),0 , "mout_aclk200" , mout_aclk200_p, SRC_TOP0, 12 , 1 ),0 , "mout_aclk300_disp1_mid" , mout_aclk200_p, SRC_TOP0, 14 , 1 ),0 , "mout_aclk300" , mout_aclk300_p, SRC_TOP0, 15 , 1 ),0 , "mout_aclk333" , mout_aclk166_p, SRC_TOP0, 16 , 1 ),0 , "mout_aclk400_g3d_mid" , mout_aclk200_p, SRC_TOP0, 20 , 1 ),0 , "mout_aclk300_disp1_mid1" , mout_aclk300_disp1_mid1_p, SRC_TOP1,8 , 1 ),0 , "mout_aclk400_isp" , mout_aclk200_p, SRC_TOP1, 24 , 1 ),0 , "mout_aclk400_g3d" , mout_aclk400_p, SRC_TOP1, 28 , 1 ),0 , "mout_cpll" , mout_cpll_p, SRC_TOP2, 8 , 1 ),0 , "mout_epll" , mout_epll_p, SRC_TOP2, 12 , 1 ),0 , "mout_vpll" , mout_vpll_p, SRC_TOP2, 16 , 1 ),0 , "mout_mpll_user" , mout_mpll_user_p, SRC_TOP2, 20 , 1 ),0 , "mout_bpll_user" , mout_bpll_user_p, SRC_TOP2, 24 , 1 ),"mout_gpll" , mout_gpll_p, SRC_TOP2, 28 , 1 ),"mout_aclk200_disp1_sub" ,4 , 1 ),"mout_aclk300_disp1_sub" ,6 , 1 ),0 , "mout_aclk266_gscl_sub" , mout_aclk266_sub_p, SRC_TOP3, 8 , 1 ),0 , "mout_aclk_266_isp_sub" , mout_aclk266_sub_p, SRC_TOP3, 16 , 1 ),0 , "mout_aclk_400_isp_sub" , mout_aclk400_isp_sub_p,20 , 1 ),0 , "mout_aclk333_sub" , mout_aclk333_sub_p, SRC_TOP3, 24 , 1 ),0 , "mout_cam_bayer" , mout_group1_p, SRC_GSCL, 12 , 4 ),0 , "mout_cam0" , mout_group1_p, SRC_GSCL, 16 , 4 ),0 , "mout_cam1" , mout_group1_p, SRC_GSCL, 20 , 4 ),0 , "mout_gscl_wa" , mout_group1_p, SRC_GSCL, 24 , 4 ),0 , "mout_gscl_wb" , mout_group1_p, SRC_GSCL, 28 , 4 ),0 , "mout_fimd1" , mout_group1_p, SRC_DISP1_0, 0 , 4 ),0 , "mout_mipi1" , mout_group1_p, SRC_DISP1_0, 12 , 4 ),0 , "mout_dp" , mout_group1_p, SRC_DISP1_0, 16 , 4 ),"mout_hdmi" , mout_hdmi_p, SRC_DISP1_0, 20 , 1 ),0 , "mout_audio0" , mout_audio0_p, SRC_MAU, 0 , 4 ),0 , "mout_mmc0" , mout_group1_p, SRC_FSYS, 0 , 4 ),0 , "mout_mmc1" , mout_group1_p, SRC_FSYS, 4 , 4 ),0 , "mout_mmc2" , mout_group1_p, SRC_FSYS, 8 , 4 ),0 , "mout_mmc3" , mout_group1_p, SRC_FSYS, 12 , 4 ),0 , "mout_sata" , mout_aclk200_p, SRC_FSYS, 24 , 1 ),0 , "mout_usb3" , mout_usb3_p, SRC_FSYS, 28 , 1 ),0 , "mout_jpeg" , mout_group1_p, SRC_GEN, 0 , 4 ),0 , "mout_uart0" , mout_group1_p, SRC_PERIC0, 0 , 4 ),0 , "mout_uart1" , mout_group1_p, SRC_PERIC0, 4 , 4 ),0 , "mout_uart2" , mout_group1_p, SRC_PERIC0, 8 , 4 ),0 , "mout_uart3" , mout_group1_p, SRC_PERIC0, 12 , 4 ),0 , "mout_pwm" , mout_group1_p, SRC_PERIC0, 24 , 4 ),0 , "mout_audio1" , mout_audio1_p, SRC_PERIC1, 0 , 4 ),0 , "mout_audio2" , mout_audio2_p, SRC_PERIC1, 4 , 4 ),0 , "mout_spdif" , mout_spdif_p, SRC_PERIC1, 8 , 2 ),0 , "mout_spi0" , mout_group1_p, SRC_PERIC1, 16 , 4 ),0 , "mout_spi1" , mout_group1_p, SRC_PERIC1, 20 , 4 ),0 , "mout_spi2" , mout_group1_p, SRC_PERIC1, 24 , 4 ),/* * CMU_CDREX 0 , "mout_bpll" , mout_bpll_p, SRC_CDREX, 0 , 1 ),0 , "mout_mpll_fout" , mout_mpll_fout_p, PLL_DIV2_SEL, 4 , 1 ),0 , "mout_bpll_fout" , mout_bpll_fout_p, PLL_DIV2_SEL, 0 , 1 ),static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {/* * NOTE: Following table is sorted by (clock domain, register address, * bitfield shift) triplet in ascending order. When adding new entries, * please make sure that the order is kept, to avoid merge conflicts * and make further work with defined data easier. /* * CMU_CPU 0 , "div_arm" , "mout_cpu" , DIV_CPU0, 0 , 3 ),0 , "div_apll" , "mout_apll" , DIV_CPU0, 24 , 3 ),"div_arm2" , "div_arm" , DIV_CPU0, 28 , 3 ),/* * CMU_TOP 0 , "div_aclk66" , "div_aclk66_pre" , DIV_TOP0, 0 , 3 ),0 , "div_aclk166" , "mout_aclk166" , DIV_TOP0, 8 , 3 ),0 , "div_aclk200" , "mout_aclk200" , DIV_TOP0, 12 , 3 ),0 , "div_aclk266" , "mout_mpll_user" , DIV_TOP0, 16 , 3 ),0 , "div_aclk333" , "mout_aclk333" , DIV_TOP0, 20 , 3 ),0 , "div_aclk400_g3d" , "mout_aclk400_g3d" , DIV_TOP0,24 , 3 ),0 , "div_aclk300_disp" , "mout_aclk300" , DIV_TOP0, 28 , 3 ),0 , "div_aclk400_isp" , "mout_aclk400_isp" , DIV_TOP1, 20 , 3 ),0 , "div_aclk66_pre" , "mout_mpll_user" , DIV_TOP1, 24 , 3 ),0 , "div_cam_bayer" , "mout_cam_bayer" , DIV_GSCL, 12 , 4 ),0 , "div_cam0" , "mout_cam0" , DIV_GSCL, 16 , 4 ),0 , "div_cam1" , "mout_cam1" , DIV_GSCL, 20 , 4 ),0 , "div_gscl_wa" , "mout_gscl_wa" , DIV_GSCL, 24 , 4 ),0 , "div_gscl_wb" , "mout_gscl_wb" , DIV_GSCL, 28 , 4 ),0 , "div_fimd1" , "mout_fimd1" , DIV_DISP1_0, 0 , 4 ),0 , "div_mipi1" , "mout_mipi1" , DIV_DISP1_0, 16 , 4 ),0 , "div_mipi1_pre" , "div_mipi1" ,20 , 4 , CLK_SET_RATE_PARENT, 0 ),0 , "div_dp" , "mout_dp" , DIV_DISP1_0, 24 , 4 ),"div_hdmi_pixel" , "mout_vpll" , DIV_DISP1_0, 28 , 4 ),0 , "div_jpeg" , "mout_jpeg" , DIV_GEN, 4 , 4 ),0 , "div_audio0" , "mout_audio0" , DIV_MAU, 0 , 4 ),"div_pcm0" , "sclk_audio0" , DIV_MAU, 4 , 8 ),0 , "div_sata" , "mout_sata" , DIV_FSYS0, 20 , 4 ),0 , "div_usb3" , "mout_usb3" , DIV_FSYS0, 24 , 4 ),0 , "div_mmc0" , "mout_mmc0" , DIV_FSYS1, 0 , 4 ),0 , "div_mmc_pre0" , "div_mmc0" ,8 , 8 , CLK_SET_RATE_PARENT, 0 ),0 , "div_mmc1" , "mout_mmc1" , DIV_FSYS1, 16 , 4 ),0 , "div_mmc_pre1" , "div_mmc1" ,24 , 8 , CLK_SET_RATE_PARENT, 0 ),0 , "div_mmc2" , "mout_mmc2" , DIV_FSYS2, 0 , 4 ),0 , "div_mmc_pre2" , "div_mmc2" ,8 , 8 , CLK_SET_RATE_PARENT, 0 ),0 , "div_mmc3" , "mout_mmc3" , DIV_FSYS2, 16 , 4 ),0 , "div_mmc_pre3" , "div_mmc3" ,24 , 8 , CLK_SET_RATE_PARENT, 0 ),0 , "div_uart0" , "mout_uart0" , DIV_PERIC0, 0 , 4 ),0 , "div_uart1" , "mout_uart1" , DIV_PERIC0, 4 , 4 ),0 , "div_uart2" , "mout_uart2" , DIV_PERIC0, 8 , 4 ),0 , "div_uart3" , "mout_uart3" , DIV_PERIC0, 12 , 4 ),0 , "div_spi0" , "mout_spi0" , DIV_PERIC1, 0 , 4 ),0 , "div_spi_pre0" , "div_spi0" ,8 , 8 , CLK_SET_RATE_PARENT, 0 ),0 , "div_spi1" , "mout_spi1" , DIV_PERIC1, 16 , 4 ),0 , "div_spi_pre1" , "div_spi1" ,24 , 8 , CLK_SET_RATE_PARENT, 0 ),0 , "div_spi2" , "mout_spi2" , DIV_PERIC2, 0 , 4 ),0 , "div_spi_pre2" , "div_spi2" ,8 , 8 , CLK_SET_RATE_PARENT, 0 ),0 , "div_pwm" , "mout_pwm" , DIV_PERIC3, 0 , 4 ),0 , "div_audio1" , "mout_audio1" , DIV_PERIC4, 0 , 4 ),0 , "div_pcm1" , "sclk_audio1" , DIV_PERIC4, 4 , 8 ),0 , "div_audio2" , "mout_audio2" , DIV_PERIC4, 16 , 4 ),0 , "div_pcm2" , "sclk_audio2" , DIV_PERIC4, 20 , 8 ),"div_i2s1" , "sclk_audio1" , DIV_PERIC5, 0 , 6 ),"div_i2s2" , "sclk_audio2" , DIV_PERIC5, 8 , 6 ),static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = {/* * NOTE: Following table is sorted by (clock domain, register address, * bitfield shift) triplet in ascending order. When adding new entries, * please make sure that the order is kept, to avoid merge conflicts * and make further work with defined data easier. /* * CMU_ACP "mdma0" , "div_aclk266" , GATE_IP_ACP, 1 , 0 , 0 ),"sss" , "div_aclk266" , GATE_IP_ACP, 2 , 0 , 0 ),"g2d" , "div_aclk200" , GATE_IP_ACP, 3 , 0 , 0 ),"smmu_mdma0" , "div_aclk266" , GATE_IP_ACP, 5 , 0 , 0 ),/* * CMU_TOP "sclk_cam_bayer" , "div_cam_bayer" ,12 , CLK_SET_RATE_PARENT, 0 ),"sclk_cam0" , "div_cam0" ,16 , CLK_SET_RATE_PARENT, 0 ),"sclk_cam1" , "div_cam1" ,20 , CLK_SET_RATE_PARENT, 0 ),"sclk_gscl_wa" , "div_gscl_wa" ,24 , CLK_SET_RATE_PARENT, 0 ),"sclk_gscl_wb" , "div_gscl_wb" ,28 , CLK_SET_RATE_PARENT, 0 ),"sclk_fimd1" , "div_fimd1" ,0 , CLK_SET_RATE_PARENT, 0 ),"sclk_mipi1" , "div_mipi1" ,12 , CLK_SET_RATE_PARENT, 0 ),"sclk_dp" , "div_dp" ,16 , CLK_SET_RATE_PARENT, 0 ),"sclk_hdmi" , "mout_hdmi" ,20 , 0 , 0 ),"sclk_audio0" , "div_audio0" ,0 , CLK_SET_RATE_PARENT, 0 ),"sclk_mmc0" , "div_mmc_pre0" ,0 , CLK_SET_RATE_PARENT, 0 ),"sclk_mmc1" , "div_mmc_pre1" ,4 , CLK_SET_RATE_PARENT, 0 ),"sclk_mmc2" , "div_mmc_pre2" ,8 , CLK_SET_RATE_PARENT, 0 ),"sclk_mmc3" , "div_mmc_pre3" ,12 , CLK_SET_RATE_PARENT, 0 ),"sclk_sata" , "div_sata" ,24 , CLK_SET_RATE_PARENT, 0 ),"sclk_usb3" , "div_usb3" ,28 , CLK_SET_RATE_PARENT, 0 ),"sclk_jpeg" , "div_jpeg" ,0 , CLK_SET_RATE_PARENT, 0 ),"sclk_uart0" , "div_uart0" ,0 , CLK_SET_RATE_PARENT, 0 ),"sclk_uart1" , "div_uart1" ,4 , CLK_SET_RATE_PARENT, 0 ),"sclk_uart2" , "div_uart2" ,8 , CLK_SET_RATE_PARENT, 0 ),"sclk_uart3" , "div_uart3" ,12 , CLK_SET_RATE_PARENT, 0 ),"sclk_pwm" , "div_pwm" ,24 , CLK_SET_RATE_PARENT, 0 ),"sclk_audio1" , "div_audio1" ,0 , CLK_SET_RATE_PARENT, 0 ),"sclk_audio2" , "div_audio2" ,4 , CLK_SET_RATE_PARENT, 0 ),"sclk_spdif" , "mout_spdif" ,4 , 0 , 0 ),"sclk_spi0" , "div_spi_pre0" ,16 , CLK_SET_RATE_PARENT, 0 ),"sclk_spi1" , "div_spi_pre1" ,20 , CLK_SET_RATE_PARENT, 0 ),"sclk_spi2" , "div_spi_pre2" ,24 , CLK_SET_RATE_PARENT, 0 ),"gscl0" , "mout_aclk266_gscl_sub" , GATE_IP_GSCL, 0 , 0 ,0 ),"gscl1" , "mout_aclk266_gscl_sub" , GATE_IP_GSCL, 1 , 0 ,0 ),"gscl2" , "mout_aclk266_gscl_sub" , GATE_IP_GSCL, 2 , 0 ,0 ),"gscl3" , "mout_aclk266_gscl_sub" , GATE_IP_GSCL, 3 , 0 ,0 ),"camif_top" , "mout_aclk266_gscl_sub" ,4 , 0 , 0 ),"gscl_wa" , "div_gscl_wa" , GATE_IP_GSCL, 5 , 0 , 0 ),"gscl_wb" , "div_gscl_wb" , GATE_IP_GSCL, 6 , 0 , 0 ),"smmu_gscl0" , "mout_aclk266_gscl_sub" ,7 , 0 , 0 ),"smmu_gscl1" , "mout_aclk266_gscl_sub" ,8 , 0 , 0 ),"smmu_gscl2" , "mout_aclk266_gscl_sub" ,9 , 0 , 0 ),"smmu_gscl3" , "mout_aclk266_gscl_sub" ,10 , 0 , 0 ),"smmu_fimc_lite0" , "mout_aclk266_gscl_sub" ,11 , 0 , 0 ),"smmu_fimc_lite1" , "mout_aclk266_gscl_sub" ,12 , 0 , 0 ),"mfc" , "mout_aclk333_sub" , GATE_IP_MFC, 0 , 0 , 0 ),"smmu_mfcr" , "mout_aclk333_sub" , GATE_IP_MFC, 1 , 0 ,0 ),"smmu_mfcl" , "mout_aclk333_sub" , GATE_IP_MFC, 2 , 0 ,0 ),"g3d" , "div_aclk400_g3d" , GATE_IP_G3D, 0 ,0 ),"rotator" , "div_aclk266" , GATE_IP_GEN, 1 , 0 , 0 ),"jpeg" , "div_aclk166" , GATE_IP_GEN, 2 , 0 , 0 ),"mdma1" , "div_aclk266" , GATE_IP_GEN, 4 , 0 , 0 ),"smmu_rotator" , "div_aclk266" , GATE_IP_GEN, 6 , 0 ,0 ),"smmu_jpeg" , "div_aclk166" , GATE_IP_GEN, 7 , 0 , 0 ),"smmu_mdma1" , "div_aclk266" , GATE_IP_GEN, 9 , 0 , 0 ),"pdma0" , "div_aclk200" , GATE_IP_FSYS, 1 , 0 , 0 ),"pdma1" , "div_aclk200" , GATE_IP_FSYS, 2 , 0 , 0 ),"sata" , "div_aclk200" , GATE_IP_FSYS, 6 , 0 , 0 ),"usbotg" , "div_aclk200" , GATE_IP_FSYS, 7 , 0 , 0 ),"mipi_hsi" , "div_aclk200" , GATE_IP_FSYS, 8 , 0 , 0 ),"sdmmc0" , "div_aclk200" , GATE_IP_FSYS, 12 , 0 , 0 ),"sdmmc1" , "div_aclk200" , GATE_IP_FSYS, 13 , 0 , 0 ),"sdmmc2" , "div_aclk200" , GATE_IP_FSYS, 14 , 0 , 0 ),"sdmmc3" , "div_aclk200" , GATE_IP_FSYS, 15 , 0 , 0 ),"sromc" , "div_aclk200" , GATE_IP_FSYS, 17 , 0 , 0 ),"usb2" , "div_aclk200" , GATE_IP_FSYS, 18 , 0 , 0 ),"usb3" , "div_aclk200" , GATE_IP_FSYS, 19 , 0 , 0 ),"sata_phyctrl" , "div_aclk200" ,24 , 0 , 0 ),"sata_phyi2c" , "div_aclk200" , GATE_IP_FSYS, 25 , 0 ,0 ),"uart0" , "div_aclk66" , GATE_IP_PERIC, 0 , 0 , 0 ),"uart1" , "div_aclk66" , GATE_IP_PERIC, 1 , 0 , 0 ),"uart2" , "div_aclk66" , GATE_IP_PERIC, 2 , 0 , 0 ),"uart3" , "div_aclk66" , GATE_IP_PERIC, 3 , 0 , 0 ),"uart4" , "div_aclk66" , GATE_IP_PERIC, 4 , 0 , 0 ),"i2c0" , "div_aclk66" , GATE_IP_PERIC, 6 , 0 , 0 ),"i2c1" , "div_aclk66" , GATE_IP_PERIC, 7 , 0 , 0 ),"i2c2" , "div_aclk66" , GATE_IP_PERIC, 8 , 0 , 0 ),"i2c3" , "div_aclk66" , GATE_IP_PERIC, 9 , 0 , 0 ),"i2c4" , "div_aclk66" , GATE_IP_PERIC, 10 , 0 , 0 ),"i2c5" , "div_aclk66" , GATE_IP_PERIC, 11 , 0 , 0 ),"i2c6" , "div_aclk66" , GATE_IP_PERIC, 12 , 0 , 0 ),"i2c7" , "div_aclk66" , GATE_IP_PERIC, 13 , 0 , 0 ),"i2c_hdmi" , "div_aclk66" , GATE_IP_PERIC, 14 , 0 , 0 ),"adc" , "div_aclk66" , GATE_IP_PERIC, 15 , 0 , 0 ),"spi0" , "div_aclk66" , GATE_IP_PERIC, 16 , 0 , 0 ),"spi1" , "div_aclk66" , GATE_IP_PERIC, 17 , 0 , 0 ),"spi2" , "div_aclk66" , GATE_IP_PERIC, 18 , 0 , 0 ),"i2s1" , "div_aclk66" , GATE_IP_PERIC, 20 , 0 , 0 ),"i2s2" , "div_aclk66" , GATE_IP_PERIC, 21 , 0 , 0 ),"pcm1" , "div_aclk66" , GATE_IP_PERIC, 22 , 0 , 0 ),"pcm2" , "div_aclk66" , GATE_IP_PERIC, 23 , 0 , 0 ),"pwm" , "div_aclk66" , GATE_IP_PERIC, 24 , 0 , 0 ),"spdif" , "div_aclk66" , GATE_IP_PERIC, 26 , 0 , 0 ),"ac97" , "div_aclk66" , GATE_IP_PERIC, 27 , 0 , 0 ),"hsi2c0" , "div_aclk66" , GATE_IP_PERIC, 28 , 0 , 0 ),"hsi2c1" , "div_aclk66" , GATE_IP_PERIC, 29 , 0 , 0 ),"hsi2c2" , "div_aclk66" , GATE_IP_PERIC, 30 , 0 , 0 ),"hsi2c3" , "div_aclk66" , GATE_IP_PERIC, 31 , 0 , 0 ),"chipid" , "div_aclk66" , GATE_IP_PERIS, 0 , 0 , 0 ),"sysreg" , "div_aclk66" ,1 , CLK_IGNORE_UNUSED, 0 ),"pmu" , "div_aclk66" , GATE_IP_PERIS, 2 , CLK_IGNORE_UNUSED,0 ),"cmu_top" , "div_aclk66" ,3 , CLK_IGNORE_UNUSED, 0 ),"cmu_core" , "div_aclk66" ,4 , CLK_IGNORE_UNUSED, 0 ),"cmu_mem" , "div_aclk66" ,5 , CLK_IGNORE_UNUSED, 0 ),"tzpc0" , "div_aclk66" , GATE_IP_PERIS, 6 , 0 , 0 ),"tzpc1" , "div_aclk66" , GATE_IP_PERIS, 7 , 0 , 0 ),"tzpc2" , "div_aclk66" , GATE_IP_PERIS, 8 , 0 , 0 ),"tzpc3" , "div_aclk66" , GATE_IP_PERIS, 9 , 0 , 0 ),"tzpc4" , "div_aclk66" , GATE_IP_PERIS, 10 , 0 , 0 ),"tzpc5" , "div_aclk66" , GATE_IP_PERIS, 11 , 0 , 0 ),"tzpc6" , "div_aclk66" , GATE_IP_PERIS, 12 , 0 , 0 ),"tzpc7" , "div_aclk66" , GATE_IP_PERIS, 13 , 0 , 0 ),"tzpc8" , "div_aclk66" , GATE_IP_PERIS, 14 , 0 , 0 ),"tzpc9" , "div_aclk66" , GATE_IP_PERIS, 15 , 0 , 0 ),"hdmi_cec" , "div_aclk66" , GATE_IP_PERIS, 16 , 0 , 0 ),"mct" , "div_aclk66" , GATE_IP_PERIS, 18 , 0 , 0 ),"wdt" , "div_aclk66" , GATE_IP_PERIS, 19 , 0 , 0 ),"rtc" , "div_aclk66" , GATE_IP_PERIS, 20 , 0 , 0 ),"tmu" , "div_aclk66" , GATE_IP_PERIS, 21 , 0 , 0 ),"smmu_2d" , "div_aclk200" , GATE_IP_ACP, 7 , 0 , 0 ),"smmu_fimc_isp" , "mout_aclk_266_isp_sub" ,8 , 0 , 0 ),"smmu_fimc_drc" , "mout_aclk_266_isp_sub" ,9 , 0 , 0 ),"smmu_fimc_fd" , "mout_aclk_266_isp_sub" ,10 , 0 , 0 ),"smmu_fimc_scc" , "mout_aclk_266_isp_sub" ,11 , 0 , 0 ),"smmu_fimc_scp" , "mout_aclk_266_isp_sub" ,12 , 0 , 0 ),"smmu_fimc_mcu" , "mout_aclk_400_isp_sub" ,13 , 0 , 0 ),"smmu_fimc_odc" , "mout_aclk_266_isp_sub" ,4 , 0 , 0 ),"smmu_fimc_dis0" , "mout_aclk_266_isp_sub" ,5 , 0 , 0 ),"smmu_fimc_dis1" , "mout_aclk_266_isp_sub" ,6 , 0 , 0 ),"smmu_fimc_3dnr" , "mout_aclk_266_isp_sub" ,7 , 0 , 0 ),static const struct samsung_gate_clock exynos5250_disp_gate_clks[] __initconst = {"fimd1" , "mout_aclk200_disp1_sub" , GATE_IP_DISP1, 0 , 0 ,0 ),"mie1" , "mout_aclk200_disp1_sub" , GATE_IP_DISP1, 1 , 0 ,0 ),"dsim0" , "mout_aclk200_disp1_sub" , GATE_IP_DISP1, 3 , 0 ,0 ),"dp" , "mout_aclk200_disp1_sub" , GATE_IP_DISP1, 4 , 0 , 0 ),"mixer" , "mout_aclk200_disp1_sub" , GATE_IP_DISP1, 5 , 0 ,0 ),"hdmi" , "mout_aclk200_disp1_sub" , GATE_IP_DISP1, 6 , 0 ,0 ),"smmu_tv" , "mout_aclk200_disp1_sub" ,9 , 0 , 0 ),"smmu_fimd1" , "mout_aclk200_disp1_sub" ,8 , 0 , 0 ),static struct exynos5_subcmu_reg_dump exynos5250_disp_suspend_regs[] = {0 xffffffff, 0 xffffffff }, /* DISP1 gates */ 0 , BIT(4 ) }, /* MUX mout_aclk200_disp1_sub */ 0 , BIT(6 ) }, /* MUX mout_aclk300_disp1_sub */ static const struct exynos5_subcmu_info exynos5250_disp_subcmu = {"DISP1" ,static const struct exynos5_subcmu_info *exynos5250_subcmus[] = {static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {/* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ 24 * MHZ, 266000000 , 266 , 3 , 3 , 0 ),/* Not in UM, but need for eDP on snow */ 24 * MHZ, 70500000 , 94 , 2 , 4 , 0 ),static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = {/* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ 24 * MHZ, 192000000 , 64 , 2 , 2 , 0 ),24 * MHZ, 180633605 , 90 , 3 , 2 , 20762 ),24 * MHZ, 180000000 , 90 , 3 , 2 , 0 ),24 * MHZ, 73728000 , 98 , 2 , 4 , 19923 ),24 * MHZ, 67737602 , 90 , 2 , 4 , 20762 ),24 * MHZ, 49152000 , 98 , 3 , 4 , 19923 ),24 * MHZ, 45158401 , 90 , 3 , 4 , 20762 ),24 * MHZ, 32768001 , 131 , 3 , 5 , 4719 ),static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {/* sorted in descending order */ /* PLL_35XX_RATE(fin, rate, m, p, s) */ 24 * MHZ, 1700000000 , 425 , 6 , 0 ),24 * MHZ, 1600000000 , 200 , 3 , 0 ),24 * MHZ, 1500000000 , 250 , 4 , 0 ),24 * MHZ, 1400000000 , 175 , 3 , 0 ),24 * MHZ, 1300000000 , 325 , 6 , 0 ),24 * MHZ, 1200000000 , 200 , 4 , 0 ),24 * MHZ, 1100000000 , 275 , 6 , 0 ),24 * MHZ, 1000000000 , 125 , 3 , 0 ),24 * MHZ, 900000000 , 150 , 4 , 0 ),24 * MHZ, 800000000 , 100 , 3 , 0 ),24 * MHZ, 700000000 , 175 , 3 , 1 ),24 * MHZ, 600000000 , 200 , 4 , 1 ),24 * MHZ, 500000000 , 125 , 3 , 1 ),24 * MHZ, 400000000 , 100 , 3 , 1 ),24 * MHZ, 300000000 , 200 , 4 , 2 ),24 * MHZ, 200000000 , 100 , 3 , 2 ),static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {"fout_apll" , "fin_pll" , APLL_LOCK,"fout_mpll" , "fin_pll" , MPLL_LOCK,"fout_bpll" , "fin_pll" , BPLL_LOCK,"fout_gpll" , "fin_pll" , GPLL_LOCK,"fout_cpll" , "fin_pll" , CPLL_LOCK,"fout_epll" , "fin_pll" , EPLL_LOCK,"fout_vpll" , "mout_vpllsrc" ,#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \24 ) | ((pclk_dbg) << 20 ) | ((atb) << 16 ) | \12 ) | ((acp) << 8 ) | ((cpud) << 4 )))#define E5250_CPU_DIV1(hpm, copy) \4 ) | (copy))static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {1700000 , E5250_CPU_DIV0(5 , 3 , 7 , 7 , 7 , 3 ), E5250_CPU_DIV1(2 , 0 ), },1600000 , E5250_CPU_DIV0(4 , 1 , 7 , 7 , 7 , 3 ), E5250_CPU_DIV1(2 , 0 ), },1500000 , E5250_CPU_DIV0(4 , 1 , 7 , 7 , 7 , 2 ), E5250_CPU_DIV1(2 , 0 ), },1400000 , E5250_CPU_DIV0(4 , 1 , 6 , 7 , 7 , 2 ), E5250_CPU_DIV1(2 , 0 ), },1300000 , E5250_CPU_DIV0(3 , 1 , 6 , 7 , 7 , 2 ), E5250_CPU_DIV1(2 , 0 ), },1200000 , E5250_CPU_DIV0(3 , 1 , 5 , 7 , 7 , 2 ), E5250_CPU_DIV1(2 , 0 ), },1100000 , E5250_CPU_DIV0(3 , 1 , 5 , 7 , 7 , 3 ), E5250_CPU_DIV1(2 , 0 ), },1000000 , E5250_CPU_DIV0(2 , 1 , 4 , 7 , 7 , 1 ), E5250_CPU_DIV1(2 , 0 ), },900000 , E5250_CPU_DIV0(2 , 1 , 4 , 7 , 7 , 1 ), E5250_CPU_DIV1(2 , 0 ), },800000 , E5250_CPU_DIV0(2 , 1 , 4 , 7 , 7 , 1 ), E5250_CPU_DIV1(2 , 0 ), },700000 , E5250_CPU_DIV0(1 , 1 , 3 , 7 , 7 , 1 ), E5250_CPU_DIV1(2 , 0 ), },600000 , E5250_CPU_DIV0(1 , 1 , 3 , 7 , 7 , 1 ), E5250_CPU_DIV1(2 , 0 ), },500000 , E5250_CPU_DIV0(1 , 1 , 2 , 7 , 7 , 1 ), E5250_CPU_DIV1(2 , 0 ), },400000 , E5250_CPU_DIV0(1 , 1 , 2 , 7 , 7 , 1 ), E5250_CPU_DIV1(2 , 0 ), },300000 , E5250_CPU_DIV0(1 , 1 , 1 , 7 , 7 , 1 ), E5250_CPU_DIV1(2 , 0 ), },200000 , E5250_CPU_DIV0(1 , 1 , 1 , 7 , 7 , 1 ), E5250_CPU_DIV1(2 , 0 ), },0 },static const struct samsung_cpu_clock exynos5250_cpu_clks[] __initconst = {"armclk" , CLK_MOUT_APLL, CLK_MOUT_MPLL,0 x0, CPUCLK_LAYOUT_E4210,static const struct of_device_id ext_clk_match[] __initconst = {"samsung,clock-xxti" , .data = (void *)0 , },/* register exynox5250 clocks */ static void __init exynos5250_clk_init(struct device_node *np)struct samsung_clk_provider *ctx;unsigned int tmp;struct clk_hw **hws;if (np) {0 );if (!reg_base)"%s: failed to map registers\n" , __func__);else {"%s: unable to determine soc\n" , __func__);if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24 * MHZ)/* * Enable arm clock down (in idle) and set arm divider * ratios in WFI/WFE state. /* * Enable arm clock up (on exiting idle). Set arm divider * ratios when not in idle along with the standby duration * ratios. "Exynos5250: clock setup completed, armclk=%ld\n" ,"samsung,exynos5250-clock" , exynos5250_clk_init);
Messung V0.5 in Prozent C=93 H=93 G=92
