// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * * Common Clock Framework support for Exynos3250 SoC. #include <linux/clk-provider.h>#include <linux/io.h>#include <linux/mod_devicetable.h>#include <linux/platform_device.h>#include <dt-bindings/clock/exynos3250.h>#include "clk.h" #include "clk-cpu.h" #include "clk-pll.h" #define SRC_LEFTBUS 0 x4200#define DIV_LEFTBUS 0 x4500#define GATE_IP_LEFTBUS 0 x4800#define SRC_RIGHTBUS 0 x8200#define DIV_RIGHTBUS 0 x8500#define GATE_IP_RIGHTBUS 0 x8800#define GATE_IP_PERIR 0 x8960#define MPLL_LOCK 0 xc010#define MPLL_CON0 0 xc110#define VPLL_LOCK 0 xc020#define VPLL_CON0 0 xc120#define UPLL_LOCK 0 xc030#define UPLL_CON0 0 xc130#define SRC_TOP0 0 xc210#define SRC_TOP1 0 xc214#define SRC_CAM 0 xc220#define SRC_MFC 0 xc228#define SRC_G3D 0 xc22c#define SRC_LCD 0 xc234#define SRC_ISP 0 xc238#define SRC_FSYS 0 xc240#define SRC_PERIL0 0 xc250#define SRC_PERIL1 0 xc254#define SRC_MASK_TOP 0 xc310#define SRC_MASK_CAM 0 xc320#define SRC_MASK_LCD 0 xc334#define SRC_MASK_ISP 0 xc338#define SRC_MASK_FSYS 0 xc340#define SRC_MASK_PERIL0 0 xc350#define SRC_MASK_PERIL1 0 xc354#define DIV_TOP 0 xc510#define DIV_CAM 0 xc520#define DIV_MFC 0 xc528#define DIV_G3D 0 xc52c#define DIV_LCD 0 xc534#define DIV_ISP 0 xc538#define DIV_FSYS0 0 xc540#define DIV_FSYS1 0 xc544#define DIV_FSYS2 0 xc548#define DIV_PERIL0 0 xc550#define DIV_PERIL1 0 xc554#define DIV_PERIL3 0 xc55c#define DIV_PERIL4 0 xc560#define DIV_PERIL5 0 xc564#define DIV_CAM1 0 xc568#define CLKDIV2_RATIO 0 xc580#define GATE_SCLK_CAM 0 xc820#define GATE_SCLK_MFC 0 xc828#define GATE_SCLK_G3D 0 xc82c#define GATE_SCLK_LCD 0 xc834#define GATE_SCLK_ISP_TOP 0 xc838#define GATE_SCLK_FSYS 0 xc840#define GATE_SCLK_PERIL 0 xc850#define GATE_IP_CAM 0 xc920#define GATE_IP_MFC 0 xc928#define GATE_IP_G3D 0 xc92c#define GATE_IP_LCD 0 xc934#define GATE_IP_ISP 0 xc938#define GATE_IP_FSYS 0 xc940#define GATE_IP_PERIL 0 xc950#define GATE_BLOCK 0 xc970#define APLL_LOCK 0 x14000#define APLL_CON0 0 x14100#define SRC_CPU 0 x14200#define DIV_CPU0 0 x14500#define DIV_CPU1 0 x14504#define PWR_CTRL1 0 x15020#define PWR_CTRL2 0 x15024/* Below definitions are used for PWR_CTRL settings */ #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0 x7) << 28 )#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0 x7) << 16 )#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9 )#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8 )#define PWR_CTRL1_USE_CORE3_WFE (1 << 7 )#define PWR_CTRL1_USE_CORE2_WFE (1 << 6 )#define PWR_CTRL1_USE_CORE1_WFE (1 << 5 )#define PWR_CTRL1_USE_CORE0_WFE (1 << 4 )#define PWR_CTRL1_USE_CORE3_WFI (1 << 3 )#define PWR_CTRL1_USE_CORE2_WFI (1 << 2 )#define PWR_CTRL1_USE_CORE1_WFI (1 << 1 )#define PWR_CTRL1_USE_CORE0_WFI (1 << 0 )/* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_MAIN (CLK_SCLK_MMC2 + 1 )#define CLKS_NR_DMC (CLK_DIV_DMCD + 1 )#define CLKS_NR_ISP (CLK_SCLK_MPWM_ISP + 1 )static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {/* list of all parent clock list */ "fin_pll" , };"fin_pll" , "fout_apll" , };"fin_pll" , "fout_mpll" , };"fin_pll" , "fout_vpll" , };"fin_pll" , "fout_upll" , };"fin_pll" , "div_mpll_pre" , };"fin_pll" , "mout_epll" , };"mout_apll" , "mout_mpll_user_c" , };"mout_apll" , "mout_mpll_user_c" , };"div_aclk_200" , "div_aclk_160" , };"mout_ebi" , "mout_vpll" , };"mout_mpll_user_l" , };"mout_mpll_user_r" , };"fin_pll" , "div_aclk_400_mcuisp" , };"div_mpll_pre" , "mout_vpll" , };"mout_epll_user" , };"mout_aclk_266_0" , "mout_aclk_266_1" , };"fin_pll" , "div_aclk_266" , };"div_mpll_pre" , };"mout_epll_user" , "mout_vpll" };"xxti" , "xusbxti" ,"none" , "none" ,"none" , "none" , "div_mpll_pre" ,"mout_epll_user" , "mout_vpll" , };"audiocdclk" , "none" ,"none" , "none" ,"xxti" , "xusbxti" ,"div_mpll_pre" , "mout_epll_user" ,"mout_vpll" , };"xxti" , "xusbxti" ,"none" , "none" , "none" ,"none" , "div_mpll_pre" ,"mout_epll_user" , "mout_vpll" ,"none" , "none" , "none" ,"div_cam_blk_320" , };"xxti" , "xusbxti" ,"m_bitclkhsdiv4_2l" , "none" ,"none" , "none" , "div_mpll_pre" ,"mout_epll_user" , "mout_vpll" ,"none" , "none" , "none" ,"div_lcd_blk_145" , };"mout_mfc_0" , "mout_mfc_1" };"mout_g3d_0" , "mout_g3d_1" };static const struct samsung_fixed_factor_clock fixed_factor_clks[] __initconst = {0 , "sclk_mpll_1600" , "mout_mpll" , 1 , 1 , 0 ),0 , "sclk_mpll_mif" , "mout_mpll" , 1 , 2 , 0 ),0 , "sclk_bpll" , "fout_bpll" , 1 , 2 , 0 ),0 , "div_cam_blk_320" , "sclk_mpll_1600" , 1 , 5 , 0 ),0 , "div_lcd_blk_145" , "sclk_mpll_1600" , 1 , 11 , 0 ),/* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */ "fin_pll" , "xusbxti" , 1 , 1 , 0 ),static const struct samsung_mux_clock mux_clks[] __initconst = {/* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done * in the User's Manual. When adding new entries, please make sure * that the order is preserved, to avoid merge conflicts and make * further work with defined data easier. /* SRC_LEFTBUS */ "mout_mpll_user_l" , mout_mpll_user_p,4 , 1 ),"mout_gdl" , mout_gdl_p, SRC_LEFTBUS, 0 , 1 ),/* SRC_RIGHTBUS */ "mout_mpll_user_r" , mout_mpll_user_p,4 , 1 ),"mout_gdr" , mout_gdr_p, SRC_RIGHTBUS, 0 , 1 ),/* SRC_TOP0 */ "mout_ebi" , mout_ebi_p, SRC_TOP0, 28 , 1 ),"mout_aclk_200" , group_div_mpll_pre_p, SRC_TOP0, 24 , 1 ),"mout_aclk_160" , group_div_mpll_pre_p, SRC_TOP0, 20 , 1 ),"mout_aclk_100" , group_div_mpll_pre_p, SRC_TOP0, 16 , 1 ),"mout_aclk_266_1" , mout_aclk_266_1_p, SRC_TOP0, 14 , 1 ),"mout_aclk_266_0" , mout_aclk_266_0_p, SRC_TOP0, 13 , 1 ),"mout_aclk_266" , mout_aclk_266_p, SRC_TOP0, 12 , 1 ),"mout_vpll" , mout_vpll_p, SRC_TOP0, 8 , 1 ),"mout_epll_user" , mout_epll_user_p, SRC_TOP0, 4 , 1 ),"mout_ebi_1" , mout_ebi_1_p, SRC_TOP0, 0 , 1 ),/* SRC_TOP1 */ "mout_upll" , mout_upll_p, SRC_TOP1, 28 , 1 ),"mout_aclk_400_mcuisp_sub" , mout_aclk_400_mcuisp_sub_p,24 , 1 ),"mout_aclk_266_sub" , mout_aclk_266_sub_p, SRC_TOP1, 20 , 1 ),"mout_mpll" , mout_mpll_p, SRC_TOP1, 12 , 1 ),"mout_aclk_400_mcuisp" , group_div_mpll_pre_p, SRC_TOP1, 8 , 1 ),"mout_vpllsrc" , mout_vpllsrc_p, SRC_TOP1, 0 , 1 ),/* SRC_CAM */ "mout_cam1" , group_sclk_p, SRC_CAM, 20 , 4 ),"mout_cam_blk" , group_sclk_cam_blk_p, SRC_CAM, 0 , 4 ),/* SRC_MFC */ "mout_mfc" , mout_mfc_p, SRC_MFC, 8 , 1 ),"mout_mfc_1" , group_epll_vpll_p, SRC_MFC, 4 , 1 ),"mout_mfc_0" , group_div_mpll_pre_p, SRC_MFC, 0 , 1 ),/* SRC_G3D */ "mout_g3d" , mout_g3d_p, SRC_G3D, 8 , 1 ),"mout_g3d_1" , group_epll_vpll_p, SRC_G3D, 4 , 1 ),"mout_g3d_0" , group_div_mpll_pre_p, SRC_G3D, 0 , 1 ),/* SRC_LCD */ "mout_mipi0" , group_sclk_p, SRC_LCD, 12 , 4 ),"mout_fimd0" , group_sclk_fimd0_p, SRC_LCD, 0 , 4 ),/* SRC_ISP */ "mout_uart_isp" , group_sclk_p, SRC_ISP, 12 , 4 ),"mout_spi1_isp" , group_sclk_p, SRC_ISP, 8 , 4 ),"mout_spi0_isp" , group_sclk_p, SRC_ISP, 4 , 4 ),/* SRC_FSYS */ "mout_tsadc" , group_sclk_p, SRC_FSYS, 28 , 4 ),"mout_mmc2" , group_sclk_p, SRC_FSYS, 8 , 4 ),"mout_mmc1" , group_sclk_p, SRC_FSYS, 4 , 4 ),"mout_mmc0" , group_sclk_p, SRC_FSYS, 0 , 4 ),/* SRC_PERIL0 */ "mout_uart2" , group_sclk_p, SRC_PERIL0, 8 , 4 ),"mout_uart1" , group_sclk_p, SRC_PERIL0, 4 , 4 ),"mout_uart0" , group_sclk_p, SRC_PERIL0, 0 , 4 ),/* SRC_PERIL1 */ "mout_spi1" , group_sclk_p, SRC_PERIL1, 20 , 4 ),"mout_spi0" , group_sclk_p, SRC_PERIL1, 16 , 4 ),"mout_audio" , group_sclk_audio_p, SRC_PERIL1, 4 , 4 ),/* SRC_CPU */ "mout_mpll_user_c" , mout_mpll_user_p,24 , 1 ),"mout_hpm" , mout_hpm_p, SRC_CPU, 20 , 1 ),"mout_core" , mout_core_p, SRC_CPU, 16 , 1 ,0 ),"mout_apll" , mout_apll_p, SRC_CPU, 0 , 1 ,0 ),static const struct samsung_div_clock div_clks[] __initconst = {/* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done * in the User's Manual. When adding new entries, please make sure * that the order is preserved, to avoid merge conflicts and make * further work with defined data easier. /* DIV_LEFTBUS */ "div_gpl" , "div_gdl" , DIV_LEFTBUS, 4 , 3 ),"div_gdl" , "mout_gdl" , DIV_LEFTBUS, 0 , 4 ),/* DIV_RIGHTBUS */ "div_gpr" , "div_gdr" , DIV_RIGHTBUS, 4 , 3 ),"div_gdr" , "mout_gdr" , DIV_RIGHTBUS, 0 , 4 ),/* DIV_TOP */ "div_mpll_pre" , "sclk_mpll_mif" , DIV_TOP, 28 , 2 ),"div_aclk_400_mcuisp" ,"mout_aclk_400_mcuisp" , DIV_TOP, 24 , 3 ),"div_ebi" , "mout_ebi_1" , DIV_TOP, 16 , 3 ),"div_aclk_200" , "mout_aclk_200" , DIV_TOP, 12 , 3 ),"div_aclk_160" , "mout_aclk_160" , DIV_TOP, 8 , 3 ),"div_aclk_100" , "mout_aclk_100" , DIV_TOP, 4 , 4 ),"div_aclk_266" , "mout_aclk_266" , DIV_TOP, 0 , 3 ),/* DIV_CAM */ "div_cam1" , "mout_cam1" , DIV_CAM, 20 , 4 ),"div_cam_blk" , "mout_cam_blk" , DIV_CAM, 0 , 4 ),/* DIV_MFC */ "div_mfc" , "mout_mfc" , DIV_MFC, 0 , 4 ),/* DIV_G3D */ "div_g3d" , "mout_g3d" , DIV_G3D, 0 , 4 ),/* DIV_LCD */ "div_mipi0_pre" , "div_mipi0" , DIV_LCD, 20 , 4 ,0 ),"div_mipi0" , "mout_mipi0" , DIV_LCD, 16 , 4 ),"div_fimd0" , "mout_fimd0" , DIV_LCD, 0 , 4 ),/* DIV_ISP */ "div_uart_isp" , "mout_uart_isp" , DIV_ISP, 28 , 4 ),"div_spi1_isp_pre" , "div_spi1_isp" ,20 , 8 , CLK_SET_RATE_PARENT, 0 ),"div_spi1_isp" , "mout_spi1_isp" , DIV_ISP, 16 , 4 ),"div_spi0_isp_pre" , "div_spi0_isp" ,8 , 8 , CLK_SET_RATE_PARENT, 0 ),"div_spi0_isp" , "mout_spi0_isp" , DIV_ISP, 4 , 4 ),/* DIV_FSYS0 */ "div_tsadc_pre" , "div_tsadc" , DIV_FSYS0, 8 , 8 ,0 ),"div_tsadc" , "mout_tsadc" , DIV_FSYS0, 0 , 4 ),/* DIV_FSYS1 */ "div_mmc1_pre" , "div_mmc1" , DIV_FSYS1, 24 , 8 ,0 ),"div_mmc1" , "mout_mmc1" , DIV_FSYS1, 16 , 4 ),"div_mmc0_pre" , "div_mmc0" , DIV_FSYS1, 8 , 8 ,0 ),"div_mmc0" , "mout_mmc0" , DIV_FSYS1, 0 , 4 ),/* DIV_FSYS2 */ "div_mmc2_pre" , "div_mmc2" , DIV_FSYS2, 8 , 8 ,0 ),"div_mmc2" , "mout_mmc2" , DIV_FSYS2, 0 , 4 ),/* DIV_PERIL0 */ "div_uart2" , "mout_uart2" , DIV_PERIL0, 8 , 4 ),"div_uart1" , "mout_uart1" , DIV_PERIL0, 4 , 4 ),"div_uart0" , "mout_uart0" , DIV_PERIL0, 0 , 4 ),/* DIV_PERIL1 */ "div_spi1_pre" , "div_spi1" , DIV_PERIL1, 24 , 8 ,0 ),"div_spi1" , "mout_spi1" , DIV_PERIL1, 16 , 4 ),"div_spi0_pre" , "div_spi0" , DIV_PERIL1, 8 , 8 ,0 ),"div_spi0" , "mout_spi0" , DIV_PERIL1, 0 , 4 ),/* DIV_PERIL4 */ "div_pcm" , "div_audio" , DIV_PERIL4, 20 , 8 ),"div_audio" , "mout_audio" , DIV_PERIL4, 16 , 4 ),/* DIV_PERIL5 */ "div_i2s" , "div_audio" , DIV_PERIL5, 8 , 6 ),/* DIV_CPU0 */ "div_core2" , "div_core" , DIV_CPU0, 28 , 3 ),"div_apll" , "mout_apll" , DIV_CPU0, 24 , 3 ),"div_pclk_dbg" , "div_core2" , DIV_CPU0, 20 , 3 ),"div_atb" , "div_core2" , DIV_CPU0, 16 , 3 ),"div_corem" , "div_core2" , DIV_CPU0, 4 , 3 ),"div_core" , "mout_core" , DIV_CPU0, 0 , 3 ),/* DIV_CPU1 */ "div_hpm" , "div_copy" , DIV_CPU1, 4 , 3 ),"div_copy" , "mout_hpm" , DIV_CPU1, 0 , 3 ),static const struct samsung_gate_clock gate_clks[] __initconst = {/* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done * in the User's Manual. When adding new entries, please make sure * that the order is preserved, to avoid merge conflicts and make * further work with defined data easier. /* GATE_IP_LEFTBUS */ "async_g3d" , "div_aclk_100" , GATE_IP_LEFTBUS, 6 ,0 ),"async_mfcl" , "div_aclk_100" , GATE_IP_LEFTBUS, 4 ,0 ),"ppmuleft" , "div_aclk_100" , GATE_IP_LEFTBUS, 1 ,0 ),"gpio_left" , "div_aclk_100" , GATE_IP_LEFTBUS, 0 ,0 ),/* GATE_IP_RIGHTBUS */ "async_ispmx" , "div_aclk_100" ,9 , CLK_IGNORE_UNUSED, 0 ),"async_fsysd" , "div_aclk_100" ,5 , CLK_IGNORE_UNUSED, 0 ),"async_lcd0x" , "div_aclk_100" ,3 , CLK_IGNORE_UNUSED, 0 ),"async_camx" , "div_aclk_100" , GATE_IP_RIGHTBUS, 2 ,0 ),"ppmuright" , "div_aclk_100" , GATE_IP_RIGHTBUS, 1 ,0 ),"gpio_right" , "div_aclk_100" , GATE_IP_RIGHTBUS, 0 ,0 ),/* GATE_IP_PERIR */ "monocnt" , "div_aclk_100" , GATE_IP_PERIR, 22 ,0 ),"tzpc6" , "div_aclk_100" , GATE_IP_PERIR, 21 ,0 ),"provisionkey1" , "div_aclk_100" ,20 , CLK_IGNORE_UNUSED, 0 ),"provisionkey0" , "div_aclk_100" ,19 , CLK_IGNORE_UNUSED, 0 ),"cmu_isppart" , "div_aclk_100" , GATE_IP_PERIR, 18 ,0 ),"tmu_apbif" , "div_aclk_100" ,17 , 0 , 0 ),"keyif" , "div_aclk_100" , GATE_IP_PERIR, 16 , 0 , 0 ),"rtc" , "div_aclk_100" , GATE_IP_PERIR, 15 , 0 , 0 ),"wdt" , "div_aclk_100" , GATE_IP_PERIR, 14 , 0 , 0 ),"mct" , "div_aclk_100" , GATE_IP_PERIR, 13 , 0 , 0 ),"seckey" , "div_aclk_100" , GATE_IP_PERIR, 12 ,0 ),"tzpc5" , "div_aclk_100" , GATE_IP_PERIR, 10 ,0 ),"tzpc4" , "div_aclk_100" , GATE_IP_PERIR, 9 ,0 ),"tzpc3" , "div_aclk_100" , GATE_IP_PERIR, 8 ,0 ),"tzpc2" , "div_aclk_100" , GATE_IP_PERIR, 7 ,0 ),"tzpc1" , "div_aclk_100" , GATE_IP_PERIR, 6 ,0 ),"tzpc0" , "div_aclk_100" , GATE_IP_PERIR, 5 ,0 ),"cmu_corepart" , "div_aclk_100" , GATE_IP_PERIR, 4 ,0 ),"cmu_toppart" , "div_aclk_100" , GATE_IP_PERIR, 3 ,0 ),"pmu_apbif" , "div_aclk_100" , GATE_IP_PERIR, 2 ,0 ),"sysreg" , "div_aclk_100" , GATE_IP_PERIR, 1 ,0 ),"chip_id" , "div_aclk_100" , GATE_IP_PERIR, 0 ,0 ),/* GATE_SCLK_CAM */ "sclk_jpeg" , "div_cam_blk" ,8 , CLK_SET_RATE_PARENT, 0 ),"sclk_m2mscaler" , "div_cam_blk" ,2 , CLK_SET_RATE_PARENT, 0 ),"sclk_gscaler1" , "div_cam_blk" ,1 , CLK_SET_RATE_PARENT, 0 ),"sclk_gscaler0" , "div_cam_blk" ,0 , CLK_SET_RATE_PARENT, 0 ),/* GATE_SCLK_MFC */ "sclk_mfc" , "div_mfc" ,0 , CLK_SET_RATE_PARENT, 0 ),/* GATE_SCLK_G3D */ "sclk_g3d" , "div_g3d" ,0 , CLK_SET_RATE_PARENT, 0 ),/* GATE_SCLK_LCD */ "sclk_mipidphy2l" , "div_mipi0" ,4 , CLK_SET_RATE_PARENT, 0 ),"sclk_mipi0" , "div_mipi0_pre" ,3 , CLK_SET_RATE_PARENT, 0 ),"sclk_fimd0" , "div_fimd0" ,0 , CLK_SET_RATE_PARENT, 0 ),/* GATE_SCLK_ISP_TOP */ "sclk_cam1" , "div_cam1" ,4 , CLK_SET_RATE_PARENT, 0 ),"sclk_uart_isp" , "div_uart_isp" ,3 , CLK_SET_RATE_PARENT, 0 ),"sclk_spi1_isp" , "div_spi1_isp" ,2 , CLK_SET_RATE_PARENT, 0 ),"sclk_spi0_isp" , "div_spi0_isp" ,1 , CLK_SET_RATE_PARENT, 0 ),/* GATE_SCLK_FSYS */ "sclk_upll" , "mout_upll" , GATE_SCLK_FSYS, 10 , 0 , 0 ),"sclk_tsadc" , "div_tsadc_pre" ,9 , CLK_SET_RATE_PARENT, 0 ),"sclk_ebi" , "div_ebi" ,6 , CLK_SET_RATE_PARENT, 0 ),"sclk_mmc2" , "div_mmc2_pre" ,2 , CLK_SET_RATE_PARENT, 0 ),"sclk_mmc1" , "div_mmc1_pre" ,1 , CLK_SET_RATE_PARENT, 0 ),"sclk_mmc0" , "div_mmc0_pre" ,0 , CLK_SET_RATE_PARENT, 0 ),/* GATE_SCLK_PERIL */ "sclk_i2s" , "div_i2s" ,18 , CLK_SET_RATE_PARENT, 0 ),"sclk_pcm" , "div_pcm" ,16 , CLK_SET_RATE_PARENT, 0 ),"sclk_spi1" , "div_spi1_pre" ,7 , CLK_SET_RATE_PARENT, 0 ),"sclk_spi0" , "div_spi0_pre" ,6 , CLK_SET_RATE_PARENT, 0 ),"sclk_uart2" , "div_uart2" ,2 , CLK_SET_RATE_PARENT, 0 ),"sclk_uart1" , "div_uart1" ,1 , CLK_SET_RATE_PARENT, 0 ),"sclk_uart0" , "div_uart0" ,0 , CLK_SET_RATE_PARENT, 0 ),/* GATE_IP_CAM */ "qejpeg" , "div_cam_blk_320" , GATE_IP_CAM, 19 ,0 ),"pixelasyncm1" , "div_cam_blk_320" ,18 , CLK_IGNORE_UNUSED, 0 ),"pixelasyncm0" , "div_cam_blk_320" ,17 , CLK_IGNORE_UNUSED, 0 ),"ppmucamif" , "div_cam_blk_320" ,16 , CLK_IGNORE_UNUSED, 0 ),"qem2mscaler" , "div_cam_blk_320" ,14 , CLK_IGNORE_UNUSED, 0 ),"qegscaler1" , "div_cam_blk_320" ,13 , CLK_IGNORE_UNUSED, 0 ),"qegscaler0" , "div_cam_blk_320" ,12 , CLK_IGNORE_UNUSED, 0 ),"smmujpeg" , "div_cam_blk_320" ,11 , 0 , 0 ),"smmum2m2scaler" , "div_cam_blk_320" ,9 , 0 , 0 ),"smmugscaler1" , "div_cam_blk_320" ,8 , 0 , 0 ),"smmugscaler0" , "div_cam_blk_320" ,7 , 0 , 0 ),"jpeg" , "div_cam_blk_320" , GATE_IP_CAM, 6 , 0 , 0 ),"m2mscaler" , "div_cam_blk_320" ,2 , 0 , 0 ),"gscaler1" , "div_cam_blk_320" , GATE_IP_CAM, 1 , 0 , 0 ),"gscaler0" , "div_cam_blk_320" , GATE_IP_CAM, 0 , 0 , 0 ),/* GATE_IP_MFC */ "qemfc" , "div_aclk_200" , GATE_IP_MFC, 5 ,0 ),"ppmumfc_l" , "div_aclk_200" , GATE_IP_MFC, 3 ,0 ),"smmumfc_l" , "div_aclk_200" , GATE_IP_MFC, 1 , 0 , 0 ),"mfc" , "div_aclk_200" , GATE_IP_MFC, 0 , 0 , 0 ),/* GATE_IP_G3D */ "smmug3d" , "div_aclk_200" , GATE_IP_G3D, 3 , 0 , 0 ),"qeg3d" , "div_aclk_200" , GATE_IP_G3D, 2 ,0 ),"ppmug3d" , "div_aclk_200" , GATE_IP_G3D, 1 ,0 ),"g3d" , "div_aclk_200" , GATE_IP_G3D, 0 , 0 , 0 ),/* GATE_IP_LCD */ "qe_ch1_lcd" , "div_aclk_160" , GATE_IP_LCD, 7 ,0 ),"qe_ch0_lcd" , "div_aclk_160" , GATE_IP_LCD, 6 ,0 ),"ppmulcd0" , "div_aclk_160" , GATE_IP_LCD, 5 ,0 ),"smmufimd0" , "div_aclk_160" , GATE_IP_LCD, 4 , 0 , 0 ),"dsim0" , "div_aclk_160" , GATE_IP_LCD, 3 , 0 , 0 ),"smies" , "div_aclk_160" , GATE_IP_LCD, 2 , 0 , 0 ),"fimd0" , "div_aclk_160" , GATE_IP_LCD, 0 , 0 , 0 ),/* GATE_IP_ISP */ "cam1" , "mout_aclk_266_sub" , GATE_IP_ISP, 5 , 0 , 0 ),"uart_isp_top" , "mout_aclk_266_sub" ,3 , 0 , 0 ),"spi1_isp_top" , "mout_aclk_266_sub" ,2 , 0 , 0 ),"spi0_isp_top" , "mout_aclk_266_sub" ,1 , 0 , 0 ),/* GATE_IP_FSYS */ "tsadc" , "div_aclk_200" , GATE_IP_FSYS, 20 , 0 , 0 ),"ppmufile" , "div_aclk_200" , GATE_IP_FSYS, 17 ,0 ),"usbotg" , "div_aclk_200" , GATE_IP_FSYS, 13 , 0 , 0 ),"usbhost" , "div_aclk_200" , GATE_IP_FSYS, 12 , 0 , 0 ),"sromc" , "div_aclk_200" , GATE_IP_FSYS, 11 , 0 , 0 ),"sdmmc2" , "div_aclk_200" , GATE_IP_FSYS, 7 , 0 , 0 ),"sdmmc1" , "div_aclk_200" , GATE_IP_FSYS, 6 , 0 , 0 ),"sdmmc0" , "div_aclk_200" , GATE_IP_FSYS, 5 , 0 , 0 ),"pdma1" , "div_aclk_200" , GATE_IP_FSYS, 1 , 0 , 0 ),"pdma0" , "div_aclk_200" , GATE_IP_FSYS, 0 , 0 , 0 ),/* GATE_IP_PERIL */ "pwm" , "div_aclk_100" , GATE_IP_PERIL, 24 , 0 , 0 ),"pcm" , "div_aclk_100" , GATE_IP_PERIL, 23 , 0 , 0 ),"i2s" , "div_aclk_100" , GATE_IP_PERIL, 21 , 0 , 0 ),"spi1" , "div_aclk_100" , GATE_IP_PERIL, 17 , 0 , 0 ),"spi0" , "div_aclk_100" , GATE_IP_PERIL, 16 , 0 , 0 ),"i2c7" , "div_aclk_100" , GATE_IP_PERIL, 13 , 0 , 0 ),"i2c6" , "div_aclk_100" , GATE_IP_PERIL, 12 , 0 , 0 ),"i2c5" , "div_aclk_100" , GATE_IP_PERIL, 11 , 0 , 0 ),"i2c4" , "div_aclk_100" , GATE_IP_PERIL, 10 , 0 , 0 ),"i2c3" , "div_aclk_100" , GATE_IP_PERIL, 9 , 0 , 0 ),"i2c2" , "div_aclk_100" , GATE_IP_PERIL, 8 , 0 , 0 ),"i2c1" , "div_aclk_100" , GATE_IP_PERIL, 7 , 0 , 0 ),"i2c0" , "div_aclk_100" , GATE_IP_PERIL, 6 , 0 , 0 ),"uart2" , "div_aclk_100" , GATE_IP_PERIL, 2 , 0 , 0 ),"uart1" , "div_aclk_100" , GATE_IP_PERIL, 1 , 0 , 0 ),"uart0" , "div_aclk_100" , GATE_IP_PERIL, 0 , 0 , 0 ),/* APLL & MPLL & BPLL & UPLL */ static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = {24 * MHZ, 1200000000 , 400 , 4 , 1 ),24 * MHZ, 1100000000 , 275 , 3 , 1 ),24 * MHZ, 1066000000 , 533 , 6 , 1 ),24 * MHZ, 1000000000 , 250 , 3 , 1 ),24 * MHZ, 960000000 , 320 , 4 , 1 ),24 * MHZ, 900000000 , 300 , 4 , 1 ),24 * MHZ, 850000000 , 425 , 6 , 1 ),24 * MHZ, 800000000 , 200 , 3 , 1 ),24 * MHZ, 700000000 , 175 , 3 , 1 ),24 * MHZ, 667000000 , 667 , 12 , 1 ),24 * MHZ, 600000000 , 400 , 4 , 2 ),24 * MHZ, 533000000 , 533 , 6 , 2 ),24 * MHZ, 520000000 , 260 , 3 , 2 ),24 * MHZ, 500000000 , 250 , 3 , 2 ),24 * MHZ, 400000000 , 200 , 3 , 2 ),24 * MHZ, 200000000 , 200 , 3 , 3 ),24 * MHZ, 100000000 , 200 , 3 , 4 ),/* sentinel */ } /* EPLL */ static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = {24 * MHZ, 800000000 , 200 , 3 , 1 , 0 ),24 * MHZ, 288000000 , 96 , 2 , 2 , 0 ),24 * MHZ, 192000000 , 128 , 2 , 3 , 0 ),24 * MHZ, 144000000 , 96 , 2 , 3 , 0 ),24 * MHZ, 96000000 , 128 , 2 , 4 , 0 ),24 * MHZ, 84000000 , 112 , 2 , 4 , 0 ),24 * MHZ, 80000003 , 106 , 2 , 4 , 43691 ),24 * MHZ, 73728000 , 98 , 2 , 4 , 19923 ),24 * MHZ, 67737598 , 270 , 3 , 5 , 62285 ),24 * MHZ, 65535999 , 174 , 2 , 5 , 49982 ),24 * MHZ, 50000000 , 200 , 3 , 5 , 0 ),24 * MHZ, 49152002 , 131 , 2 , 5 , 4719 ),24 * MHZ, 48000000 , 128 , 2 , 5 , 0 ),24 * MHZ, 45158401 , 180 , 3 , 5 , 41524 ),/* sentinel */ } /* VPLL */ static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = {24 * MHZ, 600000000 , 100 , 2 , 1 , 0 ),24 * MHZ, 533000000 , 266 , 3 , 2 , 32768 ),24 * MHZ, 519230987 , 173 , 2 , 2 , 5046 ),24 * MHZ, 500000000 , 250 , 3 , 2 , 0 ),24 * MHZ, 445500000 , 148 , 2 , 2 , 32768 ),24 * MHZ, 445055007 , 148 , 2 , 2 , 23047 ),24 * MHZ, 400000000 , 200 , 3 , 2 , 0 ),24 * MHZ, 371250000 , 123 , 2 , 2 , 49152 ),24 * MHZ, 370878997 , 185 , 3 , 2 , 28803 ),24 * MHZ, 340000000 , 170 , 3 , 2 , 0 ),24 * MHZ, 335000015 , 111 , 2 , 2 , 43691 ),24 * MHZ, 333000000 , 111 , 2 , 2 , 0 ),24 * MHZ, 330000000 , 110 , 2 , 2 , 0 ),24 * MHZ, 320000015 , 106 , 2 , 2 , 43691 ),24 * MHZ, 300000000 , 100 , 2 , 2 , 0 ),24 * MHZ, 275000000 , 275 , 3 , 3 , 0 ),24 * MHZ, 222750000 , 148 , 2 , 3 , 32768 ),24 * MHZ, 222528007 , 148 , 2 , 3 , 23069 ),24 * MHZ, 160000000 , 160 , 3 , 3 , 0 ),24 * MHZ, 148500000 , 99 , 2 , 3 , 0 ),24 * MHZ, 148352005 , 98 , 2 , 3 , 59070 ),24 * MHZ, 108000000 , 144 , 2 , 4 , 0 ),24 * MHZ, 74250000 , 99 , 2 , 4 , 0 ),24 * MHZ, 74176002 , 98 , 2 , 4 , 59070 ),24 * MHZ, 54054000 , 216 , 3 , 5 , 14156 ),24 * MHZ, 54000000 , 144 , 2 , 5 , 0 ),/* sentinel */ } static const struct samsung_pll_clock exynos3250_plls[] __initconst = {"fout_apll" , "fin_pll" ,"fout_mpll" , "fin_pll" ,"fout_vpll" , "fin_pll" ,"fout_upll" , "fin_pll" ,#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \24 ) | ((pclk_dbg) << 20 ) | ((atb) << 16 ) | \4 ))#define E3250_CPU_DIV1(hpm, copy) \4 ) | ((copy) << 0 ))static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {1000000 , E3250_CPU_DIV0(1 , 7 , 4 , 1 ), E3250_CPU_DIV1(7 , 7 ), },900000 , E3250_CPU_DIV0(1 , 7 , 3 , 1 ), E3250_CPU_DIV1(7 , 7 ), },800000 , E3250_CPU_DIV0(1 , 7 , 3 , 1 ), E3250_CPU_DIV1(7 , 7 ), },700000 , E3250_CPU_DIV0(1 , 7 , 3 , 1 ), E3250_CPU_DIV1(7 , 7 ), },600000 , E3250_CPU_DIV0(1 , 7 , 3 , 1 ), E3250_CPU_DIV1(7 , 7 ), },500000 , E3250_CPU_DIV0(1 , 7 , 3 , 1 ), E3250_CPU_DIV1(7 , 7 ), },400000 , E3250_CPU_DIV0(1 , 7 , 3 , 1 ), E3250_CPU_DIV1(7 , 7 ), },300000 , E3250_CPU_DIV0(1 , 5 , 3 , 1 ), E3250_CPU_DIV1(7 , 7 ), },200000 , E3250_CPU_DIV0(1 , 3 , 3 , 1 ), E3250_CPU_DIV1(7 , 7 ), },100000 , E3250_CPU_DIV0(1 , 1 , 1 , 1 ), E3250_CPU_DIV1(7 , 7 ), },0 },static const struct samsung_cpu_clock exynos3250_cpu_clks[] __initconst = {"armclk" , CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,0 x14000, CPUCLK_LAYOUT_E4210, e3250_armclk_d),static void __init exynos3_core_down_clock(void __iomem *reg_base)unsigned int tmp;/* * Enable arm clock down (in idle) and set arm divider * ratios in WFI/WFE state. 7 ) | PWR_CTRL1_CORE1_DOWN_RATIO(7 ) |/* * Disable the clock up feature on Exynos4x12, in case it was * enabled by bootloader. 0 x0, reg_base + PWR_CTRL2);static const struct samsung_cmu_info cmu_info __initconst = {static void __init exynos3250_cmu_init(struct device_node *np)struct samsung_clk_provider *ctx;if (!ctx)return ;"samsung,exynos3250-cmu" , exynos3250_cmu_init);/* * CMU DMC #define BPLL_LOCK 0 x0118#define BPLL_CON0 0 x0218#define BPLL_CON1 0 x021c#define BPLL_CON2 0 x0220#define SRC_DMC 0 x0300#define DIV_DMC1 0 x0504#define GATE_BUS_DMC0 0 x0700#define GATE_BUS_DMC1 0 x0704#define GATE_BUS_DMC2 0 x0708#define GATE_BUS_DMC3 0 x070c#define GATE_SCLK_DMC 0 x0800#define GATE_IP_DMC0 0 x0900#define GATE_IP_DMC1 0 x0904#define EPLL_LOCK 0 x1110#define EPLL_CON0 0 x1114#define EPLL_CON1 0 x1118#define EPLL_CON2 0 x111c#define SRC_EPLL 0 x1120static const unsigned long exynos3250_cmu_dmc_clk_regs[] __initconst = {"fin_pll" , "fout_epll" , };"fin_pll" , "fout_bpll" , };"fin_pll" , "sclk_mpll_mif" , };"mout_mpll_mif" , "mout_bpll" , };static const struct samsung_mux_clock dmc_mux_clks[] __initconst = {/* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done * in the User's Manual. When adding new entries, please make sure * that the order is preserved, to avoid merge conflicts and make * further work with defined data easier. /* SRC_DMC */ "mout_mpll_mif" , mout_mpll_mif_p, SRC_DMC, 12 , 1 ),"mout_bpll" , mout_bpll_p, SRC_DMC, 10 , 1 ),"mout_dphy" , mout_dphy_p, SRC_DMC, 8 , 1 ),"mout_dmc_bus" , mout_dphy_p, SRC_DMC, 4 , 1 ),/* SRC_EPLL */ "mout_epll" , mout_epll_p, SRC_EPLL, 4 , 1 ),static const struct samsung_div_clock dmc_div_clks[] __initconst = {/* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done * in the User's Manual. When adding new entries, please make sure * that the order is preserved, to avoid merge conflicts and make * further work with defined data easier. /* DIV_DMC1 */ "div_dmc" , "div_dmc_pre" , DIV_DMC1, 27 , 3 ),"div_dphy" , "mout_dphy" , DIV_DMC1, 23 , 3 ),"div_dmc_pre" , "mout_dmc_bus" , DIV_DMC1, 19 , 2 ),"div_dmcp" , "div_dmcd" , DIV_DMC1, 15 , 3 ),"div_dmcd" , "div_dmc" , DIV_DMC1, 11 , 3 ),static const struct samsung_pll_clock exynos3250_dmc_plls[] __initconst = {"fout_bpll" , "fin_pll" ,"fout_epll" , "fin_pll" ,static const struct samsung_cmu_info dmc_cmu_info __initconst = {static void __init exynos3250_cmu_dmc_init(struct device_node *np)"samsung,exynos3250-cmu-dmc" ,/* * CMU ISP #define DIV_ISP0 0 x300#define DIV_ISP1 0 x304#define GATE_IP_ISP0 0 x800#define GATE_IP_ISP1 0 x804#define GATE_SCLK_ISP 0 x900static const struct samsung_div_clock isp_div_clks[] __initconst = {/* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done * in the User's Manual. When adding new entries, please make sure * that the order is preserved, to avoid merge conflicts and make * further work with defined data easier. /* DIV_ISP0 */ "div_isp1" , "mout_aclk_266_sub" , DIV_ISP0, 4 , 3 ),"div_isp0" , "mout_aclk_266_sub" , DIV_ISP0, 0 , 3 ),/* DIV_ISP1 */ "div_mcuisp1" , "mout_aclk_400_mcuisp_sub" ,8 , 3 ),"div_mcuisp0" , "mout_aclk_400_mcuisp_sub" ,4 , 3 ),"div_mpwm" , "div_isp1" , DIV_ISP1, 0 , 3 ),static const struct samsung_gate_clock isp_gate_clks[] __initconst = {/* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done * in the User's Manual. When adding new entries, please make sure * that the order is preserved, to avoid merge conflicts and make * further work with defined data easier. /* GATE_IP_ISP0 */ "uart_isp" , "uart_isp_top" ,31 , CLK_IGNORE_UNUSED, 0 ),"wdt_isp" , "mout_aclk_266_sub" ,30 , CLK_IGNORE_UNUSED, 0 ),"pwm_isp" , "mout_aclk_266_sub" ,28 , CLK_IGNORE_UNUSED, 0 ),"i2c1_isp" , "mout_aclk_266_sub" ,26 , CLK_IGNORE_UNUSED, 0 ),"i2c0_isp" , "mout_aclk_266_sub" ,25 , CLK_IGNORE_UNUSED, 0 ),"mpwm_isp" , "mout_aclk_266_sub" ,24 , CLK_IGNORE_UNUSED, 0 ),"mcuctl_isp" , "mout_aclk_266_sub" ,23 , CLK_IGNORE_UNUSED, 0 ),"ppmuispx" , "mout_aclk_266_sub" ,21 , CLK_IGNORE_UNUSED, 0 ),"ppmuispmx" , "mout_aclk_266_sub" ,20 , CLK_IGNORE_UNUSED, 0 ),"qe_lite1" , "mout_aclk_266_sub" ,18 , CLK_IGNORE_UNUSED, 0 ),"qe_lite0" , "mout_aclk_266_sub" ,17 , CLK_IGNORE_UNUSED, 0 ),"qe_fd" , "mout_aclk_266_sub" ,16 , CLK_IGNORE_UNUSED, 0 ),"qe_drc" , "mout_aclk_266_sub" ,15 , CLK_IGNORE_UNUSED, 0 ),"qe_isp" , "mout_aclk_266_sub" ,14 , CLK_IGNORE_UNUSED, 0 ),"csis1" , "mout_aclk_266_sub" ,13 , CLK_IGNORE_UNUSED, 0 ),"smmu_lite1" , "mout_aclk_266_sub" ,12 , CLK_IGNORE_UNUSED, 0 ),"smmu_lite0" , "mout_aclk_266_sub" ,11 , CLK_IGNORE_UNUSED, 0 ),"smmu_fd" , "mout_aclk_266_sub" ,10 , CLK_IGNORE_UNUSED, 0 ),"smmu_drc" , "mout_aclk_266_sub" ,9 , CLK_IGNORE_UNUSED, 0 ),"smmu_isp" , "mout_aclk_266_sub" ,8 , CLK_IGNORE_UNUSED, 0 ),"gicisp" , "mout_aclk_266_sub" ,7 , CLK_IGNORE_UNUSED, 0 ),"csis0" , "mout_aclk_266_sub" ,6 , CLK_IGNORE_UNUSED, 0 ),"mcuisp" , "mout_aclk_266_sub" ,5 , CLK_IGNORE_UNUSED, 0 ),"lite1" , "mout_aclk_266_sub" ,4 , CLK_IGNORE_UNUSED, 0 ),"lite0" , "mout_aclk_266_sub" ,3 , CLK_IGNORE_UNUSED, 0 ),"fd" , "mout_aclk_266_sub" ,2 , CLK_IGNORE_UNUSED, 0 ),"drc" , "mout_aclk_266_sub" ,1 , CLK_IGNORE_UNUSED, 0 ),"isp" , "mout_aclk_266_sub" ,0 , CLK_IGNORE_UNUSED, 0 ),/* GATE_IP_ISP1 */ "qe_ispcx" , "uart_isp_top" ,21 , CLK_IGNORE_UNUSED, 0 ),"qe_scalerp" , "uart_isp_top" ,20 , CLK_IGNORE_UNUSED, 0 ),"qe_scalerc" , "uart_isp_top" ,19 , CLK_IGNORE_UNUSED, 0 ),"smmu_scalerp" , "uart_isp_top" ,18 , CLK_IGNORE_UNUSED, 0 ),"smmu_scalerc" , "uart_isp_top" ,17 , CLK_IGNORE_UNUSED, 0 ),"scalerp" , "uart_isp_top" ,16 , CLK_IGNORE_UNUSED, 0 ),"scalerc" , "uart_isp_top" ,15 , CLK_IGNORE_UNUSED, 0 ),"spi1_isp" , "uart_isp_top" ,13 , CLK_IGNORE_UNUSED, 0 ),"spi0_isp" , "uart_isp_top" ,12 , CLK_IGNORE_UNUSED, 0 ),"smmu_ispcx" , "uart_isp_top" ,4 , CLK_IGNORE_UNUSED, 0 ),"asyncaxim" , "uart_isp_top" ,0 , CLK_IGNORE_UNUSED, 0 ),/* GATE_SCLK_ISP */ "sclk_mpwm_isp" , "div_mpwm" ,0 , CLK_IGNORE_UNUSED, 0 ),static const struct samsung_cmu_info isp_cmu_info __initconst = {static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)struct device_node *np = pdev->dev.of_node;return 0 ;static const struct of_device_id exynos3250_cmu_isp_of_match[] __initconst = {"samsung,exynos3250-cmu-isp" , },/* sentinel */ } static struct platform_driver exynos3250_cmu_isp_driver __initdata = {"exynos3250-cmu-isp" ,true ,static int __init exynos3250_cmu_platform_init(void )return platform_driver_probe(&exynos3250_cmu_isp_driver,
Messung V0.5 in Prozent C=92 H=92 G=91
¤ Dauer der Verarbeitung: 0.16 Sekunden
(vorverarbeitet am 2026-06-05)
¤ *© Formatika GbR, Deutschland
