Quellcodebibliothek Statistik Leitseite products/Sources/formale Sprachen/C/Linux/drivers/clk/rockchip/   (Open Source Betriebssystem Version 6.17.9©)  Datei vom 24.10.2025 mit Größe 12 kB image not shown  

Quelle  rst-rk3528.c

  Sprache: C
 

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 * Based on Sebastian Reichel's implementation for RK3588
 */


#include <linux/module.h>
#include <linux/of.h>
#include <dt-bindings/reset/rockchip,rk3528-cru.h>
#include "clk.h"

/* 0xFF4A0000 + 0x0A00 */
#define RK3528_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)

/* mapping table for reset ID to register offset */
static const int rk3528_register_offset[] = {
 /* CRU_SOFTRST_CON03 */
 RK3528_CRU_RESET_OFFSET(SRST_CORE0_PO, 30),
 RK3528_CRU_RESET_OFFSET(SRST_CORE1_PO, 31),
 RK3528_CRU_RESET_OFFSET(SRST_CORE2_PO, 32),
 RK3528_CRU_RESET_OFFSET(SRST_CORE3_PO, 33),
 RK3528_CRU_RESET_OFFSET(SRST_CORE0, 34),
 RK3528_CRU_RESET_OFFSET(SRST_CORE1, 35),
 RK3528_CRU_RESET_OFFSET(SRST_CORE2, 36),
 RK3528_CRU_RESET_OFFSET(SRST_CORE3, 37),
 RK3528_CRU_RESET_OFFSET(SRST_NL2, 38),
 RK3528_CRU_RESET_OFFSET(SRST_CORE_BIU, 39),
 RK3528_CRU_RESET_OFFSET(SRST_CORE_CRYPTO, 310),

 /* CRU_SOFTRST_CON05 */
 RK3528_CRU_RESET_OFFSET(SRST_P_DBG, 513),
 RK3528_CRU_RESET_OFFSET(SRST_POT_DBG, 514),
 RK3528_CRU_RESET_OFFSET(SRST_NT_DBG, 515),

 /* CRU_SOFTRST_CON06 */
 RK3528_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 62),
 RK3528_CRU_RESET_OFFSET(SRST_P_DAPLITE_BIU, 63),
 RK3528_CRU_RESET_OFFSET(SRST_P_CPU_BIU, 64),
 RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 67),

 /* CRU_SOFTRST_CON08 */
 RK3528_CRU_RESET_OFFSET(SRST_A_BUS_VOPGL_BIU, 81),
 RK3528_CRU_RESET_OFFSET(SRST_A_BUS_H_BIU, 83),
 RK3528_CRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 88),
 RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 810),
 RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 811),
 RK3528_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 812),
 RK3528_CRU_RESET_OFFSET(SRST_P_DFT2APB, 813),
 RK3528_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 815),

 /* CRU_SOFTRST_CON09 */
 RK3528_CRU_RESET_OFFSET(SRST_A_BUS_M_BIU, 90),
 RK3528_CRU_RESET_OFFSET(SRST_A_GIC, 91),
 RK3528_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 92),
 RK3528_CRU_RESET_OFFSET(SRST_A_DMAC, 94),
 RK3528_CRU_RESET_OFFSET(SRST_P_TIMER, 95),
 RK3528_CRU_RESET_OFFSET(SRST_TIMER0, 96),
 RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 97),
 RK3528_CRU_RESET_OFFSET(SRST_TIMER2, 98),
 RK3528_CRU_RESET_OFFSET(SRST_TIMER3, 99),
 RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 910),
 RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 911),
 RK3528_CRU_RESET_OFFSET(SRST_P_JDBCK_DAP, 912),
 RK3528_CRU_RESET_OFFSET(SRST_JDBCK_DAP, 913),
 RK3528_CRU_RESET_OFFSET(SRST_P_WDT_NS, 915),

 /* CRU_SOFTRST_CON10 */
 RK3528_CRU_RESET_OFFSET(SRST_T_WDT_NS, 100),
 RK3528_CRU_RESET_OFFSET(SRST_H_TRNG_NS, 103),
 RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 107),
 RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 108),
 RK3528_CRU_RESET_OFFSET(SRST_PKA_CRYPTO, 1010),
 RK3528_CRU_RESET_OFFSET(SRST_A_CRYPTO, 1011),
 RK3528_CRU_RESET_OFFSET(SRST_H_CRYPTO, 1012),
 RK3528_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 1013),
 RK3528_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 1014),

 /* CRU_SOFTRST_CON11 */
 RK3528_CRU_RESET_OFFSET(SRST_P_PWM0, 114),
 RK3528_CRU_RESET_OFFSET(SRST_PWM0, 115),
 RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 117),
 RK3528_CRU_RESET_OFFSET(SRST_PWM1, 118),
 RK3528_CRU_RESET_OFFSET(SRST_P_SCR, 1110),
 RK3528_CRU_RESET_OFFSET(SRST_A_DCF, 1111),
 RK3528_CRU_RESET_OFFSET(SRST_P_INTMUX, 1112),

 /* CRU_SOFTRST_CON25 */
 RK3528_CRU_RESET_OFFSET(SRST_A_VPU_BIU, 256),
 RK3528_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 257),
 RK3528_CRU_RESET_OFFSET(SRST_P_VPU_BIU, 258),
 RK3528_CRU_RESET_OFFSET(SRST_A_VPU, 259),
 RK3528_CRU_RESET_OFFSET(SRST_H_VPU, 2510),
 RK3528_CRU_RESET_OFFSET(SRST_P_CRU_PCIE, 2511),
 RK3528_CRU_RESET_OFFSET(SRST_P_VPU_GRF, 2512),
 RK3528_CRU_RESET_OFFSET(SRST_H_SFC, 2513),
 RK3528_CRU_RESET_OFFSET(SRST_S_SFC, 2514),
 RK3528_CRU_RESET_OFFSET(SRST_C_EMMC, 2515),

 /* CRU_SOFTRST_CON26 */
 RK3528_CRU_RESET_OFFSET(SRST_H_EMMC, 260),
 RK3528_CRU_RESET_OFFSET(SRST_A_EMMC, 261),
 RK3528_CRU_RESET_OFFSET(SRST_B_EMMC, 262),
 RK3528_CRU_RESET_OFFSET(SRST_T_EMMC, 263),
 RK3528_CRU_RESET_OFFSET(SRST_P_GPIO1, 264),
 RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO1, 265),
 RK3528_CRU_RESET_OFFSET(SRST_A_VPU_L_BIU, 266),
 RK3528_CRU_RESET_OFFSET(SRST_P_VPU_IOC, 268),
 RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S0, 269),
 RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S0, 2610),
 RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S2, 2611),
 RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S2, 2612),
 RK3528_CRU_RESET_OFFSET(SRST_P_ACODEC, 2613),

 /* CRU_SOFTRST_CON27 */
 RK3528_CRU_RESET_OFFSET(SRST_P_GPIO3, 270),
 RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO3, 271),
 RK3528_CRU_RESET_OFFSET(SRST_P_SPI1, 274),
 RK3528_CRU_RESET_OFFSET(SRST_SPI1, 275),
 RK3528_CRU_RESET_OFFSET(SRST_P_UART2, 277),
 RK3528_CRU_RESET_OFFSET(SRST_S_UART2, 278),
 RK3528_CRU_RESET_OFFSET(SRST_P_UART5, 279),
 RK3528_CRU_RESET_OFFSET(SRST_S_UART5, 2710),
 RK3528_CRU_RESET_OFFSET(SRST_P_UART6, 2711),
 RK3528_CRU_RESET_OFFSET(SRST_S_UART6, 2712),
 RK3528_CRU_RESET_OFFSET(SRST_P_UART7, 2713),
 RK3528_CRU_RESET_OFFSET(SRST_S_UART7, 2714),
 RK3528_CRU_RESET_OFFSET(SRST_P_I2C3, 2715),

 /* CRU_SOFTRST_CON28 */
 RK3528_CRU_RESET_OFFSET(SRST_I2C3, 280),
 RK3528_CRU_RESET_OFFSET(SRST_P_I2C5, 281),
 RK3528_CRU_RESET_OFFSET(SRST_I2C5, 282),
 RK3528_CRU_RESET_OFFSET(SRST_P_I2C6, 283),
 RK3528_CRU_RESET_OFFSET(SRST_I2C6, 284),
 RK3528_CRU_RESET_OFFSET(SRST_A_MAC, 285),

 /* CRU_SOFTRST_CON30 */
 RK3528_CRU_RESET_OFFSET(SRST_P_PCIE, 301),
 RK3528_CRU_RESET_OFFSET(SRST_PCIE_PIPE_PHY, 302),
 RK3528_CRU_RESET_OFFSET(SRST_PCIE_POWER_UP, 303),
 RK3528_CRU_RESET_OFFSET(SRST_P_PCIE_PHY, 306),
 RK3528_CRU_RESET_OFFSET(SRST_P_PIPE_GRF, 307),

 /* CRU_SOFTRST_CON32 */
 RK3528_CRU_RESET_OFFSET(SRST_H_SDIO0, 322),
 RK3528_CRU_RESET_OFFSET(SRST_H_SDIO1, 324),
 RK3528_CRU_RESET_OFFSET(SRST_TS_0, 325),
 RK3528_CRU_RESET_OFFSET(SRST_TS_1, 326),
 RK3528_CRU_RESET_OFFSET(SRST_P_CAN2, 327),
 RK3528_CRU_RESET_OFFSET(SRST_CAN2, 328),
 RK3528_CRU_RESET_OFFSET(SRST_P_CAN3, 329),
 RK3528_CRU_RESET_OFFSET(SRST_CAN3, 3210),
 RK3528_CRU_RESET_OFFSET(SRST_P_SARADC, 3211),
 RK3528_CRU_RESET_OFFSET(SRST_SARADC, 3212),
 RK3528_CRU_RESET_OFFSET(SRST_SARADC_PHY, 3213),
 RK3528_CRU_RESET_OFFSET(SRST_P_TSADC, 3214),
 RK3528_CRU_RESET_OFFSET(SRST_TSADC, 3215),

 /* CRU_SOFTRST_CON33 */
 RK3528_CRU_RESET_OFFSET(SRST_A_USB3OTG, 331),

 /* CRU_SOFTRST_CON34 */
 RK3528_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 343),
 RK3528_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 345),
 RK3528_CRU_RESET_OFFSET(SRST_A_GPU, 348),
 RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 349),

 /* CRU_SOFTRST_CON36 */
 RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC_BIU, 363),
 RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC_BIU, 364),
 RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_BIU, 365),
 RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC, 366),
 RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC, 367),
 RK3528_CRU_RESET_OFFSET(SRST_CORE_RKVENC, 368),
 RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S1, 369),
 RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S1, 3610),
 RK3528_CRU_RESET_OFFSET(SRST_P_I2C1, 3611),
 RK3528_CRU_RESET_OFFSET(SRST_I2C1, 3612),
 RK3528_CRU_RESET_OFFSET(SRST_P_I2C0, 3613),
 RK3528_CRU_RESET_OFFSET(SRST_I2C0, 3614),

 /* CRU_SOFTRST_CON37 */
 RK3528_CRU_RESET_OFFSET(SRST_P_SPI0, 372),
 RK3528_CRU_RESET_OFFSET(SRST_SPI0, 373),
 RK3528_CRU_RESET_OFFSET(SRST_P_GPIO4, 378),
 RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO4, 379),
 RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_IOC, 3710),
 RK3528_CRU_RESET_OFFSET(SRST_H_SPDIF, 3714),
 RK3528_CRU_RESET_OFFSET(SRST_M_SPDIF, 3715),

 /* CRU_SOFTRST_CON38 */
 RK3528_CRU_RESET_OFFSET(SRST_H_PDM, 380),
 RK3528_CRU_RESET_OFFSET(SRST_M_PDM, 381),
 RK3528_CRU_RESET_OFFSET(SRST_P_UART1, 382),
 RK3528_CRU_RESET_OFFSET(SRST_S_UART1, 383),
 RK3528_CRU_RESET_OFFSET(SRST_P_UART3, 384),
 RK3528_CRU_RESET_OFFSET(SRST_S_UART3, 385),
 RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_GRF, 386),
 RK3528_CRU_RESET_OFFSET(SRST_P_CAN0, 387),
 RK3528_CRU_RESET_OFFSET(SRST_CAN0, 388),
 RK3528_CRU_RESET_OFFSET(SRST_P_CAN1, 389),
 RK3528_CRU_RESET_OFFSET(SRST_CAN1, 3810),

 /* CRU_SOFTRST_CON39 */
 RK3528_CRU_RESET_OFFSET(SRST_A_VO_BIU, 393),
 RK3528_CRU_RESET_OFFSET(SRST_H_VO_BIU, 394),
 RK3528_CRU_RESET_OFFSET(SRST_P_VO_BIU, 395),
 RK3528_CRU_RESET_OFFSET(SRST_H_RGA2E, 397),
 RK3528_CRU_RESET_OFFSET(SRST_A_RGA2E, 398),
 RK3528_CRU_RESET_OFFSET(SRST_CORE_RGA2E, 399),
 RK3528_CRU_RESET_OFFSET(SRST_H_VDPP, 3910),
 RK3528_CRU_RESET_OFFSET(SRST_A_VDPP, 3911),
 RK3528_CRU_RESET_OFFSET(SRST_CORE_VDPP, 3912),
 RK3528_CRU_RESET_OFFSET(SRST_P_VO_GRF, 3913),
 RK3528_CRU_RESET_OFFSET(SRST_P_CRU, 3915),

 /* CRU_SOFTRST_CON40 */
 RK3528_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 401),
 RK3528_CRU_RESET_OFFSET(SRST_H_VOP, 402),
 RK3528_CRU_RESET_OFFSET(SRST_D_VOP0, 403),
 RK3528_CRU_RESET_OFFSET(SRST_D_VOP1, 404),
 RK3528_CRU_RESET_OFFSET(SRST_A_VOP, 405),
 RK3528_CRU_RESET_OFFSET(SRST_P_HDMI, 406),
 RK3528_CRU_RESET_OFFSET(SRST_HDMI, 407),
 RK3528_CRU_RESET_OFFSET(SRST_P_HDMIPHY, 4014),
 RK3528_CRU_RESET_OFFSET(SRST_H_HDCP_KEY, 4015),

 /* CRU_SOFTRST_CON41 */
 RK3528_CRU_RESET_OFFSET(SRST_A_HDCP, 410),
 RK3528_CRU_RESET_OFFSET(SRST_H_HDCP, 411),
 RK3528_CRU_RESET_OFFSET(SRST_P_HDCP, 412),
 RK3528_CRU_RESET_OFFSET(SRST_H_CVBS, 413),
 RK3528_CRU_RESET_OFFSET(SRST_D_CVBS_VOP, 414),
 RK3528_CRU_RESET_OFFSET(SRST_D_4X_CVBS_VOP, 415),
 RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 416),
 RK3528_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 417),
 RK3528_CRU_RESET_OFFSET(SRST_A_VO_L_BIU, 419),
 RK3528_CRU_RESET_OFFSET(SRST_A_MAC_VO, 4110),

 /* CRU_SOFTRST_CON42 */
 RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 420),
 RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S3, 421),
 RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S3, 422),
 RK3528_CRU_RESET_OFFSET(SRST_MACPHY, 423),
 RK3528_CRU_RESET_OFFSET(SRST_P_VCDCPHY, 424),
 RK3528_CRU_RESET_OFFSET(SRST_P_GPIO2, 425),
 RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO2, 426),
 RK3528_CRU_RESET_OFFSET(SRST_P_VO_IOC, 427),
 RK3528_CRU_RESET_OFFSET(SRST_H_SDMMC0, 429),
 RK3528_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 4211),
 RK3528_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 4212),
 RK3528_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 4213),

 /* CRU_SOFTRST_CON43 */
 RK3528_CRU_RESET_OFFSET(SRST_HDMIHDP0, 432),
 RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST, 433),
 RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST_ARB, 434),
 RK3528_CRU_RESET_OFFSET(SRST_HOST_UTMI, 436),
 RK3528_CRU_RESET_OFFSET(SRST_P_UART4, 437),
 RK3528_CRU_RESET_OFFSET(SRST_S_UART4, 438),
 RK3528_CRU_RESET_OFFSET(SRST_P_I2C4, 439),
 RK3528_CRU_RESET_OFFSET(SRST_I2C4, 4310),
 RK3528_CRU_RESET_OFFSET(SRST_P_I2C7, 4311),
 RK3528_CRU_RESET_OFFSET(SRST_I2C7, 4312),
 RK3528_CRU_RESET_OFFSET(SRST_P_USBPHY, 4313),
 RK3528_CRU_RESET_OFFSET(SRST_USBPHY_POR, 4314),
 RK3528_CRU_RESET_OFFSET(SRST_USBPHY_OTG, 4315),

 /* CRU_SOFTRST_CON44 */
 RK3528_CRU_RESET_OFFSET(SRST_USBPHY_HOST, 440),
 RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY_CRU, 444),
 RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 446),
 RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 447),
 RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC, 448),
 RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC, 449),
 RK3528_CRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 4411),
 RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_RKVDEC, 4412),

 /* CRU_SOFTRST_CON45 */
 RK3528_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 451),
 RK3528_CRU_RESET_OFFSET(SRST_P_DDRC, 452),
 RK3528_CRU_RESET_OFFSET(SRST_P_DDRMON, 453),
 RK3528_CRU_RESET_OFFSET(SRST_TIMER_DDRMON, 454),
 RK3528_CRU_RESET_OFFSET(SRST_P_MSCH_BIU, 455),
 RK3528_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 456),
 RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 458),
 RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 459),
 RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 4510),
 RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 4511),
 RK3528_CRU_RESET_OFFSET(SRST_DDR_UPCTL, 4512),
 RK3528_CRU_RESET_OFFSET(SRST_DDRMON, 4513),
 RK3528_CRU_RESET_OFFSET(SRST_A_DDR_SCRAMBLE, 4514),
 RK3528_CRU_RESET_OFFSET(SRST_A_SPLIT, 4515),

 /* CRU_SOFTRST_CON46 */
 RK3528_CRU_RESET_OFFSET(SRST_DDR_PHY, 460),
};

void rk3528_rst_init(struct device_node *np, void __iomem *reg_base)
{
 rockchip_register_softrst_lut(np,
          rk3528_register_offset,
          ARRAY_SIZE(rk3528_register_offset),
          reg_base + RK3528_SOFTRST_CON(0),
          ROCKCHIP_SOFTRST_HIWORD_MASK);
}

Messung V0.5 in Prozent
C=97 H=96 G=96

¤ Dauer der Verarbeitung: 0.11 Sekunden  (vorverarbeitet am  2026-06-07) ¤

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