// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2019 Rockchip Electronics Co. Ltd. * Author: Finley Xiao <finley.xiao@rock-chips.com> #include <linux/clk-provider.h>#include <linux/module.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/platform_device.h>#include <linux/syscore_ops.h>#include <dt-bindings/clock/rockchip,rv1126-cru.h>#include "clk.h" #define RV1126_GMAC_CON 0 x460#define RV1126_GRF_IOFUNC_CON1 0 x10264#define RV1126_GRF_SOC_STATUS0 0 x10#define RV1126_FRAC_MAX_PRATE 1200000000 #define RV1126_CSIOUT_FRAC_MAX_PRATE 300000000 enum rv1126_pmu_plls {enum rv1126_plls {static struct rockchip_pll_rate_table rv1126_pll_rates[] = {/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 1608000000 , 1 , 67 , 1 , 1 , 1 , 0 ),1600000000 , 3 , 200 , 1 , 1 , 1 , 0 ),1584000000 , 1 , 132 , 2 , 1 , 1 , 0 ),1560000000 , 1 , 130 , 2 , 1 , 1 , 0 ),1536000000 , 1 , 128 , 2 , 1 , 1 , 0 ),1512000000 , 1 , 126 , 2 , 1 , 1 , 0 ),1488000000 , 1 , 124 , 2 , 1 , 1 , 0 ),1464000000 , 1 , 122 , 2 , 1 , 1 , 0 ),1440000000 , 1 , 120 , 2 , 1 , 1 , 0 ),1416000000 , 1 , 118 , 2 , 1 , 1 , 0 ),1400000000 , 3 , 350 , 2 , 1 , 1 , 0 ),1392000000 , 1 , 116 , 2 , 1 , 1 , 0 ),1368000000 , 1 , 114 , 2 , 1 , 1 , 0 ),1344000000 , 1 , 112 , 2 , 1 , 1 , 0 ),1320000000 , 1 , 110 , 2 , 1 , 1 , 0 ),1296000000 , 1 , 108 , 2 , 1 , 1 , 0 ),1272000000 , 1 , 106 , 2 , 1 , 1 , 0 ),1248000000 , 1 , 104 , 2 , 1 , 1 , 0 ),1200000000 , 1 , 100 , 2 , 1 , 1 , 0 ),1188000000 , 1 , 99 , 2 , 1 , 1 , 0 ),1104000000 , 1 , 92 , 2 , 1 , 1 , 0 ),1100000000 , 3 , 275 , 2 , 1 , 1 , 0 ),1008000000 , 1 , 84 , 2 , 1 , 1 , 0 ),1000000000 , 3 , 250 , 2 , 1 , 1 , 0 ),984000000 , 1 , 82 , 2 , 1 , 1 , 0 ),960000000 , 1 , 80 , 2 , 1 , 1 , 0 ),936000000 , 1 , 78 , 2 , 1 , 1 , 0 ),912000000 , 1 , 76 , 2 , 1 , 1 , 0 ),900000000 , 1 , 75 , 2 , 1 , 1 , 0 ),888000000 , 1 , 74 , 2 , 1 , 1 , 0 ),864000000 , 1 , 72 , 2 , 1 , 1 , 0 ),840000000 , 1 , 70 , 2 , 1 , 1 , 0 ),816000000 , 1 , 68 , 2 , 1 , 1 , 0 ),800000000 , 3 , 200 , 2 , 1 , 1 , 0 ),700000000 , 3 , 350 , 4 , 1 , 1 , 0 ),696000000 , 1 , 116 , 4 , 1 , 1 , 0 ),624000000 , 1 , 104 , 4 , 1 , 1 , 0 ),600000000 , 1 , 100 , 4 , 1 , 1 , 0 ),594000000 , 1 , 99 , 4 , 1 , 1 , 0 ),504000000 , 1 , 84 , 4 , 1 , 1 , 0 ),500000000 , 1 , 125 , 6 , 1 , 1 , 0 ),408000000 , 1 , 68 , 2 , 2 , 1 , 0 ),312000000 , 1 , 78 , 6 , 1 , 1 , 0 ),216000000 , 1 , 72 , 4 , 2 , 1 , 0 ),96000000 , 1 , 96 , 6 , 4 , 1 , 0 ),/* sentinel */ }, #define RV1126_DIV_ACLK_CORE_MASK 0 xf#define RV1126_DIV_ACLK_CORE_SHIFT 4 #define RV1126_DIV_PCLK_DBG_MASK 0 x7#define RV1126_DIV_PCLK_DBG_SHIFT 0 #define RV1126_CLKSEL1(_aclk_core, _pclk_dbg) \1 ), \#define RV1126_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \static struct rockchip_cpuclk_rate_table rv1126_cpuclk_rates[] __initdata = {1608000000 , 1 , 7 ),1584000000 , 1 , 7 ),1560000000 , 1 , 7 ),1536000000 , 1 , 7 ),1512000000 , 1 , 7 ),1488000000 , 1 , 5 ),1464000000 , 1 , 5 ),1440000000 , 1 , 5 ),1416000000 , 1 , 5 ),1392000000 , 1 , 5 ),1368000000 , 1 , 5 ),1344000000 , 1 , 5 ),1320000000 , 1 , 5 ),1296000000 , 1 , 5 ),1272000000 , 1 , 5 ),1248000000 , 1 , 5 ),1224000000 , 1 , 5 ),1200000000 , 1 , 5 ),1104000000 , 1 , 5 ),1008000000 , 1 , 5 ),912000000 , 1 , 5 ),816000000 , 1 , 3 ),696000000 , 1 , 3 ),600000000 , 1 , 3 ),408000000 , 1 , 1 ),312000000 , 1 , 1 ),216000000 , 1 , 1 ),96000000 , 1 , 1 ),static const struct rockchip_cpuclk_reg_data rv1126_cpuclk_data = {0 ] = RV1126_CLKSEL_CON(0 ),0 ] = 0 ,0 ] = 0 x1f,1 ,0 ,2 ,6 ,0 x3,"xin24m" };"clk_pmupvtm_divout" , "xin32k" , "clk_osc0_div32k" };"clk_wifi_osc0" , "clk_wifi_div" };"gpll" , "usb480m" , "cpll" , "xin24m" };"sclk_uart1_div" , "sclk_uart1_fracdiv" , "xin24m" };"xin24m" , "gpll" };"gpll" , "xin24m" };"xin24m" , "clk_rtc32k" };"clk_ref12m" , "xin_osc0_div2_usbphyref_otg" };"clk_ref12m" , "xin_osc0_div2_usbphyref_host" };"clk_ref24m" , "xin_osc0_mipiphyref" };"xin24m" , "usb480m_phy" , "clk_rtc32k" };"gpll" , "cpll" , "apll" };"gpll" , "cpll" , "dummy_dpll" };"gpll" , "cpll" };"gpll" , "dummy_cpll" };"gpll" , "cpll" , "usb480m" , "xin24m" };"sclk_uart0_div" , "sclk_uart0_frac" , "xin24m" };"sclk_uart2_div" , "sclk_uart2_frac" , "xin24m" };"sclk_uart3_div" , "sclk_uart3_frac" , "xin24m" };"sclk_uart4_div" , "sclk_uart4_frac" , "xin24m" };"sclk_uart5_div" , "sclk_uart5_frac" , "xin24m" };"cpll" , "gpll" };"mclk_i2s0_tx_div" , "mclk_i2s0_tx_fracdiv" , "i2s0_mclkin" , "xin12m" };"mclk_i2s0_rx_div" , "mclk_i2s0_rx_fracdiv" , "i2s0_mclkin" , "xin12m" };"mclk_i2s0_tx" , "xin12m" };"mclk_i2s0_rx" , "xin12m" };"mclk_i2s1_div" , "mclk_i2s1_fracdiv" , "i2s1_mclkin" , "xin12m" };"mclk_i2s1" , "xin12m" };"mclk_i2s2_div" , "mclk_i2s2_fracdiv" , "i2s2_mclkin" , "xin12m" };"mclk_i2s2" , "xin12m" };"gpll" , "cpll" , "xin24m" };"sclk_audpwm_div" , "sclk_audpwm_fracdiv" , "xin24m" };"dclk_vop_div" , "dclk_vop_fracdiv" , "xin24m" };"usb480m" , "gpll" };"clk_gmac_div" , "clk_gmac_rgmii_m0" };"clk_gmac_div" , "clk_gmac_rgmii_m1" };"clk_gmac_src_m0" , "clk_gmac_src_m1" };"clk_gmac_tx_div50" , "clk_gmac_tx_div5" , "clk_gmac_tx_src" , "clk_gmac_tx_src" };"clk_gmac_rx_div20" , "clk_gmac_rx_div2" };"rgmii_mode_clk" , "rmii_mode_clk" };"dpll" , "gpll" };static u32 rgmii_mux_idx[] = { 2 , 3 , 0 , 1 };static struct rockchip_pll_clock rv1126_pmu_pll_clks[] __initdata = {"gpll" , mux_pll_p,0 , RV1126_PMU_PLL_CON(0 ),0 , 3 , 0 , rv1126_pll_rates),static struct rockchip_pll_clock rv1126_pll_clks[] __initdata = {"apll" , mux_pll_p,0 , RV1126_PLL_CON(0 ),0 , 0 , 0 , rv1126_pll_rates),"dpll" , mux_pll_p,0 , RV1126_PLL_CON(8 ),2 , 1 , 0 , NULL),"cpll" , mux_pll_p,0 , RV1126_PLL_CON(16 ),4 , 2 , 0 , rv1126_pll_rates),"hpll" , mux_pll_p,0 , RV1126_PLL_CON(24 ),6 , 4 , 0 , rv1126_pll_rates),#define MFLAGS CLK_MUX_HIWORD_MASK#define DFLAGS CLK_DIVIDER_HIWORD_MASK#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)static struct rockchip_clk_branch rv1126_rtc32k_fracmux __initdata ="clk_rtc32k" , mux_rtc32k_p, CLK_SET_RATE_PARENT,0 ), 7 , 2 , MFLAGS);static struct rockchip_clk_branch rv1126_uart1_fracmux __initdata ="sclk_uart1_mux" , mux_uart1_p, CLK_SET_RATE_PARENT,4 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch rv1126_uart0_fracmux __initdata ="sclk_uart0_mux" , mux_uart0_p, CLK_SET_RATE_PARENT,10 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch rv1126_uart2_fracmux __initdata ="sclk_uart2_mux" , mux_uart2_p, CLK_SET_RATE_PARENT,12 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch rv1126_uart3_fracmux __initdata ="sclk_uart3_mux" , mux_uart3_p, CLK_SET_RATE_PARENT,14 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch rv1126_uart4_fracmux __initdata ="sclk_uart4_mux" , mux_uart4_p, CLK_SET_RATE_PARENT,16 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch rv1126_uart5_fracmux __initdata ="sclk_uart5_mux" , mux_uart5_p, CLK_SET_RATE_PARENT,18 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch rv1126_i2s0_tx_fracmux __initdata ="mclk_i2s0_tx_mux" , mux_i2s0_tx_p, CLK_SET_RATE_PARENT,30 ), 0 , 2 , MFLAGS);static struct rockchip_clk_branch rv1126_i2s0_rx_fracmux __initdata ="mclk_i2s0_rx_mux" , mux_i2s0_rx_p, CLK_SET_RATE_PARENT,30 ), 2 , 2 , MFLAGS);static struct rockchip_clk_branch rv1126_i2s1_fracmux __initdata ="mclk_i2s1_mux" , mux_i2s1_p, CLK_SET_RATE_PARENT,31 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rv1126_i2s2_fracmux __initdata ="mclk_i2s2_mux" , mux_i2s2_p, CLK_SET_RATE_PARENT,33 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rv1126_audpwm_fracmux __initdata ="mclk_audpwm_mux" , mux_audpwm_p, CLK_SET_RATE_PARENT,36 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rv1126_dclk_vop_fracmux __initdata ="dclk_vop_mux" , mux_dclk_vop_p, CLK_SET_RATE_PARENT,47 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {/* * Clock-Architecture Diagram 2 /* PD_PMU */ "pclk_pdpmu" , "gpll" , CLK_IGNORE_UNUSED,1 ), 0 , 5 , DFLAGS,0 ), 0 , GFLAGS),"clk_osc0_div32k" , "xin24m" , CLK_IGNORE_UNUSED,13 ), 0 ,2 ), 9 , GFLAGS,"clk_wifi_div" , "gpll" , 0 ,12 ), 0 , 6 , DFLAGS,2 ), 10 , GFLAGS),"clk_wifi_osc0" , "xin24m" , 0 ,2 ), 11 , GFLAGS),"clk_wifi" , mux_wifi_p, CLK_SET_RATE_PARENT,12 ), 8 , 1 , MFLAGS),"pclk_pmu" , "pclk_pdpmu" , CLK_IGNORE_UNUSED,0 ), 1 , GFLAGS),"pclk_uart1" , "pclk_pdpmu" , 0 ,0 ), 11 , GFLAGS),"sclk_uart1_div" , mux_gpll_usb480m_cpll_xin24m_p, 0 ,4 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,0 ), 12 , GFLAGS),"sclk_uart1_fracdiv" , "sclk_uart1_div" ,5 ), 0 ,0 ), 13 , GFLAGS,"sclk_uart1" , "sclk_uart1_mux" , 0 ,0 ), 14 , GFLAGS),"pclk_i2c0" , "pclk_pdpmu" , 0 ,0 ), 5 , GFLAGS),"clk_i2c0" , "gpll" , 0 ,2 ), 0 , 7 , DFLAGS,0 ), 6 , GFLAGS),"pclk_i2c2" , "pclk_pdpmu" , 0 ,0 ), 9 , GFLAGS),"clk_i2c2" , "gpll" , 0 ,3 ), 0 , 7 , DFLAGS,0 ), 10 , GFLAGS),"clk_capture_pwm0" , "xin24m" , 0 ,1 ), 2 , GFLAGS),"pclk_pwm0" , "pclk_pdpmu" , 0 ,1 ), 0 , GFLAGS),"clk_pwm0" , mux_xin24m_gpll_p, 0 ,6 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,1 ), 1 , GFLAGS),"clk_capture_pwm1" , "xin24m" , 0 ,1 ), 5 , GFLAGS),"pclk_pwm1" , "pclk_pdpmu" , 0 ,1 ), 3 , GFLAGS),"clk_pwm1" , mux_xin24m_gpll_p, 0 ,6 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,1 ), 4 , GFLAGS),"pclk_spi0" , "pclk_pdpmu" , 0 ,1 ), 11 , GFLAGS),"clk_spi0" , mux_gpll_xin24m_p, 0 ,9 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,1 ), 12 , GFLAGS),"pclk_gpio0" , "pclk_pdpmu" , 0 ,1 ), 9 , GFLAGS),"dbclk_gpio0" , mux_xin24m_32k_p, 0 ,8 ), 15 , 1 , MFLAGS,1 ), 10 , GFLAGS),"pclk_pmupvtm" , "pclk_pdpmu" , 0 ,2 ), 6 , GFLAGS),"clk_pmupvtm" , "xin24m" , 0 ,2 ), 5 , GFLAGS),"clk_core_pmupvtm" , "xin24m" , 0 ,2 ), 7 , GFLAGS),"clk_ref12m" , "gpll" , 0 ,7 ), 8 , 7 , DFLAGS,1 ), 15 , GFLAGS),0 , "xin_osc0_usbphyref_otg" , "xin24m" , 0 ,1 ), 6 , GFLAGS),0 , "xin_osc0_usbphyref_host" , "xin24m" , 0 ,1 ), 7 , GFLAGS),0 , "xin_osc0_div2_usbphyref_otg" , "xin_osc0_usbphyref_otg" , 0 , 1 , 2 ),0 , "xin_osc0_div2_usbphyref_host" , "xin_osc0_usbphyref_host" , 0 , 1 , 2 ),"clk_usbphy_otg_ref" , mux_usbphy_otg_ref_p, CLK_SET_RATE_PARENT,7 ), 6 , 1 , MFLAGS),"clk_usbphy_host_ref" , mux_usbphy_host_ref_p, CLK_SET_RATE_PARENT,7 ), 7 , 1 , MFLAGS),"clk_ref24m" , "gpll" , 0 ,7 ), 0 , 6 , DFLAGS,1 ), 14 , GFLAGS),0 , "xin_osc0_mipiphyref" , "xin24m" , 0 ,1 ), 8 , GFLAGS),"clk_mipidsiphy_ref" , mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,7 ), 15 , 1 , MFLAGS),"clk_pmu" , "xin24m" , CLK_IGNORE_UNUSED,0 ), 15 , GFLAGS),"pclk_pmusgrf" , "pclk_pdpmu" , CLK_IGNORE_UNUSED,0 ), 4 , GFLAGS),"pclk_pmugrf" , "pclk_pdpmu" , CLK_IGNORE_UNUSED,1 ), 13 , GFLAGS),"pclk_pmucru" , "pclk_pdpmu" , CLK_IGNORE_UNUSED,2 ), 4 , GFLAGS),"pclk_chipverotp" , "pclk_pdpmu" , CLK_IGNORE_UNUSED,2 ), 0 , GFLAGS),"pclk_pdpmu_niu" , "pclk_pdpmu" , CLK_IGNORE_UNUSED,0 ), 2 , GFLAGS),"pclk_scrkeygen" , "pclk_pdpmu" , 0 ,0 ), 7 , GFLAGS),static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {/* * Clock-Architecture Diagram 1 "usb480m" , mux_usb480m_p, CLK_SET_RATE_PARENT,10 , 2 , MFLAGS),0 , "xin12m" , "xin24m" , 0 , 1 , 2 ),/* * Clock-Architecture Diagram 3 /* PD_CORE */ 0 , "pclk_dbg" , "armclk" , CLK_IGNORE_UNUSED,1 ), 0 , 3 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 6 , GFLAGS),"clk_core_cpupvtm" , "armclk" , 0 ,0 ), 12 , GFLAGS),"pclk_cpupvtm" , "pclk_dbg" , 0 ,0 ), 10 , GFLAGS),"clk_cpupvtm" , "xin24m" , 0 ,0 ), 11 , GFLAGS),"hclk_pdcore_niu" , "gpll" , CLK_IGNORE_UNUSED,0 ), 8 , 5 , DFLAGS,0 ), 8 , GFLAGS),/* * Clock-Architecture Diagram 4 /* PD_BUS */ 0 , "aclk_pdbus_pre" , mux_gpll_cpll_dpll_p, CLK_IGNORE_UNUSED,2 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,2 ), 0 , GFLAGS),"aclk_pdbus" , "aclk_pdbus_pre" , CLK_IGNORE_UNUSED,2 ), 11 , GFLAGS),0 , "hclk_pdbus_pre" , mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,2 ), 15 , 1 , MFLAGS, 8 , 5 , DFLAGS,2 ), 1 , GFLAGS),"hclk_pdbus" , "hclk_pdbus_pre" , CLK_IGNORE_UNUSED,2 ), 12 , GFLAGS),0 , "pclk_pdbus_pre" , mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,3 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS,2 ), 2 , GFLAGS),"pclk_pdbus" , "pclk_pdbus_pre" , CLK_IGNORE_UNUSED,2 ), 13 , GFLAGS),/* aclk_dmac is controlled by sgrf_clkgat_con. */ "aclk_dmac" , "hclk_pdbus" ),"aclk_dcf" , "hclk_pdbus" , CLK_IGNORE_UNUSED,3 ), 6 , GFLAGS),"pclk_dcf" , "pclk_pdbus" , CLK_IGNORE_UNUSED,3 ), 7 , GFLAGS),"pclk_wdt" , "pclk_pdbus" , 0 ,6 ), 14 , GFLAGS),"pclk_mailbox" , "pclk_pdbus" , 0 ,7 ), 10 , GFLAGS),"clk_scr1" , mux_gpll_cpll_p, 0 ,3 ), 15 , 1 , MFLAGS, 8 , 5 , DFLAGS,4 ), 7 , GFLAGS),0 , "clk_scr1_niu" , "clk_scr1" , CLK_IGNORE_UNUSED,2 ), 14 , GFLAGS),"clk_scr1_core" , "clk_scr1" , 0 ,4 ), 8 , GFLAGS),"clk_scr1_rtc" , "xin24m" , 0 ,4 ), 9 , GFLAGS),"clk_scr1_jtag" , "clk_scr1_jtag_io" , 0 ,4 ), 10 , GFLAGS),"pclk_uart0" , "pclk_pdbus" , 0 ,5 ), 0 , GFLAGS),"sclk_uart0_div" , mux_gpll_cpll_usb480m_xin24m_p, 0 ,10 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,5 ), 1 , GFLAGS),"sclk_uart0_frac" , "sclk_uart0_div" , CLK_SET_RATE_PARENT,11 ), 0 ,5 ), 2 , GFLAGS,"sclk_uart0" , "sclk_uart0_mux" , 0 ,5 ), 3 , GFLAGS),"pclk_uart2" , "pclk_pdbus" , 0 ,5 ), 4 , GFLAGS),"sclk_uart2_div" , mux_gpll_cpll_usb480m_xin24m_p, 0 ,12 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,5 ), 5 , GFLAGS),"sclk_uart2_frac" , "sclk_uart2_div" , CLK_SET_RATE_PARENT,13 ), 0 ,5 ), 6 , GFLAGS,"sclk_uart2" , "sclk_uart2_mux" , 0 ,5 ), 7 , GFLAGS),"pclk_uart3" , "pclk_pdbus" , 0 ,5 ), 8 , GFLAGS),"sclk_uart3_div" , mux_gpll_cpll_usb480m_xin24m_p, 0 ,14 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,5 ), 9 , GFLAGS),"sclk_uart3_frac" , "sclk_uart3_div" , CLK_SET_RATE_PARENT,15 ), 0 ,5 ), 10 , GFLAGS,"sclk_uart3" , "sclk_uart3_mux" , 0 ,5 ), 11 , GFLAGS),"pclk_uart4" , "pclk_pdbus" , 0 ,5 ), 12 , GFLAGS),"sclk_uart4_div" , mux_gpll_cpll_usb480m_xin24m_p, 0 ,16 ), 8 , 2 , MFLAGS, 0 , 7 ,5 ), 13 , GFLAGS),"sclk_uart4_frac" , "sclk_uart4_div" , CLK_SET_RATE_PARENT,17 ), 0 ,5 ), 14 , GFLAGS,"sclk_uart4" , "sclk_uart4_mux" , 0 ,5 ), 15 , GFLAGS),"pclk_uart5" , "pclk_pdbus" , 0 ,6 ), 0 , GFLAGS),"sclk_uart5_div" , mux_gpll_cpll_usb480m_xin24m_p, 0 ,18 ), 8 , 2 , MFLAGS, 0 , 7 ,6 ), 1 , GFLAGS),"sclk_uart5_frac" , "sclk_uart5_div" , CLK_SET_RATE_PARENT,19 ), 0 ,6 ), 2 , GFLAGS,"sclk_uart5" , "sclk_uart5_mux" , 0 ,6 ), 3 , GFLAGS),"pclk_i2c1" , "pclk_pdbus" , 0 ,3 ), 10 , GFLAGS),"clk_i2c1" , "gpll" , 0 ,5 ), 0 , 7 , DFLAGS,3 ), 11 , GFLAGS),"pclk_i2c3" , "pclk_pdbus" , 0 ,3 ), 12 , GFLAGS),"clk_i2c3" , "gpll" , 0 ,5 ), 8 , 7 , DFLAGS,3 ), 13 , GFLAGS),"pclk_i2c4" , "pclk_pdbus" , 0 ,3 ), 14 , GFLAGS),"clk_i2c4" , "gpll" , 0 ,6 ), 0 , 7 , DFLAGS,3 ), 15 , GFLAGS),"pclk_i2c5" , "pclk_pdbus" , 0 ,4 ), 0 , GFLAGS),"clk_i2c5" , "gpll" , 0 ,6 ), 8 , 7 , DFLAGS,4 ), 1 , GFLAGS),"pclk_spi1" , "pclk_pdbus" , 0 ,4 ), 2 , GFLAGS),"clk_spi1" , mux_gpll_xin24m_p, 0 ,8 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,4 ), 3 , GFLAGS),"clk_capture_pwm2" , "xin24m" , 0 ,4 ), 6 , GFLAGS),"pclk_pwm2" , "pclk_pdbus" , 0 ,4 ), 4 , GFLAGS),"clk_pwm2" , mux_xin24m_gpll_p, 0 ,9 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,4 ), 5 , GFLAGS),"pclk_gpio1" , "pclk_pdbus" , 0 ,7 ), 0 , GFLAGS),"dbclk_gpio1" , mux_xin24m_32k_p, 0 ,21 ), 15 , 1 , MFLAGS,7 ), 1 , GFLAGS),"pclk_gpio2" , "pclk_pdbus" , 0 ,7 ), 2 , GFLAGS),"dbclk_gpio2" , mux_xin24m_32k_p, 0 ,22 ), 15 , 1 , MFLAGS,7 ), 3 , GFLAGS),"pclk_gpio3" , "pclk_pdbus" , 0 ,7 ), 4 , GFLAGS),"dbclk_gpio3" , mux_xin24m_32k_p, 0 ,23 ), 15 , 1 , MFLAGS,7 ), 5 , GFLAGS),"pclk_gpio4" , "pclk_pdbus" , 0 ,7 ), 6 , GFLAGS),"dbclk_gpio4" , mux_xin24m_32k_p, 0 ,24 ), 15 , 1 , MFLAGS,7 ), 7 , GFLAGS),"pclk_saradc" , "pclk_pdbus" , 0 ,6 ), 4 , GFLAGS),"clk_saradc" , "xin24m" , 0 ,20 ), 0 , 11 , DFLAGS,6 ), 5 , GFLAGS),"pclk_timer" , "pclk_pdbus" , 0 ,6 ), 7 , GFLAGS),"clk_timer0" , "xin24m" , 0 ,6 ), 8 , GFLAGS),"clk_timer1" , "xin24m" , 0 ,6 ), 9 , GFLAGS),"clk_timer2" , "xin24m" , 0 ,6 ), 10 , GFLAGS),"clk_timer3" , "xin24m" , 0 ,6 ), 11 , GFLAGS),"clk_timer4" , "xin24m" , 0 ,6 ), 12 , GFLAGS),"clk_timer5" , "xin24m" , 0 ,6 ), 13 , GFLAGS),"aclk_spinlock" , "hclk_pdbus" , 0 ,6 ), 6 , GFLAGS),"aclk_decom" , "aclk_pdbus" , 0 ,7 ), 11 , GFLAGS),"pclk_decom" , "pclk_pdbus" , 0 ,7 ), 12 , GFLAGS),"dclk_decom" , mux_gpll_cpll_p, 0 ,25 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,7 ), 13 , GFLAGS),"pclk_can" , "pclk_pdbus" , 0 ,7 ), 8 , GFLAGS),"clk_can" , mux_gpll_xin24m_p, 0 ,25 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,7 ), 9 , GFLAGS),/* pclk_otp and clk_otp are controlled by sgrf_clkgat_con. */ "clk_otp" , "xin24m" ),"pclk_otp" , "pclk_pdbus" ),"pclk_npu_tsadc" , "pclk_pdbus" , 0 ,24 ), 3 , GFLAGS),"clk_npu_tsadc" , "xin24m" , 0 ,71 ), 0 , 11 , DFLAGS,24 ), 4 , GFLAGS),"clk_npu_tsadcphy" , "clk_npu_tsadc" , 0 ,24 ), 5 , GFLAGS),"pclk_cpu_tsadc" , "pclk_pdbus" , 0 ,24 ), 0 , GFLAGS),"clk_cpu_tsadc" , "xin24m" , 0 ,70 ), 0 , 11 , DFLAGS,24 ), 1 , GFLAGS),"clk_cpu_tsadcphy" , "clk_cpu_tsadc" , 0 ,24 ), 2 , GFLAGS),/* * Clock-Architecture Diagram 6 /* PD_AUDIO */ "hclk_pdaudio" , "gpll" , 0 ,26 ), 0 , 5 , DFLAGS,9 ), 0 , GFLAGS),"hclk_i2s0" , "hclk_pdaudio" , 0 ,9 ), 4 , GFLAGS),"mclk_i2s0_tx_div" , mux_cpll_gpll_p, 0 ,27 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,9 ), 5 , GFLAGS),"mclk_i2s0_tx_fracdiv" , "mclk_i2s0_tx_div" ,28 ), 0 ,9 ), 6 , GFLAGS,"mclk_i2s0_tx" , "mclk_i2s0_tx_mux" , 0 ,9 ), 9 , GFLAGS),"mclk_i2s0_rx_div" , mux_cpll_gpll_p, 0 ,27 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,9 ), 7 , GFLAGS),"mclk_i2s0_rx_fracdiv" , "mclk_i2s0_rx_div" ,29 ), 0 ,9 ), 8 , GFLAGS,"mclk_i2s0_rx" , "mclk_i2s0_rx_mux" , 0 ,9 ), 10 , GFLAGS),"mclk_i2s0_tx_out2io" , mux_i2s0_tx_out2io_p, 0 ,30 ), 6 , 1 , MFLAGS,9 ), 13 , GFLAGS),"mclk_i2s0_rx_out2io" , mux_i2s0_rx_out2io_p, 0 ,30 ), 8 , 1 , MFLAGS,9 ), 14 , GFLAGS),"hclk_i2s1" , "hclk_pdaudio" , 0 ,10 ), 0 , GFLAGS),"mclk_i2s1_div" , mux_cpll_gpll_p, 0 ,31 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,10 ), 1 , GFLAGS),"mclk_i2s1_fracdiv" , "mclk_i2s1_div" ,32 ), 0 ,10 ), 2 , GFLAGS,"mclk_i2s1" , "mclk_i2s1_mux" , 0 ,10 ), 3 , GFLAGS),"mclk_i2s1_out2io" , mux_i2s1_out2io_p, 0 ,31 ), 12 , 1 , MFLAGS,10 ), 4 , GFLAGS),"hclk_i2s2" , "hclk_pdaudio" , 0 ,10 ), 5 , GFLAGS),"mclk_i2s2_div" , mux_cpll_gpll_p, 0 ,33 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,10 ), 6 , GFLAGS),"mclk_i2s2_fracdiv" , "mclk_i2s2_div" ,34 ), 0 ,10 ), 7 , GFLAGS,"mclk_i2s2" , "mclk_i2s2_mux" , 0 ,10 ), 8 , GFLAGS),"mclk_i2s2_out2io" , mux_i2s2_out2io_p, 0 ,33 ), 10 , 1 , MFLAGS,10 ), 9 , GFLAGS),"hclk_pdm" , "hclk_pdaudio" , 0 ,10 ), 10 , GFLAGS),"mclk_pdm" , mux_gpll_cpll_xin24m_p, 0 ,35 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,10 ), 11 , GFLAGS),"hclk_audpwm" , "hclk_pdaudio" , 0 ,10 ), 12 , GFLAGS),"sclk_audpwm_div" , mux_gpll_cpll_p, 0 ,36 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,10 ), 13 , GFLAGS),"sclk_audpwm_fracdiv" , "sclk_audpwm_div" ,37 ), 0 ,10 ), 14 , GFLAGS,"sclk_audpwm" , "mclk_audpwm_mux" , 0 ,10 ), 15 , GFLAGS),"pclk_acdcdig" , "hclk_pdaudio" , 0 ,11 ), 0 , GFLAGS),"clk_acdcdig_adc" , "mclk_i2s0_rx" , 0 ,11 ), 2 , GFLAGS),"clk_acdcdig_dac" , "mclk_i2s0_tx" , 0 ,11 ), 3 , GFLAGS),"clk_acdcdig_i2c" , mux_gpll_xin24m_p, 0 ,72 ), 8 , 1 , MFLAGS, 0 , 7 , DFLAGS,11 ), 1 , GFLAGS),/* * Clock-Architecture Diagram 9 /* PD_VO */ "aclk_pdvo" , mux_gpll_cpll_p, 0 ,45 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS,14 ), 0 , GFLAGS),"hclk_pdvo" , "aclk_pdvo" , 0 ,45 ), 8 , 5 , DFLAGS,14 ), 1 , GFLAGS),"pclk_pdvo" , "aclk_pdvo" , 0 ,46 ), 8 , 5 , DFLAGS,14 ), 2 , GFLAGS),"aclk_rga" , "aclk_pdvo" , 0 ,14 ), 6 , GFLAGS),"hclk_rga" , "hclk_pdvo" , 0 ,14 ), 7 , GFLAGS),"clk_rga_core" , mux_gpll_cpll_p, 0 ,46 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS,14 ), 8 , GFLAGS),"aclk_vop" , "aclk_pdvo" , 0 ,14 ), 9 , GFLAGS),"hclk_vop" , "hclk_pdvo" , 0 ,14 ), 10 , GFLAGS),"dclk_vop_div" , mux_gpll_cpll_p, 0 ,47 ), 8 , 1 , MFLAGS, 0 , 8 , DFLAGS,14 ), 11 , GFLAGS),"dclk_vop_fracdiv" , "dclk_vop_div" ,48 ), 0 ,14 ), 12 , GFLAGS,"dclk_vop" , "dclk_vop_mux" , 0 ,14 ), 13 , GFLAGS),"pclk_dsihost" , "pclk_pdvo" , 0 ,14 ), 14 , GFLAGS),"aclk_iep" , "aclk_pdvo" , 0 ,12 ), 7 , GFLAGS),"hclk_iep" , "hclk_pdvo" , 0 ,12 ), 8 , GFLAGS),"clk_iep_core" , mux_gpll_cpll_p, 0 ,54 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS,12 ), 9 , GFLAGS),/* * Clock-Architecture Diagram 12 /* PD_PHP */ "aclk_pdphp" , mux_gpll_cpll_p, CLK_IGNORE_UNUSED,53 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS,17 ), 0 , GFLAGS),"hclk_pdphp" , "gpll" , CLK_IGNORE_UNUSED,53 ), 8 , 5 , DFLAGS,17 ), 1 , GFLAGS),/* PD_SDCARD */ "hclk_pdsdmmc" , "hclk_pdphp" , 0 ,17 ), 6 , GFLAGS),"hclk_sdmmc" , "hclk_pdsdmmc" , 0 ,18 ), 4 , GFLAGS),"clk_sdmmc" , mux_gpll_cpll_xin24m_p, 0 ,55 ), 14 , 2 , MFLAGS, 0 , 8 ,18 ), 5 , GFLAGS),"sdmmc_drv" , "clk_sdmmc" , RV1126_SDMMC_CON0, 1 ),"sdmmc_sample" , "clk_sdmmc" , RV1126_SDMMC_CON1, 1 ),/* PD_SDIO */ "hclk_pdsdio" , "hclk_pdphp" , 0 ,17 ), 8 , GFLAGS),"hclk_sdio" , "hclk_pdsdio" , 0 ,18 ), 6 , GFLAGS),"clk_sdio" , mux_gpll_cpll_xin24m_p, 0 ,56 ), 14 , 2 , MFLAGS, 0 , 8 , DFLAGS,18 ), 7 , GFLAGS),"sdio_drv" , "clk_sdio" , RV1126_SDIO_CON0, 1 ),"sdio_sample" , "clk_sdio" , RV1126_SDIO_CON1, 1 ),/* PD_NVM */ "hclk_pdnvm" , "hclk_pdphp" , 0 ,18 ), 1 , GFLAGS),"hclk_emmc" , "hclk_pdnvm" , 0 ,18 ), 8 , GFLAGS),"clk_emmc" , mux_gpll_cpll_xin24m_p, 0 ,57 ), 14 , 2 , MFLAGS, 0 , 8 , DFLAGS,18 ), 9 , GFLAGS),"hclk_nandc" , "hclk_pdnvm" , 0 ,18 ), 13 , GFLAGS),"clk_nandc" , mux_gpll_cpll_p, 0 ,59 ), 15 , 1 , MFLAGS, 0 , 8 , DFLAGS,18 ), 14 , GFLAGS),"hclk_sfc" , "hclk_pdnvm" , 0 ,18 ), 10 , GFLAGS),"hclk_sfcxip" , "hclk_pdnvm" , 0 ,18 ), 11 , GFLAGS),"sclk_sfc" , mux_cpll_gpll_p, 0 ,58 ), 15 , 1 , MFLAGS, 0 , 8 , DFLAGS,18 ), 12 , GFLAGS),"emmc_drv" , "clk_emmc" , RV1126_EMMC_CON0, 1 ),"emmc_sample" , "clk_emmc" , RV1126_EMMC_CON1, 1 ),/* PD_USB */ "aclk_pdusb" , "aclk_pdphp" , 0 ,19 ), 0 , GFLAGS),"hclk_pdusb" , "hclk_pdphp" , 0 ,19 ), 1 , GFLAGS),"hclk_usbhost" , "hclk_pdusb" , 0 ,19 ), 4 , GFLAGS),"hclk_usbhost_arb" , "hclk_pdusb" , 0 ,19 ), 5 , GFLAGS),"clk_usbhost_utmi_ohci" , mux_usb480m_gpll_p, 0 ,61 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS,19 ), 6 , GFLAGS),"aclk_usbotg" , "aclk_pdusb" , 0 ,19 ), 7 , GFLAGS),"clk_usbotg_ref" , "xin24m" , 0 ,19 ), 8 , GFLAGS),/* PD_GMAC */ "aclk_pdgmac" , "aclk_pdphp" , 0 ,20 ), 0 , GFLAGS),"pclk_pdgmac" , "aclk_pdgmac" , 0 ,63 ), 8 , 5 , DFLAGS,20 ), 1 , GFLAGS),"aclk_gmac" , "aclk_pdgmac" , 0 ,20 ), 4 , GFLAGS),"pclk_gmac" , "pclk_pdgmac" , 0 ,20 ), 5 , GFLAGS),"clk_gmac_div" , mux_cpll_gpll_p, 0 ,63 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS,20 ), 6 , GFLAGS),"clk_gmac_rgmii_m0" , "clk_gmac_rgmii_clkin_m0" , 0 ,20 ), 12 , GFLAGS),"clk_gmac_src_m0" , clk_gmac_src_m0_p, CLK_SET_RATE_PARENT,0 , 1 , MFLAGS),"clk_gmac_rgmii_m1" , "clk_gmac_rgmii_clkin_m1" , 0 ,20 ), 13 , GFLAGS),"clk_gmac_src_m1" , clk_gmac_src_m1_p, CLK_SET_RATE_PARENT,5 , 1 , MFLAGS),"clk_gmac_src" , mux_clk_gmac_src_p, CLK_SET_RATE_PARENT |12 , 1 , MFLAGS, grf_type_sys),"clk_gmac_ref" , "clk_gmac_src" , 0 ,20 ), 7 , GFLAGS),"clk_gmac_tx_src" , "clk_gmac_src" , 0 ,20 ), 9 , GFLAGS),"clk_gmac_tx_div5" , "clk_gmac_tx_src" , 0 , 1 , 5 ),"clk_gmac_tx_div50" , "clk_gmac_tx_src" , 0 , 1 , 50 ),"rgmii_mode_clk" , mux_rgmii_clk_p, CLK_SET_RATE_PARENT,2 , 2 , MFLAGS, rgmii_mux_idx),"clk_gmac_rx_src" , "clk_gmac_src" , 0 ,20 ), 8 , GFLAGS),"clk_gmac_rx_div2" , "clk_gmac_rx_src" , 0 , 1 , 2 ),"clk_gmac_rx_div20" , "clk_gmac_rx_src" , 0 , 1 , 20 ),"rmii_mode_clk" , mux_rmii_clk_p, CLK_SET_RATE_PARENT,1 , 1 , MFLAGS),"clk_gmac_tx_rx" , mux_gmac_tx_rx_p, CLK_SET_RATE_PARENT |4 , 1 , MFLAGS),"clk_gmac_ptpref" , "xin24m" , 0 ,20 ), 10 , GFLAGS),"clk_gmac_ethernet_out2io" , mux_cpll_gpll_p, 0 ,61 ), 15 , 1 , MFLAGS, 8 , 5 , DFLAGS,20 ), 11 , GFLAGS),/* * Clock-Architecture Diagram 15 "pclk_pdtop" , "pclk_pdbus" , CLK_IGNORE_UNUSED,23 ), 8 , GFLAGS),"pclk_dsiphy" , "pclk_pdtop" , 0 ,23 ), 4 , GFLAGS),"pclk_csiphy0" , "pclk_pdtop" , 0 ,23 ), 2 , GFLAGS),"pclk_csiphy1" , "pclk_pdtop" , 0 ,23 ), 3 , GFLAGS),"pclk_usbphy_host" , "pclk_pdtop" , 0 ,19 ), 13 , GFLAGS),"pclk_usbphy_otg" , "pclk_pdtop" , 0 ,19 ), 12 , GFLAGS),/* * Clock-Architecture Diagram 3 /* PD_CORE */ 0 , "aclk_core" , "armclk" , CLK_IGNORE_UNUSED,1 ), 4 , 4 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 2 , GFLAGS),0 , "pclk_dbg_daplite" , "pclk_dbg" , CLK_IGNORE_UNUSED,0 ), 5 , GFLAGS),0 , "clk_a7_jtag" , "clk_jtag_ori" , CLK_IGNORE_UNUSED,0 ), 9 , GFLAGS),0 , "aclk_core_niu" , "aclk_core" , CLK_IGNORE_UNUSED,0 ), 3 , GFLAGS),0 , "pclk_dbg_niu" , "pclk_dbg" , CLK_IGNORE_UNUSED,0 ), 4 , GFLAGS),/* * Clock-Architecture Diagram 4 /* PD_BUS */ 0 , "aclk_pdbus_hold_niu1" , "aclk_pdbus" , CLK_IGNORE_UNUSED,2 ), 10 , GFLAGS),0 , "aclk_pdbus_niu1" , "aclk_pdbus" , CLK_IGNORE_UNUSED,2 ), 3 , GFLAGS),0 , "hclk_pdbus_niu1" , "hclk_pdbus" , CLK_IGNORE_UNUSED,2 ), 4 , GFLAGS),0 , "pclk_pdbus_niu1" , "pclk_pdbus" , CLK_IGNORE_UNUSED,2 ), 5 , GFLAGS),0 , "aclk_pdbus_niu2" , "aclk_pdbus" , CLK_IGNORE_UNUSED,2 ), 6 , GFLAGS),0 , "hclk_pdbus_niu2" , "hclk_pdbus" , CLK_IGNORE_UNUSED,2 ), 7 , GFLAGS),0 , "aclk_pdbus_niu3" , "aclk_pdbus" , CLK_IGNORE_UNUSED,2 ), 8 , GFLAGS),0 , "hclk_pdbus_niu3" , "hclk_pdbus" , CLK_IGNORE_UNUSED,2 ), 9 , GFLAGS),0 , "pclk_grf" , "pclk_pdbus" , CLK_IGNORE_UNUSED,6 ), 15 , GFLAGS),0 , "pclk_sgrf" , "pclk_pdbus" , CLK_IGNORE_UNUSED,8 ), 4 , GFLAGS),0 , "aclk_sysram" , "hclk_pdbus" , CLK_IGNORE_UNUSED,3 ), 9 , GFLAGS),0 , "pclk_intmux" , "pclk_pdbus" , CLK_IGNORE_UNUSED,7 ), 14 , GFLAGS),/* * Clock-Architecture Diagram 6 /* PD_AUDIO */ 0 , "hclk_pdaudio_niu" , "hclk_pdaudio" , CLK_IGNORE_UNUSED,9 ), 2 , GFLAGS),0 , "pclk_pdaudio_niu" , "hclk_pdaudio" , CLK_IGNORE_UNUSED,9 ), 3 , GFLAGS),/* * Clock-Architecture Diagram 9 /* PD_VO */ 0 , "aclk_pdvo_niu" , "aclk_pdvo" , CLK_IGNORE_UNUSED,14 ), 3 , GFLAGS),0 , "hclk_pdvo_niu" , "hclk_pdvo" , CLK_IGNORE_UNUSED,14 ), 4 , GFLAGS),0 , "pclk_pdvo_niu" , "pclk_pdvo" , CLK_IGNORE_UNUSED,14 ), 5 , GFLAGS),/* * Clock-Architecture Diagram 12 /* PD_PHP */ 0 , "aclk_pdphpmid" , "aclk_pdphp" , CLK_IGNORE_UNUSED,17 ), 2 , GFLAGS),0 , "hclk_pdphpmid" , "hclk_pdphp" , CLK_IGNORE_UNUSED,17 ), 3 , GFLAGS),0 , "aclk_pdphpmid_niu" , "aclk_pdphpmid" , CLK_IGNORE_UNUSED,17 ), 4 , GFLAGS),0 , "hclk_pdphpmid_niu" , "hclk_pdphpmid" , CLK_IGNORE_UNUSED,17 ), 5 , GFLAGS),/* PD_SDCARD */ 0 , "hclk_pdsdmmc_niu" , "hclk_pdsdmmc" , CLK_IGNORE_UNUSED,17 ), 7 , GFLAGS),/* PD_SDIO */ 0 , "hclk_pdsdio_niu" , "hclk_pdsdio" , CLK_IGNORE_UNUSED,17 ), 9 , GFLAGS),/* PD_NVM */ 0 , "hclk_pdnvm_niu" , "hclk_pdnvm" , CLK_IGNORE_UNUSED,18 ), 3 , GFLAGS),/* PD_USB */ 0 , "aclk_pdusb_niu" , "aclk_pdusb" , CLK_IGNORE_UNUSED,19 ), 2 , GFLAGS),0 , "hclk_pdusb_niu" , "hclk_pdusb" , CLK_IGNORE_UNUSED,19 ), 3 , GFLAGS),/* PD_GMAC */ 0 , "aclk_pdgmac_niu" , "aclk_pdgmac" , CLK_IGNORE_UNUSED,20 ), 2 , GFLAGS),0 , "pclk_pdgmac_niu" , "pclk_pdgmac" , CLK_IGNORE_UNUSED,20 ), 3 , GFLAGS),/* * Clock-Architecture Diagram 13 /* PD_DDR */ 0 , "pclk_pdddr_pre" , "gpll" , CLK_IGNORE_UNUSED,64 ), 0 , 5 , DFLAGS,21 ), 0 , GFLAGS),"pclk_pdddr" , "pclk_pdddr_pre" , CLK_IGNORE_UNUSED,21 ), 15 , GFLAGS),0 , "pclk_ddr_msch" , "pclk_pdddr" , CLK_IGNORE_UNUSED,21 ), 6 , GFLAGS),"sclk_ddrc" , mux_dpll_gpll_p, CLK_IGNORE_UNUSED,64 ), 15 , 1 , MFLAGS, 8 , 5 , DFLAGS |"clk_ddrphy" , mux_dpll_gpll_p, CLK_IGNORE_UNUSED,64 ), 15 , 1 , MFLAGS, 8 , 5 , DFLAGS,21 ), 8 , GFLAGS),0 , "clk1x_phy" , "clk_ddrphy" , CLK_IGNORE_UNUSED,23 ), 1 , GFLAGS),0 , "clk_ddr_msch" , "clk_ddrphy" , CLK_IGNORE_UNUSED,21 ), 10 , GFLAGS),0 , "pclk_ddr_dfictl" , "pclk_pdddr" , CLK_IGNORE_UNUSED,21 ), 2 , GFLAGS),0 , "clk_ddr_dfictl" , "clk_ddrphy" , CLK_IGNORE_UNUSED,21 ), 13 , GFLAGS),0 , "pclk_ddr_standby" , "pclk_pdddr" , CLK_IGNORE_UNUSED,21 ), 4 , GFLAGS),0 , "clk_ddr_standby" , "clk_ddrphy" , CLK_IGNORE_UNUSED,21 ), 14 , GFLAGS),0 , "aclk_ddr_split" , "clk_ddrphy" , CLK_IGNORE_UNUSED,21 ), 9 , GFLAGS),0 , "pclk_ddr_grf" , "pclk_pdddr" , CLK_IGNORE_UNUSED,21 ), 5 , GFLAGS),"pclk_ddr_mon" , "pclk_pdddr" , CLK_IGNORE_UNUSED,21 ), 3 , GFLAGS),"clk_ddr_mon" , "clk_ddrphy" , CLK_IGNORE_UNUSED,20 ), 15 , GFLAGS),"tmclk_ddr_mon" , "xin24m" , CLK_IGNORE_UNUSED,21 ), 7 , GFLAGS),/* * Clock-Architecture Diagram 15 0 , "pclk_topniu" , "pclk_pdtop" , CLK_IGNORE_UNUSED,23 ), 9 , GFLAGS),"pclk_topcru" , "pclk_pdtop" , CLK_IGNORE_UNUSED,23 ), 10 , GFLAGS),"pclk_topgrf" , "pclk_pdtop" , CLK_IGNORE_UNUSED,23 ), 11 , GFLAGS),"pclk_cpuemadet" , "pclk_pdtop" , CLK_IGNORE_UNUSED,23 ), 12 , GFLAGS),"pclk_ddrphy" , "pclk_pdtop" , CLK_IGNORE_UNUSED,23 ), 0 , GFLAGS),static const char *const rv1126_cru_critical_clocks[] __initconst = {"gpll" ,"cpll" ,"hpll" ,"armclk" ,"pclk_dbg" ,"pclk_pdpmu" ,"aclk_pdbus" ,"hclk_pdbus" ,"pclk_pdbus" ,"aclk_pdphp" ,"hclk_pdphp" ,"clk_ddrphy" ,"pclk_pdddr" ,"pclk_pdtop" ,"clk_usbhost_utmi_ohci" ,"aclk_pdjpeg_niu" ,"hclk_pdjpeg_niu" ,"aclk_pdvdec_niu" ,"hclk_pdvdec_niu" ,static void __init rv1126_pmu_clk_init(struct device_node *np)struct rockchip_clk_provider *ctx;void __iomem *reg_base;0 );if (!reg_base) {"%s: could not map cru pmu region\n" , __func__);return ;if (IS_ERR(ctx)) {"%s: rockchip pmu clk init failed\n" , __func__);return ;2 , reg_base + RV1126_PMU_SOFTRST_CON(0 ),static void __init rv1126_clk_init(struct device_node *np)struct rockchip_clk_provider *ctx;void __iomem *reg_base;0 );if (!reg_base) {"%s: could not map cru region\n" , __func__);return ;if (IS_ERR(ctx)) {"%s: rockchip clk init failed\n" , __func__);return ;"armclk" ,15 , reg_base + RV1126_SOFTRST_CON(0 ),struct clk_rv1126_inits {void (*inits)(struct device_node *np);static const struct clk_rv1126_inits clk_rv1126_pmucru_init = {static const struct clk_rv1126_inits clk_rv1126_cru_init = {static const struct of_device_id clk_rv1126_match_table[] = {"rockchip,rv1126-cru" ,"rockchip,rv1126-pmucru" ,static int __init clk_rv1126_probe(struct platform_device *pdev)struct device_node *np = pdev->dev.of_node;const struct clk_rv1126_inits *init_data;struct clk_rv1126_inits *)of_device_get_match_data(&pdev->dev);if (!init_data)return -EINVAL;if (init_data->inits)return 0 ;static struct platform_driver clk_rv1126_driver = {"clk-rv1126" ,true ,
Messung V0.5 in Prozent C=97 H=94 G=95
