// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2023 Rockchip Electronics Co. Ltd. * Author: Elaine Zhang <zhangqing@rock-chips.com> #include <linux/clk-provider.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/platform_device.h>#include <linux/syscore_ops.h>#include <linux/mfd/syscon.h>#include <linux/slab.h>#include <dt-bindings/clock/rockchip,rk3576-cru.h>#include "clk.h" #define RK3576_GRF_SOC_STATUS0 0 x600#define RK3576_PMU0_GRF_OSC_CON6 0 x18#define RK3576_VCCIO_IOC_MISC_CON0 0 x6400enum rk3576_plls {static struct rockchip_pll_rate_table rk3576_pll_rates[] = {/* _mhz, _p, _m, _s, _k */ 2520000000 , 2 , 210 , 0 , 0 ),2496000000 , 2 , 208 , 0 , 0 ),2472000000 , 2 , 206 , 0 , 0 ),2448000000 , 2 , 204 , 0 , 0 ),2424000000 , 2 , 202 , 0 , 0 ),2400000000 , 2 , 200 , 0 , 0 ),2376000000 , 2 , 198 , 0 , 0 ),2352000000 , 2 , 196 , 0 , 0 ),2328000000 , 2 , 194 , 0 , 0 ),2304000000 , 2 , 192 , 0 , 0 ),2280000000 , 2 , 190 , 0 , 0 ),2256000000 , 2 , 376 , 1 , 0 ),2232000000 , 2 , 372 , 1 , 0 ),2208000000 , 2 , 368 , 1 , 0 ),2184000000 , 2 , 364 , 1 , 0 ),2160000000 , 2 , 360 , 1 , 0 ),2136000000 , 2 , 356 , 1 , 0 ),2112000000 , 2 , 352 , 1 , 0 ),2088000000 , 2 , 348 , 1 , 0 ),2064000000 , 2 , 344 , 1 , 0 ),2040000000 , 2 , 340 , 1 , 0 ),2016000000 , 2 , 336 , 1 , 0 ),1992000000 , 2 , 332 , 1 , 0 ),1968000000 , 2 , 328 , 1 , 0 ),1944000000 , 2 , 324 , 1 , 0 ),1920000000 , 2 , 320 , 1 , 0 ),1896000000 , 2 , 316 , 1 , 0 ),1872000000 , 2 , 312 , 1 , 0 ),1848000000 , 2 , 308 , 1 , 0 ),1824000000 , 2 , 304 , 1 , 0 ),1800000000 , 2 , 300 , 1 , 0 ),1776000000 , 2 , 296 , 1 , 0 ),1752000000 , 2 , 292 , 1 , 0 ),1728000000 , 2 , 288 , 1 , 0 ),1704000000 , 2 , 284 , 1 , 0 ),1680000000 , 2 , 280 , 1 , 0 ),1656000000 , 2 , 276 , 1 , 0 ),1632000000 , 2 , 272 , 1 , 0 ),1608000000 , 2 , 268 , 1 , 0 ),1584000000 , 2 , 264 , 1 , 0 ),1560000000 , 2 , 260 , 1 , 0 ),1536000000 , 2 , 256 , 1 , 0 ),1512000000 , 2 , 252 , 1 , 0 ),1488000000 , 2 , 248 , 1 , 0 ),1464000000 , 2 , 244 , 1 , 0 ),1440000000 , 2 , 240 , 1 , 0 ),1416000000 , 2 , 236 , 1 , 0 ),1392000000 , 2 , 232 , 1 , 0 ),1320000000 , 2 , 220 , 1 , 0 ),1200000000 , 2 , 200 , 1 , 0 ),1188000000 , 2 , 198 , 1 , 0 ),1100000000 , 3 , 550 , 2 , 0 ),1008000000 , 2 , 336 , 2 , 0 ),1000000000 , 3 , 500 , 2 , 0 ),983040000 , 4 , 655 , 2 , 23592 ),955520000 , 3 , 477 , 2 , 49806 ),903168000 , 6 , 903 , 2 , 11009 ),900000000 , 2 , 300 , 2 , 0 ),816000000 , 2 , 272 , 2 , 0 ),786432000 , 2 , 262 , 2 , 9437 ),786000000 , 1 , 131 , 2 , 0 ),785560000 , 3 , 392 , 2 , 51117 ),722534400 , 8 , 963 , 2 , 24850 ),600000000 , 2 , 200 , 2 , 0 ),594000000 , 2 , 198 , 2 , 0 ),408000000 , 2 , 272 , 3 , 0 ),312000000 , 2 , 208 , 3 , 0 ),216000000 , 2 , 288 , 4 , 0 ),96000000 , 2 , 256 , 5 , 0 ),/* sentinel */ }, static struct rockchip_pll_rate_table rk3576_ppll_rates[] = {/* _mhz, _p, _m, _s, _k */ 1300000000 , 3 , 325 , 2 , 0 ),/* sentinel */ }, #define RK3576_ACLK_M_BIGCORE_DIV_MASK 0 x1f#define RK3576_ACLK_M_BIGCORE_DIV_SHIFT 0 #define RK3576_ACLK_M_LITCORE_DIV_MASK 0 x1f#define RK3576_ACLK_M_LITCORE_DIV_SHIFT 8 #define RK3576_PCLK_DBG_LITCORE_DIV_MASK 0 x1f#define RK3576_PCLK_DBG_LITCORE_DIV_SHIFT 0 #define RK3576_ACLK_CCI_DIV_MASK 0 x1f#define RK3576_ACLK_CCI_DIV_SHIFT 7 #define RK3576_ACLK_CCI_MUX_MASK 0 x3#define RK3576_ACLK_CCI_MUX_SHIFT 12 #define RK3576_BIGCORE_CLKSEL2(_amcore) \2 ), \1 , RK3576_ACLK_M_BIGCORE_DIV_MASK, \#define RK3576_LITCORE_CLKSEL1(_amcore) \1 ), \1 , RK3576_ACLK_M_LITCORE_DIV_MASK, \#define RK3576_LITCORE_CLKSEL2(_pclkdbg) \2 ), \1 , RK3576_PCLK_DBG_LITCORE_DIV_MASK, \#define RK3576_CCI_CLKSEL4(_ccisel, _div) \4 ), \1 , RK3576_ACLK_CCI_DIV_MASK, \#define RK3576_CPUBCLK_RATE(_prate, _amcore) \## U, \#define RK3576_CPULCLK_RATE(_prate, _amcore, _pclkdbg, _ccisel) \## U, \2 , 2 ), \2 ), \static struct rockchip_cpuclk_rate_table rk3576_cpubclk_rates[] __initdata = {2496000000 , 2 ),2400000000 , 2 ),2304000000 , 2 ),2208000000 , 2 ),2184000000 , 2 ),2088000000 , 2 ),2040000000 , 2 ),2016000000 , 2 ),1992000000 , 2 ),1896000000 , 2 ),1800000000 , 2 ),1704000000 , 2 ),1608000000 , 2 ),1584000000 , 2 ),1560000000 , 2 ),1536000000 , 2 ),1512000000 , 2 ),1488000000 , 2 ),1464000000 , 2 ),1440000000 , 2 ),1416000000 , 2 ),1392000000 , 2 ),1368000000 , 2 ),1344000000 , 2 ),1320000000 , 2 ),1296000000 , 2 ),1272000000 , 2 ),1248000000 , 2 ),1224000000 , 2 ),1200000000 , 2 ),1104000000 , 2 ),1008000000 , 2 ),912000000 , 2 ),816000000 , 2 ),696000000 , 2 ),600000000 , 2 ),408000000 , 2 ),312000000 , 2 ),216000000 , 2 ),96000000 , 2 ),static const struct rockchip_cpuclk_reg_data rk3576_cpubclk_data = {0 ] = RK3576_BIGCORE_CLKSEL_CON(1 ),0 ] = 7 ,0 ] = 0 x1f,1 ,1 ,0 ,12 ,0 x3,static struct rockchip_cpuclk_rate_table rk3576_cpulclk_rates[] __initdata = {2400000000 , 2 , 6 , 3 ),2304000000 , 2 , 6 , 3 ),2208000000 , 2 , 6 , 3 ),2184000000 , 2 , 6 , 3 ),2088000000 , 2 , 6 , 3 ),2040000000 , 2 , 6 , 3 ),2016000000 , 2 , 6 , 3 ),1992000000 , 2 , 6 , 3 ),1896000000 , 2 , 6 , 3 ),1800000000 , 2 , 6 , 3 ),1704000000 , 2 , 6 , 3 ),1608000000 , 2 , 6 , 3 ),1584000000 , 2 , 6 , 3 ),1560000000 , 2 , 6 , 3 ),1536000000 , 2 , 6 , 3 ),1512000000 , 2 , 6 , 3 ),1488000000 , 2 , 6 , 3 ),1464000000 , 2 , 6 , 3 ),1440000000 , 2 , 6 , 3 ),1416000000 , 2 , 6 , 3 ),1392000000 , 2 , 6 , 3 ),1368000000 , 2 , 6 , 3 ),1344000000 , 2 , 6 , 3 ),1320000000 , 2 , 6 , 3 ),1296000000 , 2 , 6 , 3 ),1272000000 , 2 , 6 , 3 ),1248000000 , 2 , 6 , 3 ),1224000000 , 2 , 6 , 3 ),1200000000 , 2 , 6 , 2 ),1104000000 , 2 , 6 , 2 ),1008000000 , 2 , 6 , 2 ),912000000 , 2 , 6 , 2 ),816000000 , 2 , 6 , 2 ),696000000 , 2 , 6 , 2 ),600000000 , 2 , 6 , 2 ),408000000 , 2 , 6 , 2 ),312000000 , 2 , 6 , 2 ),216000000 , 2 , 6 , 2 ),96000000 , 2 , 6 , 2 ),static const struct rockchip_cpuclk_reg_data rk3576_cpulclk_data = {0 ] = RK3576_LITCORE_CLKSEL_CON(0 ),0 ] = 7 ,0 ] = 0 x1f,1 ,1 ,0 ,12 ,0 x3,#define MFLAGS CLK_MUX_HIWORD_MASK#define DFLAGS CLK_DIVIDER_HIWORD_MASK#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)"xin24m" , "xin32k" };"xin24m" , "xin_osc0_div" };"xin24m" , "pll_lpll" , "lpll" };"xin24m" , "pll_bpll" , "bpll" };"gpll" , "xin24m" };"cpll" , "xin24m" };"gpll" , "cpll" };"gpll" , "spll" };"gpll" , "cpll" , "aupll" };"gpll" , "cpll" , "xin24m" };"gpll" , "cpll" , "xin24m" , "spll" };"gpll" , "cpll" , "aupll" , "xin24m" };"gpll" , "cpll" , "aupll" , "spll" };"gpll" , "cpll" , "aupll" , "spll" , "lpll_dummy" };"gpll" , "cpll" , "spll" , "bpll_dummy" };"gpll" , "cpll" , "lpll_dummy" , "bpll_dummy" };"gpll" , "spll" , "cpll" , "bpll_dummy" , "lpll_dummy" };"gpll" , "cpll" , "vpll" , "aupll" , "xin24m" };"gpll" , "cpll" , "spll" , "aupll" , "bpll_dummy" };"gpll" , "cpll" , "spll" , "bpll_dummy" , "lpll_dummy" };"gpll" , "cpll" , "spll" , "lpll_dummy" , "bpll_dummy" };"gpll" , "cpll" , "vpll" , "bpll_dummy" , "lpll_dummy" };"gpll" , "spll" , "aupll" , "bpll_dummy" , "lpll_dummy" };"gpll" , "spll" , "isp_pvtpll" , "bpll_dummy" , "lpll_dummy" "gpll" , "cpll" , "spll" , "aupll" , "lpll_dummy" , "xin24m" };"gpll" , "cpll" , "spll" , "vpll" , "bpll_dummy" , "lpll_dummy" };"cpll" , "vpll" , "lpll_dummy" , "bpll_dummy" };"xin24m" , "cci_pvtpll" , "gpll" , "lpll" };"xin24m" , "spll" , "gpll" , "cpll" };"xin24m" , "clk_audio_frac_0" , "clk_audio_frac_1" , "clk_audio_frac_2" ,"clk_audio_frac_3" , "clk_audio_int_0" , "clk_audio_int_1" , "clk_audio_int_2" };"clk_audio_frac_0" , "clk_audio_frac_1" , "clk_audio_frac_2" , "clk_audio_frac_3" };"clk_cpll_div10" , "xin24m" };"clk_cpll_div10" , "clk_cpll_div20" , "xin24m" };"clk_cpll_div10" , "xin24m" , "lclk_asrc_src_0" };"clk_cpll_div10" , "xin24m" , "lclk_asrc_src_1" };"clk_gpll_div8" , "clk_cpll_div10" , "clk_cpll_div20" , "xin24m" };"clk_gpll_div6" , "clk_cpll_div10" , "clk_cpll_div20" , "xin24m" };"clk_gpll_div3" , "clk_gpll_div6" , "clk_cpll_div10" , "xin24m" };"clk_cpll_div2" , "clk_cpll_div4" , "clk_cpll_div10" , "xin24m" };"clk_gpll_div2" , "clk_gpll_div3" , "clk_gpll_div4" , "xin24m" };"clk_spll_div2" , "clk_spll_div4" , "clk_spll_div6" , "xin24m" };"clk_spll_div4" , "clk_spll_div6" , "clk_spll_div12" , "xin24m" };"clk_spll_div6" , "clk_spll_div12" , "xin24m" };"mclk_sai0_8ch_src" , "sai0_mclkin" , "sai1_mclkin" };"mclk_sai1_8ch_src" , "sai1_mclkin" };"mclk_sai2_2ch_src" , "sai2_mclkin" , "sai1_mclkin" };"mclk_sai3_2ch_src" , "sai3_mclkin" , "sai1_mclkin" };"mclk_sai4_2ch_src" , "sai4_mclkin" , "sai1_mclkin" };"mclk_sai5_8ch_src" , "sai1_mclkin" };"mclk_sai6_8ch_src" , "sai1_mclkin" };"mclk_sai7_8ch_src" , "sai1_mclkin" };"mclk_sai8_8ch_src" , "sai1_mclkin" };"mclk_sai9_8ch_src" , "sai1_mclkin" };"clk_uart1_src_top" , "xin24m" };"gpll" , "cpll" , "gmac1_ptp_refclk_in" };"gpll" , "cpll" , "gmac0_ptp_refclk_in" };"gpll" , "cpll" , "vpll" , "aupll" , "lpll_dummy" ,"dclk_ebc_frac" , "xin24m" };"dclk_vp0_src" , "clk_hdmiphy_pixel0" };"dclk_vp1_src" , "clk_hdmiphy_pixel0" };"dclk_vp2_src" , "clk_hdmiphy_pixel0" };"gpll" , "cpll" , "aupll" , "xin24m" , "clk_uart_frac_0" ,"clk_uart_frac_1" , "clk_uart_frac_2" };"sai0_mclkin" , "sai1_mclkin" , "sai2_mclkin" ,"sai3_mclkin" , "sai4_mclkin" , "sai_sclkin_freq" };"sai0_mclkin" , "sai1_mclkin" , "sai2_mclkin" ,"sai3_mclkin" , "sai4_mclkin" , "sai_sclkin_counter" };"sai0_sclk_in" , "sai1_sclk_in" , "sai2_sclk_in" ,"sai3_sclk_in" , "sai4_sclk_in" };"clk_pcie_100m_src" , "clk_pcie_100m_nduty_src" ,"xin24m" };"clk_gpll_div6" , "clk_cpll_div10" ,"aclk_vi_root_inter" , "xin24m" };"xin24m" , "clk_gpio_mphy_i" , "clk_ref_mphy_26m" };"clk_200m_pmu_src" , "clk_100m_pmu_src" ,"clk_50m_pmu_src" , "xin24m" };"clk_100m_pmu_src" , "clk_50m_pmu_src" , "xin24m" };"clk_100m_pmu_src" , "xin24m" , "xin_osc0_div" };"xin24m" , "clk_pmuphy_ref_src" };"usbphy0_24m" , "usbphy1_24m" };"xin24m" , "clk_usbphy_ref_src" };"xin24m" , "clk_aupll_ref_io" };static struct rockchip_pll_clock rk3576_pll_clks[] __initdata = {"bpll" , mux_pll_p,0 , RK3576_PLL_CON(0 ),0 , 15 , 0 , rk3576_pll_rates),"lpll" , mux_pll_p,0 , RK3576_LPLL_CON(16 ),0 , 15 , 0 , rk3576_pll_rates),"vpll" , mux_pll_p,0 , RK3576_PLL_CON(88 ),4 , 15 , 0 , rk3576_pll_rates),"aupll" , mux_pll_p,0 , RK3576_PLL_CON(96 ),6 , 15 , 0 , rk3576_pll_rates),"cpll" , mux_pll_p,104 ),8 , 15 , 0 , rk3576_pll_rates),"gpll" , mux_pll_p,112 ),2 , 15 , 0 , rk3576_pll_rates),"ppll" , mux_pll_p,128 ),10 , 15 , 0 , rk3576_ppll_rates),static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = {/* * CRU Clock-Architecture /* fixed */ 0 , "xin12m" , "xin24m" , 0 , 1 , 2 ),"xin_osc0_div" , "xin24m" , CLK_IS_CRITICAL,21 ), 0 ,7 ), 11 , GFLAGS),0 , "clk_spll_div12" , "spll" , 0 , 1 , 12 ),0 , "clk_spll_div6" , "spll" , 0 , 1 , 6 ),0 , "clk_spll_div4" , "spll" , 0 , 1 , 4 ),0 , "lpll_div2" , "lpll" , 0 , 1 , 2 ),0 , "bpll_div4" , "bpll" , 0 , 1 , 4 ),/* top */ "clk_cpll_div20" , gpll_cpll_p, CLK_IS_CRITICAL,0 ), 5 , 1 , MFLAGS, 0 , 5 , DFLAGS,0 ), 0 , GFLAGS),"clk_cpll_div10" , gpll_cpll_p, CLK_IS_CRITICAL,0 ), 11 , 1 , MFLAGS, 6 , 5 , DFLAGS,0 ), 1 , GFLAGS),"clk_gpll_div8" , gpll_cpll_p, CLK_IS_CRITICAL,1 ), 5 , 1 , MFLAGS, 0 , 5 , DFLAGS,0 ), 2 , GFLAGS),"clk_gpll_div6" , gpll_cpll_p, CLK_IS_CRITICAL,1 ), 11 , 1 , MFLAGS, 6 , 5 , DFLAGS,0 ), 3 , GFLAGS),"clk_cpll_div4" , gpll_cpll_p, CLK_IS_CRITICAL,2 ), 5 , 1 , MFLAGS, 0 , 5 , DFLAGS,0 ), 4 , GFLAGS),"clk_gpll_div4" , gpll_cpll_p, CLK_IS_CRITICAL,2 ), 11 , 1 , MFLAGS, 6 , 5 , DFLAGS,0 ), 5 , GFLAGS),"clk_spll_div2" , gpll_cpll_spll_bpll_p, CLK_IS_CRITICAL,3 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,0 ), 6 , GFLAGS),"clk_gpll_div3" , gpll_cpll_p, CLK_IS_CRITICAL,3 ), 12 , 1 , MFLAGS, 7 , 5 , DFLAGS,0 ), 7 , GFLAGS),"clk_cpll_div2" , gpll_cpll_p, CLK_IS_CRITICAL,4 ), 11 , 1 , MFLAGS, 6 , 5 , DFLAGS,0 ), 9 , GFLAGS),"clk_gpll_div2" , gpll_cpll_p, CLK_IS_CRITICAL,5 ), 5 , 1 , MFLAGS, 0 , 5 , DFLAGS,0 ), 10 , GFLAGS),"clk_spll_div1" , gpll_cpll_spll_bpll_lpll_p, CLK_IS_CRITICAL,6 ), 5 , 3 , MFLAGS, 0 , 5 , DFLAGS,0 ), 12 , GFLAGS),"pclk_top_root" , mux_100m_50m_24m_p, CLK_IS_CRITICAL,8 ), 7 , 2 , MFLAGS,1 ), 1 , GFLAGS),"aclk_top" , gpll_cpll_aupll_p, CLK_IS_CRITICAL,9 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,1 ), 3 , GFLAGS),"aclk_top_mid" , gpll_cpll_p, CLK_IS_CRITICAL,10 ), 5 , 1 , MFLAGS, 0 , 5 , DFLAGS,1 ), 6 , GFLAGS),"aclk_secure_high" , gpll_spll_aupll_bpll_lpll_p, CLK_IS_CRITICAL,10 ), 11 , 3 , MFLAGS, 6 , 5 , DFLAGS,1 ), 7 , GFLAGS),"hclk_top" , mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,19 ), 2 , 2 , MFLAGS,1 ), 14 , GFLAGS),"hclk_vo0vop_channel" , mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,19 ), 6 , 2 , MFLAGS,2 ), 0 , GFLAGS),"aclk_vo0vop_channel" , gpll_cpll_lpll_bpll_p, CLK_IS_CRITICAL,19 ), 12 , 2 , MFLAGS, 8 , 4 , DFLAGS,2 ), 1 , GFLAGS),"clk_audio_frac_0_src" , gpll_cpll_aupll_24m_p, 0 ,13 ), 0 , 2 , MFLAGS),"clk_audio_frac_0" , "clk_audio_frac_0_src" , 0 ,12 ), 0 ,1 ), 10 , GFLAGS),"clk_audio_frac_1_src" , gpll_cpll_aupll_24m_p, 0 ,15 ), 0 , 2 , MFLAGS),"clk_audio_frac_1" , "clk_audio_frac_1_src" , 0 ,14 ), 0 ,1 ), 11 , GFLAGS),"clk_audio_frac_2_src" , gpll_cpll_aupll_24m_p, 0 ,17 ), 0 , 2 , MFLAGS),"clk_audio_frac_2" , "clk_audio_frac_2_src" , 0 ,16 ), 0 ,1 ), 12 , GFLAGS),"clk_audio_frac_3_src" , gpll_cpll_aupll_24m_p, 0 ,19 ), 0 , 2 , MFLAGS),"clk_audio_frac_3" , "clk_audio_frac_3_src" , 0 ,18 ), 0 ,1 ), 13 , GFLAGS),0 , "clk_uart_frac_0_src" , gpll_cpll_aupll_24m_p, 0 ,22 ), 0 , 2 , MFLAGS),"clk_uart_frac_0" , "clk_uart_frac_0_src" , 0 ,21 ), 0 ,2 ), 5 , GFLAGS),0 , "clk_uart_frac_1_src" , gpll_cpll_aupll_24m_p, 0 ,24 ), 0 , 2 , MFLAGS),"clk_uart_frac_1" , "clk_uart_frac_1_src" , 0 ,23 ), 0 ,2 ), 6 , GFLAGS),0 , "clk_uart_frac_2_src" , gpll_cpll_aupll_24m_p, 0 ,26 ), 0 , 2 , MFLAGS),"clk_uart_frac_2" , "clk_uart_frac_2_src" , 0 ,25 ), 0 ,2 ), 7 , GFLAGS),"clk_uart1_src_top" , clk_uart_p, 0 ,27 ), 13 , 3 , MFLAGS, 5 , 8 , DFLAGS,2 ), 13 , GFLAGS),"clk_audio_int_0" , "gpll" , 0 ,28 ), 0 , 5 , DFLAGS,2 ), 14 , GFLAGS),"clk_audio_int_1" , "cpll" , 0 ,28 ), 5 , 5 , DFLAGS,2 ), 15 , GFLAGS),"clk_audio_int_2" , "aupll" , 0 ,28 ), 10 , 5 , DFLAGS,3 ), 0 , GFLAGS),"clk_pdm0_src_top" , audio_frac_int_p, 0 ,29 ), 9 , 3 , MFLAGS, 0 , 9 , DFLAGS,3 ), 2 , GFLAGS),"clk_gmac0_125m_src" , "cpll" , 0 ,30 ), 10 , 5 , DFLAGS,3 ), 6 , GFLAGS),"clk_gmac1_125m_src" , "cpll" , 0 ,31 ), 0 , 5 , DFLAGS,3 ), 7 , GFLAGS),"lclk_asrc_src_0" , audio_frac_p, 0 ,31 ), 10 , 2 , MFLAGS, 5 , 5 , DFLAGS,3 ), 10 , GFLAGS),"lclk_asrc_src_1" , audio_frac_p, 0 ,32 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,3 ), 11 , GFLAGS),"ref_clk0_out_pll" , gpll_cpll_spll_aupll_lpll_24m_p, 0 ,33 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,4 ), 1 , GFLAGS),"ref_clk1_out_pll" , gpll_cpll_spll_aupll_lpll_24m_p, 0 ,34 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,4 ), 2 , GFLAGS),"ref_clk2_out_pll" , gpll_cpll_spll_aupll_lpll_24m_p, 0 ,35 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,4 ), 3 , GFLAGS),"refclko25m_gmac0_out" , gpll_cpll_p, 0 ,36 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,5 ), 10 , GFLAGS),"refclko25m_gmac1_out" , gpll_cpll_p, 0 ,36 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,5 ), 11 , GFLAGS),"clk_cifout_out" , gpll_cpll_24m_spll_p, 0 ,37 ), 8 , 2 , MFLAGS, 0 , 8 , DFLAGS,5 ), 12 , GFLAGS),"clk_gmac0_rmii_cru" , "clk_cpll_div20" , 0 ,5 ), 13 , GFLAGS),"clk_gmac1_rmii_cru" , "clk_cpll_div20" , 0 ,5 ), 14 , GFLAGS),"clk_otpc_auto_rd_g" , "xin24m" , 0 ,5 ), 15 , GFLAGS),"clk_otp_phy_g" , "xin24m" , 0 ,6 ), 0 , GFLAGS),"clk_mipi_cameraout_m0" , mux_24m_spll_gpll_cpll_p, 0 ,38 ), 8 , 2 , MFLAGS, 0 , 8 , DFLAGS,6 ), 3 , GFLAGS),"clk_mipi_cameraout_m1" , mux_24m_spll_gpll_cpll_p, 0 ,39 ), 8 , 2 , MFLAGS, 0 , 8 , DFLAGS,6 ), 4 , GFLAGS),"clk_mipi_cameraout_m2" , mux_24m_spll_gpll_cpll_p, 0 ,40 ), 8 , 2 , MFLAGS, 0 , 8 , DFLAGS,6 ), 5 , GFLAGS),"mclk_pdm0_src_top" , audio_frac_int_p, 0 ,41 ), 7 , 3 , MFLAGS, 2 , 5 , DFLAGS,6 ), 8 , GFLAGS),/* bus */ "hclk_bus_root" , mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,55 ), 0 , 2 , MFLAGS,11 ), 0 , GFLAGS),"pclk_bus_root" , mux_100m_50m_24m_p, CLK_IS_CRITICAL,55 ), 2 , 2 , MFLAGS,11 ), 1 , GFLAGS),"aclk_bus_root" , gpll_cpll_p, CLK_IS_CRITICAL,55 ), 9 , 1 , MFLAGS, 4 , 5 , DFLAGS,11 ), 2 , GFLAGS),"hclk_can0" , "hclk_bus_root" , 0 ,11 ), 6 , GFLAGS),"clk_can0" , gpll_cpll_24m_p, 0 ,56 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,11 ), 7 , GFLAGS),"hclk_can1" , "hclk_bus_root" , 0 ,11 ), 8 , GFLAGS),"clk_can1" , gpll_cpll_24m_p, 0 ,56 ), 12 , 2 , MFLAGS, 7 , 5 , DFLAGS,11 ), 9 , GFLAGS),"clk_key_shift" , "xin24m" , CLK_IS_CRITICAL,11 ), 15 , GFLAGS),"pclk_i2c1" , "pclk_bus_root" , 0 ,12 ), 0 , GFLAGS),"pclk_i2c2" , "pclk_bus_root" , 0 ,12 ), 1 , GFLAGS),"pclk_i2c3" , "pclk_bus_root" , 0 ,12 ), 2 , GFLAGS),"pclk_i2c4" , "pclk_bus_root" , 0 ,12 ), 3 , GFLAGS),"pclk_i2c5" , "pclk_bus_root" , 0 ,12 ), 4 , GFLAGS),"pclk_i2c6" , "pclk_bus_root" , 0 ,12 ), 5 , GFLAGS),"pclk_i2c7" , "pclk_bus_root" , 0 ,12 ), 6 , GFLAGS),"pclk_i2c8" , "pclk_bus_root" , 0 ,12 ), 7 , GFLAGS),"pclk_i2c9" , "pclk_bus_root" , 0 ,12 ), 8 , GFLAGS),"pclk_wdt_busmcu" , "pclk_bus_root" , 0 ,12 ), 9 , GFLAGS),"tclk_wdt_busmcu" , "xin24m" , 0 ,12 ), 10 , GFLAGS),"aclk_gic" , "aclk_bus_root" , CLK_IS_CRITICAL,12 ), 11 , GFLAGS),"clk_i2c1" , mux_200m_100m_50m_24m_p, 0 ,57 ), 0 , 2 , MFLAGS,12 ), 12 , GFLAGS),"clk_i2c2" , mux_200m_100m_50m_24m_p, 0 ,57 ), 2 , 2 , MFLAGS,12 ), 13 , GFLAGS),"clk_i2c3" , mux_200m_100m_50m_24m_p, 0 ,57 ), 4 , 2 , MFLAGS,12 ), 14 , GFLAGS),"clk_i2c4" , mux_200m_100m_50m_24m_p, 0 ,57 ), 6 , 2 , MFLAGS,12 ), 15 , GFLAGS),"clk_i2c5" , mux_200m_100m_50m_24m_p, 0 ,57 ), 8 , 2 , MFLAGS,13 ), 0 , GFLAGS),"clk_i2c6" , mux_200m_100m_50m_24m_p, 0 ,57 ), 10 , 2 , MFLAGS,13 ), 1 , GFLAGS),"clk_i2c7" , mux_200m_100m_50m_24m_p, 0 ,57 ), 12 , 2 , MFLAGS,13 ), 2 , GFLAGS),"clk_i2c8" , mux_200m_100m_50m_24m_p, 0 ,57 ), 14 , 2 , MFLAGS,13 ), 3 , GFLAGS),"clk_i2c9" , mux_200m_100m_50m_24m_p, 0 ,58 ), 0 , 2 , MFLAGS,13 ), 4 , GFLAGS),"pclk_saradc" , "pclk_bus_root" , 0 ,13 ), 6 , GFLAGS),"clk_saradc" , gpll_24m_p, 0 ,58 ), 12 , 1 , MFLAGS, 4 , 8 , DFLAGS,13 ), 7 , GFLAGS),"pclk_tsadc" , "pclk_bus_root" , 0 ,13 ), 8 , GFLAGS),"clk_tsadc" , "xin24m" , 0 ,59 ), 0 , 8 , DFLAGS,13 ), 9 , GFLAGS),"pclk_uart0" , "pclk_bus_root" , 0 ,13 ), 10 , GFLAGS),"pclk_uart2" , "pclk_bus_root" , 0 ,13 ), 11 , GFLAGS),"pclk_uart3" , "pclk_bus_root" , 0 ,13 ), 12 , GFLAGS),"pclk_uart4" , "pclk_bus_root" , 0 ,13 ), 13 , GFLAGS),"pclk_uart5" , "pclk_bus_root" , 0 ,13 ), 14 , GFLAGS),"pclk_uart6" , "pclk_bus_root" , 0 ,13 ), 15 , GFLAGS),"pclk_uart7" , "pclk_bus_root" , 0 ,14 ), 0 , GFLAGS),"pclk_uart8" , "pclk_bus_root" , 0 ,14 ), 1 , GFLAGS),"pclk_uart9" , "pclk_bus_root" , 0 ,14 ), 2 , GFLAGS),"pclk_uart10" , "pclk_bus_root" , 0 ,14 ), 3 , GFLAGS),"pclk_uart11" , "pclk_bus_root" , 0 ,14 ), 4 , GFLAGS),"sclk_uart0" , clk_uart_p, 0 ,60 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,14 ), 5 , GFLAGS),"sclk_uart2" , clk_uart_p, 0 ,61 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,14 ), 6 , GFLAGS),"sclk_uart3" , clk_uart_p, 0 ,62 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,14 ), 9 , GFLAGS),"sclk_uart4" , clk_uart_p, 0 ,63 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,14 ), 12 , GFLAGS),"sclk_uart5" , clk_uart_p, 0 ,64 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,14 ), 15 , GFLAGS),"sclk_uart6" , clk_uart_p, 0 ,65 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,15 ), 2 , GFLAGS),"sclk_uart7" , clk_uart_p, 0 ,66 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,15 ), 5 , GFLAGS),"sclk_uart8" , clk_uart_p, 0 ,67 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,15 ), 8 , GFLAGS),"sclk_uart9" , clk_uart_p, 0 ,68 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,15 ), 9 , GFLAGS),"sclk_uart10" , clk_uart_p, 0 ,69 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,15 ), 10 , GFLAGS),"sclk_uart11" , clk_uart_p, 0 ,70 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,15 ), 11 , GFLAGS),"pclk_spi0" , "pclk_bus_root" , 0 ,15 ), 13 , GFLAGS),"pclk_spi1" , "pclk_bus_root" , 0 ,15 ), 14 , GFLAGS),"pclk_spi2" , "pclk_bus_root" , 0 ,15 ), 15 , GFLAGS),"pclk_spi3" , "pclk_bus_root" , 0 ,16 ), 0 , GFLAGS),"pclk_spi4" , "pclk_bus_root" , 0 ,16 ), 1 , GFLAGS),"clk_spi0" , mux_200m_100m_50m_24m_p, 0 ,70 ), 13 , 2 , MFLAGS,16 ), 2 , GFLAGS),"clk_spi1" , mux_200m_100m_50m_24m_p, 0 ,71 ), 0 , 2 , MFLAGS,16 ), 3 , GFLAGS),"clk_spi2" , mux_200m_100m_50m_24m_p, 0 ,71 ), 2 , 2 , MFLAGS,16 ), 4 , GFLAGS),"clk_spi3" , mux_200m_100m_50m_24m_p, 0 ,71 ), 4 , 2 , MFLAGS,16 ), 5 , GFLAGS),"clk_spi4" , mux_200m_100m_50m_24m_p, 0 ,71 ), 6 , 2 , MFLAGS,16 ), 6 , GFLAGS),"pclk_wdt0" , "pclk_bus_root" , 0 ,16 ), 7 , GFLAGS),"tclk_wdt0" , "xin24m" , 0 ,16 ), 8 , GFLAGS),"pclk_pwm1" , "pclk_bus_root" , 0 ,16 ), 10 , GFLAGS),"clk_pwm1" , mux_100m_50m_24m_p, 0 ,71 ), 8 , 2 , MFLAGS,16 ), 11 , GFLAGS),"clk_osc_pwm1" , "xin24m" , 0 ,16 ), 13 , GFLAGS),"clk_rc_pwm1" , "clk_pvtm_clkout" , 0 ,16 ), 15 , GFLAGS),"pclk_bustimer0" , "pclk_bus_root" , 0 ,17 ), 3 , GFLAGS),"pclk_bustimer1" , "pclk_bus_root" , 0 ,17 ), 4 , GFLAGS),"clk_timer0_root" , mux_100m_24m_p, 0 ,71 ), 14 , 1 , MFLAGS,17 ), 5 , GFLAGS),"clk_timer0" , "clk_timer0_root" , 0 ,17 ), 6 , GFLAGS),"clk_timer1" , "clk_timer0_root" , 0 ,17 ), 7 , GFLAGS),"clk_timer2" , "clk_timer0_root" , 0 ,17 ), 8 , GFLAGS),"clk_timer3" , "clk_timer0_root" , 0 ,17 ), 9 , GFLAGS),"clk_timer4" , "clk_timer0_root" , 0 ,17 ), 10 , GFLAGS),"clk_timer5" , "clk_timer0_root" , 0 ,17 ), 11 , GFLAGS),"pclk_mailbox0" , "pclk_bus_root" , 0 ,17 ), 13 , GFLAGS),"pclk_gpio1" , "pclk_bus_root" , 0 ,17 ), 15 , GFLAGS),"dbclk_gpio1" , "xin24m" , 0 ,18 ), 0 , GFLAGS),"pclk_gpio2" , "pclk_bus_root" , 0 ,18 ), 1 , GFLAGS),"dbclk_gpio2" , "xin24m" , 0 ,18 ), 2 , GFLAGS),"pclk_gpio3" , "pclk_bus_root" , 0 ,18 ), 3 , GFLAGS),"dbclk_gpio3" , "xin24m" , 0 ,18 ), 4 , GFLAGS),"pclk_gpio4" , "pclk_bus_root" , 0 ,18 ), 5 , GFLAGS),"dbclk_gpio4" , "xin24m" , 0 ,18 ), 6 , GFLAGS),"aclk_decom" , "aclk_bus_root" , 0 ,18 ), 7 , GFLAGS),"pclk_decom" , "pclk_bus_root" , 0 ,18 ), 8 , GFLAGS),"dclk_decom" , gpll_spll_p, 0 ,72 ), 5 , 1 , MFLAGS, 0 , 5 , DFLAGS,18 ), 9 , GFLAGS),"clk_timer1_root" , mux_100m_24m_p, 0 ,72 ), 6 , 1 , MFLAGS,18 ), 10 , GFLAGS),"clk_timer6" , "clk_timer1_root" , 0 ,18 ), 11 , GFLAGS),"clk_timer7" , mux_100m_24m_lclk0_p, 0 ,72 ), 12 , 2 , MFLAGS, 7 , 5 , DFLAGS,18 ), 12 , GFLAGS),"clk_timer8" , mux_100m_24m_lclk1_p, 0 ,73 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,18 ), 13 , GFLAGS),"clk_timer9" , "clk_timer1_root" , 0 ,18 ), 14 , GFLAGS),"clk_timer10" , "clk_timer1_root" , 0 ,18 ), 15 , GFLAGS),"clk_timer11" , "clk_timer1_root" , 0 ,19 ), 0 , GFLAGS),"aclk_dmac0" , "aclk_bus_root" , 0 ,19 ), 1 , GFLAGS),"aclk_dmac1" , "aclk_bus_root" , 0 ,19 ), 2 , GFLAGS),"aclk_dmac2" , "aclk_bus_root" , 0 ,19 ), 3 , GFLAGS),"aclk_spinlock" , "aclk_bus_root" , 0 ,19 ), 4 , GFLAGS),"hclk_i3c0" , "hclk_bus_root" , 0 ,19 ), 7 , GFLAGS),"hclk_i3c1" , "hclk_bus_root" , 0 ,19 ), 9 , GFLAGS),"hclk_bus_cm0_root" , mux_400m_200m_100m_24m_p, 0 ,73 ), 13 , 2 , MFLAGS,19 ), 10 , GFLAGS),"fclk_bus_cm0_core" , "hclk_bus_cm0_root" , 0 ,19 ), 12 , GFLAGS),"clk_bus_cm0_rtc" , mux_24m_32k_p, 0 ,74 ), 5 , 1 , MFLAGS, 0 , 5 , DFLAGS,19 ), 14 , GFLAGS),"pclk_pmu2" , "pclk_bus_root" , CLK_IS_CRITICAL,19 ), 15 , GFLAGS),"pclk_pwm2" , "pclk_bus_root" , 0 ,20 ), 4 , GFLAGS),"clk_pwm2" , mux_100m_50m_24m_p, 0 ,74 ), 6 , 2 , MFLAGS,20 ), 5 , GFLAGS),"clk_osc_pwm2" , "xin24m" , 0 ,20 ), 7 , GFLAGS),"clk_rc_pwm2" , "clk_pvtm_clkout" , 0 ,20 ), 6 , GFLAGS),"clk_freq_pwm1" , clk_freq_pwm1_p, 0 ,74 ), 8 , 3 , MFLAGS,20 ), 8 , GFLAGS),"clk_counter_pwm1" , clk_counter_pwm1_p, 0 ,74 ), 11 , 3 , MFLAGS,20 ), 9 , GFLAGS),"sai_sclkin_freq" , sai_sclkin_freq_p, 0 ,75 ), 0 , 3 , MFLAGS,20 ), 10 , GFLAGS),"sai_sclkin_counter" , sai_sclkin_freq_p, 0 ,75 ), 3 , 3 , MFLAGS,20 ), 11 , GFLAGS),"clk_i3c0" , gpll_cpll_aupll_spll_p, 0 ,78 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,20 ), 12 , GFLAGS),"clk_i3c1" , gpll_cpll_aupll_spll_p, 0 ,78 ), 12 , 2 , MFLAGS, 7 , 5 , DFLAGS,20 ), 13 , GFLAGS),"pclk_csidphy1" , "pclk_bus_root" , 0 ,40 ), 2 , GFLAGS),/* cci */ "pclk_cci_root" , mux_24m_ccipvtpll_gpll_lpll_p, CLK_IS_CRITICAL,4 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,1 ), 10 , GFLAGS),"aclk_cci_root" , mux_24m_ccipvtpll_gpll_lpll_p, CLK_IS_CRITICAL,4 ), 12 , 2 , MFLAGS, 7 , 5 , DFLAGS,1 ), 11 , GFLAGS),/* center */ "aclk_center_root" , gpll_cpll_spll_aupll_bpll_p, CLK_IS_CRITICAL,168 ), 5 , 3 , MFLAGS,167 ), 9 , 5 , DFLAGS,72 ), 0 , GFLAGS),"aclk_center_low_root" , mux_500m_250m_100m_24m_p, CLK_IS_CRITICAL,168 ), 8 , 2 , MFLAGS,72 ), 1 , GFLAGS),"hclk_center_root" , mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,168 ), 10 , 2 , MFLAGS,72 ), 2 , GFLAGS),"pclk_center_root" , mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,168 ), 12 , 2 , MFLAGS,72 ), 3 , GFLAGS),"aclk_dma2ddr" , "aclk_center_root" , CLK_IGNORE_UNUSED,72 ), 5 , GFLAGS),"aclk_ddr_sharemem" , "aclk_center_low_root" , CLK_IGNORE_UNUSED,72 ), 6 , GFLAGS),"pclk_dma2ddr" , "pclk_center_root" , CLK_IGNORE_UNUSED,72 ), 10 , GFLAGS),"pclk_sharemem" , "pclk_center_root" , CLK_IGNORE_UNUSED,72 ), 11 , GFLAGS),/* ddr */ "pclk_ddr_root" , gpll_cpll_24m_p, CLK_IS_CRITICAL,76 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,21 ), 0 , GFLAGS),"pclk_ddr_mon_ch0" , "pclk_ddr_root" , CLK_IGNORE_UNUSED,21 ), 1 , GFLAGS),"hclk_ddr_root" , gpll_cpll_p, CLK_IGNORE_UNUSED,77 ), 5 , 1 , MFLAGS, 0 , 5 , DFLAGS,22 ), 11 , GFLAGS),"fclk_ddr_cm0_core" , "hclk_ddr_root" , CLK_IS_CRITICAL,22 ), 15 , GFLAGS),"clk_ddr_timer_root" , mux_100m_24m_p, 0 ,77 ), 6 , 1 , MFLAGS,23 ), 3 , GFLAGS),"clk_ddr_timer0" , "clk_ddr_timer_root" , 0 ,23 ), 4 , GFLAGS),"clk_ddr_timer1" , "clk_ddr_timer_root" , 0 ,23 ), 5 , GFLAGS),"tclk_wdt_ddr" , "xin24m" , 0 ,23 ), 6 , GFLAGS),"pclk_wdt" , "pclk_ddr_root" , 0 ,23 ), 7 , GFLAGS),"pclk_timer" , "pclk_ddr_root" , 0 ,23 ), 8 , GFLAGS),"clk_ddr_cm0_rtc" , mux_24m_32k_p, 0 ,77 ), 12 , 1 , MFLAGS, 7 , 5 , DFLAGS,23 ), 10 , GFLAGS),/* gpu */ "clk_gpu_src_pre" , gpll_cpll_aupll_spll_lpll_p, 0 ,165 ), 5 , 3 , MFLAGS, 0 , 5 , DFLAGS,69 ), 1 , GFLAGS),"clk_gpu" , "clk_gpu_src_pre" , 0 ,69 ), 3 , GFLAGS),"pclk_gpu_root" , mux_100m_50m_24m_p, 0 ,166 ), 10 , 2 , MFLAGS,69 ), 8 , GFLAGS),/* npu */ "hclk_rknn_root" , mux_200m_100m_50m_24m_p, 0 ,86 ), 0 , 2 , MFLAGS,31 ), 4 , GFLAGS),"clk_rknn_dsu0" , gpll_cpll_aupll_spll_p, 0 ,86 ), 7 , 2 , MFLAGS, 2 , 5 , DFLAGS,31 ), 5 , GFLAGS),"aclk_rknn0" , "clk_rknn_dsu0" , 0 ,28 ), 9 , GFLAGS),"aclk_rknn1" , "clk_rknn_dsu0" , 0 ,29 ), 0 , GFLAGS),"pclk_nputop_root" , mux_100m_50m_24m_p, 0 ,87 ), 0 , 2 , MFLAGS,31 ), 8 , GFLAGS),"pclk_npu_timer" , "pclk_nputop_root" , 0 ,31 ), 10 , GFLAGS),"clk_nputimer_root" , mux_100m_24m_p, 0 ,87 ), 2 , 1 , MFLAGS,31 ), 11 , GFLAGS),"clk_nputimer0" , "clk_nputimer_root" , 0 ,31 ), 12 , GFLAGS),"clk_nputimer1" , "clk_nputimer_root" , 0 ,31 ), 13 , GFLAGS),"pclk_npu_wdt" , "pclk_nputop_root" , 0 ,31 ), 14 , GFLAGS),"tclk_npu_wdt" , "xin24m" , 0 ,31 ), 15 , GFLAGS),"aclk_rknn_cbuf" , "clk_rknn_dsu0" , 0 ,32 ), 0 , GFLAGS),"hclk_npu_cm0_root" , mux_400m_200m_100m_24m_p, 0 ,87 ), 3 , 2 , MFLAGS,32 ), 5 , GFLAGS),"fclk_npu_cm0_core" , "hclk_npu_cm0_root" , 0 ,32 ), 7 , GFLAGS),"clk_npu_cm0_rtc" , mux_24m_32k_p, 0 ,87 ), 10 , 1 , MFLAGS, 5 , 5 , DFLAGS,32 ), 9 , GFLAGS),"hclk_rknn_cbuf" , "hclk_rknn_root" , 0 ,32 ), 12 , GFLAGS),/* nvm */ "hclk_nvm_root" , mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,88 ), 0 , 2 , MFLAGS,33 ), 0 , GFLAGS),"aclk_nvm_root" , gpll_cpll_p, CLK_IS_CRITICAL,88 ), 7 , 1 , MFLAGS, 2 , 5 , DFLAGS,33 ), 1 , GFLAGS),"sclk_fspi_x2" , gpll_cpll_24m_p, 0 ,89 ), 6 , 2 , MFLAGS, 0 , 6 , DFLAGS,33 ), 6 , GFLAGS),"hclk_fspi" , "hclk_nvm_root" , 0 ,33 ), 7 , GFLAGS),"cclk_src_emmc" , gpll_cpll_24m_p, 0 ,89 ), 14 , 2 , MFLAGS, 8 , 6 , DFLAGS,33 ), 8 , GFLAGS),"hclk_emmc" , "hclk_nvm_root" , 0 ,33 ), 9 , GFLAGS),"aclk_emmc" , "aclk_nvm_root" , 0 ,33 ), 10 , GFLAGS),"bclk_emmc" , mux_200m_100m_50m_24m_p, 0 ,90 ), 0 , 2 , MFLAGS,33 ), 11 , GFLAGS),"tclk_emmc" , "xin24m" , 0 ,33 ), 12 , GFLAGS),/* usb */ "aclk_ufs_root" , gpll_cpll_p, 0 ,115 ), 5 , 1 , MFLAGS, 0 , 5 , DFLAGS,47 ), 0 , GFLAGS),"aclk_usb_root" , gpll_cpll_p, CLK_IS_CRITICAL,115 ), 11 , 1 , MFLAGS, 6 , 5 , DFLAGS,47 ), 1 , GFLAGS),"pclk_usb_root" , mux_100m_50m_24m_p, CLK_IS_CRITICAL,115 ), 12 , 2 , MFLAGS,47 ), 2 , GFLAGS),"aclk_usb3otg0" , "aclk_usb_root" , 0 ,47 ), 5 , GFLAGS),"clk_ref_usb3otg0" , "xin24m" , 0 ,47 ), 6 , GFLAGS),"clk_suspend_usb3otg0" , "xin24m" , 0 ,47 ), 7 , GFLAGS),"aclk_mmu2" , "aclk_usb_root" , 0 ,47 ), 12 , GFLAGS),"aclk_slv_mmu2" , "aclk_usb_root" , 0 ,47 ), 13 , GFLAGS),"aclk_ufs_sys" , "aclk_ufs_root" , 0 ,47 ), 15 , GFLAGS),/* vdec */ "hclk_rkvdec_root" , mux_200m_100m_50m_24m_p, 0 ,110 ), 0 , 2 , MFLAGS,45 ), 0 , GFLAGS),"aclk_rkvdec_root" , gpll_cpll_aupll_spll_p, 0 ,110 ), 7 , 2 , MFLAGS, 2 , 5 , DFLAGS,45 ), 1 , GFLAGS),"aclk_rkvdec_root_bak" , cpll_vpll_lpll_bpll_p, 0 ,110 ), 14 , 2 , MFLAGS, 9 , 5 , DFLAGS,45 ), 2 , GFLAGS),"hclk_rkvdec" , "hclk_rkvdec_root" , 0 ,45 ), 3 , GFLAGS),"clk_rkvdec_hevc_ca" , gpll_cpll_lpll_bpll_p, 0 ,111 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,45 ), 8 , GFLAGS),"clk_rkvdec_core" , "aclk_rkvdec_root" , 0 ,45 ), 9 , GFLAGS),/* venc */ "hclk_vepu0_root" , mux_200m_100m_50m_24m_p, 0 ,124 ), 0 , 2 , MFLAGS,51 ), 0 , GFLAGS),"aclk_vepu0_root" , gpll_cpll_p, 0 ,124 ), 7 , 1 , MFLAGS, 2 , 5 , DFLAGS,51 ), 1 , GFLAGS),"clk_vepu0_core" , gpll_cpll_spll_lpll_bpll_p, 0 ,124 ), 13 , 3 , MFLAGS, 8 , 5 , DFLAGS,51 ), 6 , GFLAGS),"hclk_vepu0" , "hclk_vepu0_root" , 0 ,51 ), 4 , GFLAGS),"aclk_vepu0" , "aclk_vepu0_root" , 0 ,51 ), 5 , GFLAGS),/* vi */ "aclk_vi_root" , gpll_spll_isppvtpll_bpll_lpll_p, CLK_IS_CRITICAL,128 ), 5 , 3 , MFLAGS, 0 , 5 , DFLAGS,53 ), 0 , GFLAGS),"aclk_vi_root_inter" , "aclk_vi_root" , 0 ,130 ), 10 , 3 , DFLAGS,54 ), 13 , GFLAGS),"hclk_vi_root" , hclk_vi_root_p, CLK_IS_CRITICAL,128 ), 8 , 2 , MFLAGS,53 ), 1 , GFLAGS),"pclk_vi_root" , mux_100m_50m_24m_p, 0 ,128 ), 10 , 2 , MFLAGS,53 ), 2 , GFLAGS),"dclk_vicap" , gpll_cpll_p, 0 ,129 ), 5 , 1 , MFLAGS, 0 , 5 , DFLAGS,53 ), 6 , GFLAGS),"aclk_vicap" , "aclk_vi_root" , 0 ,53 ), 7 , GFLAGS),"hclk_vicap" , "hclk_vi_root" , 0 ,53 ), 8 , GFLAGS),"clk_isp_core" , gpll_spll_isppvtpll_bpll_lpll_p, 0 ,129 ), 11 , 3 , MFLAGS, 6 , 5 , DFLAGS,53 ), 9 , GFLAGS),"clk_isp_core_marvin" , "clk_isp_core" , 0 ,53 ), 10 , GFLAGS),"clk_isp_core_vicap" , "clk_isp_core" , 0 ,53 ), 11 , GFLAGS),"aclk_isp" , "aclk_vi_root" , 0 ,53 ), 12 , GFLAGS),"hclk_isp" , "hclk_vi_root" , 0 ,53 ), 13 , GFLAGS),"aclk_vpss" , "aclk_vi_root" , 0 ,53 ), 15 , GFLAGS),"hclk_vpss" , "hclk_vi_root" , 0 ,54 ), 0 , GFLAGS),"clk_core_vpss" , "clk_isp_core" , 0 ,54 ), 1 , GFLAGS),"pclk_csi_host_0" , "pclk_vi_root" , 0 ,54 ), 4 , GFLAGS),"pclk_csi_host_1" , "pclk_vi_root" , 0 ,54 ), 5 , GFLAGS),"pclk_csi_host_2" , "pclk_vi_root" , 0 ,54 ), 6 , GFLAGS),"pclk_csi_host_3" , "pclk_vi_root" , 0 ,54 ), 7 , GFLAGS),"pclk_csi_host_4" , "pclk_vi_root" , 0 ,54 ), 8 , GFLAGS),"iclk_csihost01" , mux_400m_200m_100m_24m_p, 0 ,130 ), 7 , 2 , MFLAGS,54 ), 10 , GFLAGS),"iclk_csihost0" , "iclk_csihost01" , 0 ,54 ), 11 , GFLAGS),"aclk_vop_root" , gpll_cpll_aupll_spll_lpll_p, CLK_IS_CRITICAL,144 ), 5 , 3 , MFLAGS, 0 , 5 , DFLAGS,61 ), 0 , GFLAGS),"hclk_vop_root" , mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,144 ), 10 , 2 , MFLAGS,61 ), 2 , GFLAGS),"pclk_vop_root" , mux_100m_50m_24m_p, 0 ,144 ), 12 , 2 , MFLAGS,61 ), 3 , GFLAGS),"hclk_vop" , "hclk_vop_root" , 0 ,61 ), 8 , GFLAGS),"aclk_vop" , "aclk_vop_root" , 0 ,61 ), 9 , GFLAGS),"dclk_vp0_src" , gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT,145 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,61 ), 10 , GFLAGS),"dclk_vp1_src" , gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT,146 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,61 ), 11 , GFLAGS),"dclk_vp2_src" , gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT,147 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,61 ), 12 , GFLAGS),"dclk_vp0" , dclk_vp0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,147 ), 11 , 1 , MFLAGS,61 ), 13 , GFLAGS),"dclk_vp1" , dclk_vp1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,147 ), 12 , 1 , MFLAGS,62 ), 0 , GFLAGS),"dclk_vp2" , dclk_vp2_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,147 ), 13 , 1 , MFLAGS,62 ), 1 , GFLAGS),/* vo0 */ "aclk_vo0_root" , gpll_cpll_lpll_bpll_p, 0 ,149 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,63 ), 0 , GFLAGS),"hclk_vo0_root" , mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,149 ), 7 , 2 , MFLAGS,63 ), 1 , GFLAGS),"pclk_vo0_root" , mux_150m_100m_50m_24m_p, 0 ,149 ), 11 , 2 , MFLAGS,63 ), 3 , GFLAGS),"aclk_hdcp0" , "aclk_vo0_root" , 0 ,63 ), 12 , GFLAGS),"hclk_hdcp0" , "hclk_vo0_root" , 0 ,63 ), 13 , GFLAGS),"pclk_hdcp0" , "pclk_vo0_root" , 0 ,63 ), 14 , GFLAGS),"clk_trng0_skp" , "aclk_hdcp0" , 0 ,64 ), 4 , GFLAGS),"pclk_dsihost0" , "pclk_vo0_root" , 0 ,64 ), 5 , GFLAGS),"clk_dsihost0" , gpll_cpll_spll_vpll_bpll_lpll_p, 0 ,151 ), 7 , 3 , MFLAGS, 0 , 7 , DFLAGS,64 ), 6 , GFLAGS),"pclk_hdmitx0" , "pclk_vo0_root" , 0 ,64 ), 7 , GFLAGS),"clk_hdmitx0_earc" , gpll_cpll_p, 0 ,151 ), 15 , 1 , MFLAGS, 10 , 5 , DFLAGS,64 ), 8 , GFLAGS),"clk_hdmitx0_ref" , "aclk_vo0_root" , 0 ,64 ), 9 , GFLAGS),"pclk_edp0" , "pclk_vo0_root" , 0 ,64 ), 13 , GFLAGS),"clk_edp0_24m" , "xin24m" , 0 ,64 ), 14 , GFLAGS),"clk_edp0_200m" , mux_200m_100m_50m_24m_p, 0 ,152 ), 1 , 2 , MFLAGS,64 ), 15 , GFLAGS),"mclk_sai5_8ch_src" , audio_frac_int_p, 0 ,154 ), 10 , 3 , MFLAGS, 2 , 8 , DFLAGS,65 ), 3 , GFLAGS),"mclk_sai5_8ch" , mclk_sai5_8ch_p, CLK_SET_RATE_PARENT,154 ), 13 , 1 , MFLAGS,65 ), 4 , GFLAGS),"hclk_sai5_8ch" , "hclk_vo0_root" , 0 ,65 ), 5 , GFLAGS),"mclk_sai6_8ch_src" , audio_frac_int_p, 0 ,155 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,65 ), 7 , GFLAGS),"mclk_sai6_8ch" , mclk_sai6_8ch_p, CLK_SET_RATE_PARENT,155 ), 11 , 1 , MFLAGS,65 ), 8 , GFLAGS),"hclk_sai6_8ch" , "hclk_vo0_root" , 0 ,65 ), 9 , GFLAGS),"hclk_spdif_tx2" , "hclk_vo0_root" , 0 ,65 ), 10 , GFLAGS),"mclk_spdif_tx2" , audio_frac_int_p, 0 ,156 ), 5 , 3 , MFLAGS, 0 , 5 , DFLAGS,65 ), 13 , GFLAGS),"hclk_spdif_rx2" , "hclk_vo0_root" , 0 ,65 ), 14 , GFLAGS),"mclk_spdif_rx2" , gpll_cpll_aupll_p, 0 ,156 ), 13 , 2 , MFLAGS, 8 , 5 , DFLAGS,65 ), 15 , GFLAGS),/* vo1 */ "aclk_vo1_root" , gpll_cpll_lpll_bpll_p, 0 ,158 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,67 ), 1 , GFLAGS),"hclk_vo1_root" , mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,158 ), 7 , 2 , MFLAGS,67 ), 2 , GFLAGS),"pclk_vo1_root" , mux_100m_50m_24m_p, 0 ,158 ), 9 , 2 , MFLAGS,67 ), 3 , GFLAGS),"mclk_sai8_8ch_src" , audio_frac_int_p, 0 ,157 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,66 ), 1 , GFLAGS),"mclk_sai8_8ch" , mclk_sai8_8ch_p, CLK_SET_RATE_PARENT,157 ), 11 , 1 , MFLAGS,66 ), 2 , GFLAGS),"hclk_sai8_8ch" , "hclk_vo1_root" , 0 ,66 ), 0 , GFLAGS),"mclk_sai7_8ch_src" , audio_frac_int_p, 0 ,159 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,67 ), 8 , GFLAGS),"mclk_sai7_8ch" , mclk_sai7_8ch_p, CLK_SET_RATE_PARENT,159 ), 11 , 1 , MFLAGS,67 ), 9 , GFLAGS),"hclk_sai7_8ch" , "hclk_vo1_root" , 0 ,67 ), 10 , GFLAGS),"hclk_spdif_tx3" , "hclk_vo1_root" , 0 ,67 ), 11 , GFLAGS),"hclk_spdif_tx4" , "hclk_vo1_root" , 0 ,67 ), 12 , GFLAGS),"hclk_spdif_tx5" , "hclk_vo1_root" , 0 ,67 ), 13 , GFLAGS),"mclk_spdif_tx3" , audio_frac_int_p, 0 ,160 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,67 ), 14 , GFLAGS),"clk_aux16mhz_0" , "gpll" , 0 ,161 ), 0 , 8 , DFLAGS,67 ), 15 , GFLAGS),"aclk_dp0" , "aclk_vo1_root" , 0 ,68 ), 0 , GFLAGS),"pclk_dp0" , "pclk_vo1_root" , 0 ,68 ), 1 , GFLAGS),"aclk_hdcp1" , "aclk_vo1_root" , 0 ,68 ), 4 , GFLAGS),"hclk_hdcp1" , "hclk_vo1_root" , 0 ,68 ), 5 , GFLAGS),"pclk_hdcp1" , "pclk_vo1_root" , 0 ,68 ), 6 , GFLAGS),"clk_trng1_skp" , "aclk_hdcp1" , 0 ,68 ), 7 , GFLAGS),"hclk_sai9_8ch" , "hclk_vo1_root" , 0 ,68 ), 9 , GFLAGS),"mclk_sai9_8ch_src" , audio_frac_int_p, 0 ,162 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,68 ), 10 , GFLAGS),"mclk_sai9_8ch" , mclk_sai9_8ch_p, CLK_SET_RATE_PARENT,162 ), 11 , 1 , MFLAGS,68 ), 11 , GFLAGS),"mclk_spdif_tx4" , audio_frac_int_p, 0 ,163 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,68 ), 12 , GFLAGS),"mclk_spdif_tx5" , audio_frac_int_p, 0 ,164 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,68 ), 13 , GFLAGS),/* vpu */ "aclk_vpu_root" , gpll_spll_cpll_bpll_lpll_p, CLK_IS_CRITICAL,118 ), 5 , 3 , MFLAGS, 0 , 5 , DFLAGS,49 ), 0 , GFLAGS),"aclk_vpu_mid_root" , mux_600m_400m_300m_24m_p, 0 ,118 ), 8 , 2 , MFLAGS,49 ), 1 , GFLAGS),"hclk_vpu_root" , mux_200m_100m_50m_24m_p, 0 ,118 ), 10 , 2 , MFLAGS,49 ), 2 , GFLAGS),"aclk_jpeg_root" , gpll_cpll_aupll_spll_p, 0 ,119 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,49 ), 3 , GFLAGS),"aclk_vpu_low_root" , mux_400m_200m_100m_24m_p, 0 ,119 ), 7 , 2 , MFLAGS,49 ), 4 , GFLAGS),"hclk_rga2e_0" , "hclk_vpu_root" , 0 ,49 ), 13 , GFLAGS),"aclk_rga2e_0" , "aclk_vpu_root" , 0 ,49 ), 14 , GFLAGS),"clk_core_rga2e_0" , gpll_spll_cpll_bpll_lpll_p, 0 ,120 ), 5 , 3 , MFLAGS, 0 , 5 , DFLAGS,49 ), 15 , GFLAGS),"aclk_jpeg" , "aclk_jpeg_root" , 0 ,50 ), 0 , GFLAGS),"hclk_jpeg" , "hclk_vpu_root" , 0 ,50 ), 1 , GFLAGS),"hclk_vdpp" , "hclk_vpu_root" , 0 ,50 ), 2 , GFLAGS),"aclk_vdpp" , "aclk_vpu_mid_root" , 0 ,50 ), 3 , GFLAGS),"clk_core_vdpp" , gpll_cpll_p, 0 ,120 ), 13 , 1 , MFLAGS, 8 , 5 , DFLAGS,50 ), 4 , GFLAGS),"hclk_rga2e_1" , "hclk_vpu_root" , 0 ,50 ), 5 , GFLAGS),"aclk_rga2e_1" , "aclk_vpu_root" , 0 ,50 ), 6 , GFLAGS),"clk_core_rga2e_1" , gpll_spll_cpll_bpll_lpll_p, 0 ,121 ), 5 , 3 , MFLAGS, 0 , 5 , DFLAGS,50 ), 7 , GFLAGS),0 , "dclk_ebc_frac_src_p" , gpll_cpll_vpll_aupll_24m_p, 0 ,123 ), 0 , 3 , MFLAGS),"dclk_ebc_frac_src" , "dclk_ebc_frac_src_p" , 0 ,122 ), 0 ,50 ), 9 , GFLAGS),"aclk_ebc" , "aclk_vpu_low_root" , 0 ,50 ), 11 , GFLAGS),"hclk_ebc" , "hclk_vpu_root" , 0 ,50 ), 10 , GFLAGS),"dclk_ebc" , dclk_ebc_p, CLK_SET_RATE_NO_REPARENT,123 ), 12 , 3 , MFLAGS, 3 , 9 , DFLAGS,50 ), 12 , GFLAGS),/* vepu */ "hclk_vepu1_root" , mux_200m_100m_50m_24m_p, 0 ,178 ), 0 , 2 , MFLAGS,78 ), 0 , GFLAGS),"aclk_vepu1_root" , gpll_cpll_p, 0 ,180 ), 5 , 1 , MFLAGS, 0 , 5 , DFLAGS,79 ), 0 , GFLAGS),"hclk_vepu1" , "hclk_vepu1_root" , 0 ,79 ), 3 , GFLAGS),"aclk_vepu1" , "aclk_vepu1_root" , 0 ,79 ), 4 , GFLAGS),"clk_vepu1_core" , gpll_cpll_spll_lpll_bpll_p, 0 ,180 ), 11 , 3 , MFLAGS, 6 , 5 , DFLAGS,79 ), 5 , GFLAGS),/* php */ "pclk_php_root" , mux_100m_50m_24m_p, 0 ,92 ), 0 , 2 , MFLAGS,34 ), 0 , GFLAGS),"aclk_php_root" , gpll_cpll_p, 0 ,92 ), 9 , 1 , MFLAGS, 4 , 5 , DFLAGS,34 ), 7 , GFLAGS),"pclk_pcie0" , "pclk_php_root" , 0 ,34 ), 13 , GFLAGS),"clk_pcie0_aux" , "xin24m" , 0 ,34 ), 14 , GFLAGS),"aclk_pcie0_mst" , "aclk_php_root" , 0 ,34 ), 15 , GFLAGS),"aclk_pcie0_slv" , "aclk_php_root" , 0 ,35 ), 0 , GFLAGS),"aclk_pcie0_dbi" , "aclk_php_root" , 0 ,35 ), 1 , GFLAGS),"aclk_usb3otg1" , "aclk_php_root" , 0 ,35 ), 3 , GFLAGS),"clk_ref_usb3otg1" , "xin24m" , 0 ,35 ), 4 , GFLAGS),"clk_suspend_usb3otg1" , "xin24m" , 0 ,35 ), 5 , GFLAGS),"aclk_mmu0" , "aclk_php_root" , 0 ,35 ), 11 , GFLAGS),"aclk_slv_mmu0" , "aclk_php_root" , 0 ,35 ), 13 , GFLAGS),"aclk_mmu1" , "aclk_php_root" , 0 ,35 ), 14 , GFLAGS),"aclk_slv_mmu1" , "aclk_php_root" , 0 ,36 ), 0 , GFLAGS),"pclk_pcie1" , "pclk_php_root" , 0 ,36 ), 7 , GFLAGS),"clk_pcie1_aux" , "xin24m" , 0 ,36 ), 8 , GFLAGS),"aclk_pcie1_mst" , "aclk_php_root" , 0 ,36 ), 9 , GFLAGS),"aclk_pcie1_slv" , "aclk_php_root" , 0 ,36 ), 10 , GFLAGS),"aclk_pcie1_dbi" , "aclk_php_root" , 0 ,36 ), 11 , GFLAGS),"clk_rxoob0" , gpll_cpll_p, 0 ,93 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,37 ), 0 , GFLAGS),"clk_rxoob1" , gpll_cpll_p, 0 ,93 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,37 ), 1 , GFLAGS),"clk_pmalive0" , "xin24m" , CLK_IS_CRITICAL,37 ), 2 , GFLAGS),"clk_pmalive1" , "xin24m" , CLK_IS_CRITICAL,37 ), 3 , GFLAGS),"aclk_sata0" , "aclk_php_root" , 0 ,37 ), 4 , GFLAGS),"aclk_sata1" , "aclk_php_root" , 0 ,37 ), 5 , GFLAGS),/* audio */ "hclk_audio_root" , mux_200m_100m_50m_24m_p, 0 ,42 ), 0 , 2 , MFLAGS,7 ), 1 , GFLAGS),"hclk_asrc_2ch_0" , "hclk_audio_root" , 0 ,7 ), 3 , GFLAGS),"hclk_asrc_2ch_1" , "hclk_audio_root" , 0 ,7 ), 4 , GFLAGS),"hclk_asrc_4ch_0" , "hclk_audio_root" , 0 ,7 ), 5 , GFLAGS),"hclk_asrc_4ch_1" , "hclk_audio_root" , 0 ,7 ), 6 , GFLAGS),"clk_asrc_2ch_0" , gpll_cpll_aupll_p, 0 ,42 ), 7 , 2 , MFLAGS, 2 , 5 , DFLAGS,7 ), 7 , GFLAGS),"clk_asrc_2ch_1" , gpll_cpll_aupll_p, 0 ,42 ), 14 , 2 , MFLAGS, 9 , 5 , DFLAGS,7 ), 8 , GFLAGS),"clk_asrc_4ch_0" , gpll_cpll_aupll_p, 0 ,43 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,7 ), 9 , GFLAGS),"clk_asrc_4ch_1" , gpll_cpll_aupll_p, 0 ,43 ), 12 , 2 , MFLAGS, 7 , 5 , DFLAGS,7 ), 10 , GFLAGS),"mclk_sai0_8ch_src" , audio_frac_int_p, 0 ,44 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,7 ), 11 , GFLAGS),"mclk_sai0_8ch" , mclk_sai0_8ch_p, CLK_SET_RATE_PARENT,44 ), 11 , 2 , MFLAGS,7 ), 12 , GFLAGS),"hclk_sai0_8ch" , "hclk_audio_root" , 0 ,7 ), 13 , GFLAGS),"hclk_spdif_rx0" , "hclk_audio_root" , 0 ,7 ), 14 , GFLAGS),"mclk_spdif_rx0" , gpll_cpll_aupll_p, 0 ,45 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,7 ), 15 , GFLAGS),"hclk_spdif_rx1" , "hclk_audio_root" , 0 ,8 ), 0 , GFLAGS),"mclk_spdif_rx1" , gpll_cpll_aupll_p, 0 ,45 ), 12 , 2 , MFLAGS, 7 , 5 , DFLAGS,8 ), 1 , GFLAGS),"mclk_sai1_8ch_src" , audio_frac_int_p, 0 ,46 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,8 ), 4 , GFLAGS),"mclk_sai1_8ch" , mclk_sai1_8ch_p, CLK_SET_RATE_PARENT,46 ), 11 , 1 , MFLAGS,8 ), 5 , GFLAGS),"hclk_sai1_8ch" , "hclk_audio_root" , 0 ,8 ), 6 , GFLAGS),"mclk_sai2_2ch_src" , audio_frac_int_p, 0 ,47 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,8 ), 7 , GFLAGS),"mclk_sai2_2ch" , mclk_sai2_2ch_p, CLK_SET_RATE_PARENT,47 ), 11 , 2 , MFLAGS,8 ), 8 , GFLAGS),"hclk_sai2_2ch" , "hclk_audio_root" , 0 ,8 ), 10 , GFLAGS),"mclk_sai3_2ch_src" , audio_frac_int_p, 0 ,48 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,8 ), 11 , GFLAGS),"mclk_sai3_2ch" , mclk_sai3_2ch_p, CLK_SET_RATE_PARENT,48 ), 11 , 2 , MFLAGS,8 ), 12 , GFLAGS),"hclk_sai3_2ch" , "hclk_audio_root" , 0 ,8 ), 14 , GFLAGS),"mclk_sai4_2ch_src" , audio_frac_int_p, 0 ,49 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,8 ), 15 , GFLAGS),"mclk_sai4_2ch" , mclk_sai4_2ch_p, CLK_SET_RATE_PARENT,49 ), 11 , 2 , MFLAGS,9 ), 0 , GFLAGS),"hclk_sai4_2ch" , "hclk_audio_root" , 0 ,9 ), 2 , GFLAGS),"hclk_acdcdig_dsm" , "hclk_audio_root" , 0 ,9 ), 3 , GFLAGS),"mclk_acdcdig_dsm" , "mclk_sai4_2ch" , 0 ,9 ), 4 , GFLAGS),"clk_pdm1" , audio_frac_int_p, 0 ,50 ), 9 , 3 , MFLAGS, 0 , 9 , DFLAGS,9 ), 5 , GFLAGS),"hclk_pdm1" , "hclk_audio_root" , 0 ,9 ), 7 , GFLAGS),"clk_pdm1_out" , "clk_pdm1" , 0 ,3 ), 5 , GFLAGS),"mclk_pdm1" , audio_frac_int_p, 0 ,51 ), 5 , 3 , MFLAGS, 0 , 5 , DFLAGS,9 ), 8 , GFLAGS),"hclk_spdif_tx0" , "hclk_audio_root" , 0 ,9 ), 9 , GFLAGS),"mclk_spdif_tx0" , audio_frac_int_p, 0 ,52 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,9 ), 10 , GFLAGS),"hclk_spdif_tx1" , "hclk_audio_root" , 0 ,9 ), 11 , GFLAGS),"mclk_spdif_tx1" , audio_frac_int_p, 0 ,53 ), 8 , 3 , MFLAGS, 0 , 8 , DFLAGS,9 ), 12 , GFLAGS),"clk_sai1_mclkout" , "mclk_sai1_8ch" , 0 ,9 ), 13 , GFLAGS),"clk_sai2_mclkout" , "mclk_sai2_2ch" , 0 ,9 ), 14 , GFLAGS),"clk_sai3_mclkout" , "mclk_sai3_2ch" , 0 ,9 ), 15 , GFLAGS),"clk_sai4_mclkout" , "mclk_sai4_2ch" , 0 ,10 ), 0 , GFLAGS),"clk_sai0_mclkout" , "mclk_sai0_8ch" , 0 ,10 ), 1 , GFLAGS),"mclk_sai0_to_io" , "clk_sai0_mclkout" ,0 , RK3576_VCCIO_IOC_MISC_CON0, 0 , GFLAGS, grf_type_ioc),"mclk_sai1_to_io" , "clk_sai1_mclkout" ,0 , RK3576_VCCIO_IOC_MISC_CON0, 1 , GFLAGS, grf_type_ioc),"mclk_sai2_to_io" , "clk_sai2_mclkout" ,0 , RK3576_VCCIO_IOC_MISC_CON0, 2 , GFLAGS, grf_type_ioc),"mclk_sai3_to_io" , "clk_sai3_mclkout" ,0 , RK3576_VCCIO_IOC_MISC_CON0, 3 , GFLAGS, grf_type_ioc),/* sdgmac */ "hclk_sdgmac_root" , mux_200m_100m_50m_24m_p, 0 ,103 ), 0 , 2 , MFLAGS,42 ), 0 , GFLAGS),"aclk_sdgmac_root" , gpll_cpll_p, CLK_IS_CRITICAL,103 ), 7 , 1 , MFLAGS, 2 , 5 , DFLAGS,42 ), 1 , GFLAGS),"pclk_sdgmac_root" , mux_100m_50m_24m_p, 0 ,103 ), 8 , 2 , MFLAGS,42 ), 2 , GFLAGS),"aclk_gmac0" , "aclk_sdgmac_root" , 0 ,42 ), 7 , GFLAGS),"aclk_gmac1" , "aclk_sdgmac_root" , 0 ,42 ), 8 , GFLAGS),"pclk_gmac0" , "pclk_sdgmac_root" , 0 ,42 ), 9 , GFLAGS),"pclk_gmac1" , "pclk_sdgmac_root" , 0 ,42 ), 10 , GFLAGS),"cclk_src_sdio" , gpll_cpll_24m_p, 0 ,104 ), 6 , 2 , MFLAGS, 0 , 6 , DFLAGS,42 ), 11 , GFLAGS),"hclk_sdio" , "hclk_sdgmac_root" , 0 ,42 ), 12 , GFLAGS),"clk_gmac1_ptp_ref_src" , clk_gmac1_ptp_ref_src_p, 0 104 ), 13 , 2 , MFLAGS, 8 , 5 , DFLAGS,42 ), 15 , GFLAGS),"clk_gmac0_ptp_ref_src" , clk_gmac0_ptp_ref_src_p, 0 105 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,43 ), 0 , GFLAGS),"clk_gmac1_ptp_ref" , "clk_gmac1_ptp_ref_src" , 0 ,42 ), 13 , GFLAGS),"clk_gmac0_ptp_ref" , "clk_gmac0_ptp_ref_src" , 0 ,42 ), 14 , GFLAGS),"cclk_src_sdmmc0" , gpll_cpll_24m_p, 0 ,105 ), 13 , 2 , MFLAGS, 7 , 6 , DFLAGS,43 ), 1 , GFLAGS),"hclk_sdmmc0" , "hclk_sdgmac_root" , 0 ,43 ), 2 , GFLAGS),"sclk_fspi1_x2" , gpll_cpll_24m_p, 0 ,106 ), 6 , 2 , MFLAGS, 0 , 6 , DFLAGS,43 ), 3 , GFLAGS),"hclk_fspi1" , "hclk_sdgmac_root" , 0 ,43 ), 4 , GFLAGS),"aclk_dsmc_root" , gpll_cpll_p, CLK_IS_CRITICAL,106 ), 13 , 1 , MFLAGS, 8 , 5 , DFLAGS,43 ), 5 , GFLAGS),"aclk_dsmc" , "aclk_dsmc_root" , 0 ,43 ), 7 , GFLAGS),"pclk_dsmc" , "pclk_sdgmac_root" , 0 ,43 ), 8 , GFLAGS),"clk_dsmc_sys" , gpll_cpll_p, 0 ,107 ), 5 , 1 , MFLAGS, 0 , 5 , DFLAGS,43 ), 9 , GFLAGS),"hclk_hsgpio" , "hclk_sdgmac_root" , 0 ,43 ), 10 , GFLAGS),"clk_hsgpio_tx" , gpll_cpll_24m_p, 0 ,107 ), 11 , 2 , MFLAGS, 6 , 5 , DFLAGS,43 ), 11 , GFLAGS),"clk_hsgpio_rx" , gpll_cpll_24m_p, 0 ,108 ), 5 , 2 , MFLAGS, 0 , 5 , DFLAGS,43 ), 12 , GFLAGS),"aclk_hsgpio" , "aclk_sdgmac_root" , 0 ,43 ), 13 , GFLAGS),/* phpphy */ "pclk_phpphy_root" , "pclk_bus_root" , CLK_IS_CRITICAL,0 ), 2 , GFLAGS),"pclk_pcie2_combophy0" , "pclk_phpphy_root" , 0 ,0 ), 5 , GFLAGS),"pclk_pcie2_combophy1" , "pclk_phpphy_root" , 0 ,0 ), 7 , GFLAGS),"clk_pcie_100m_src" , "ppll" , 0 ,0 ), 2 , 5 , DFLAGS,1 ), 1 , GFLAGS),"clk_pcie_100m_nduty_src" , "ppll" , 0 ,0 ), 7 , 5 , DFLAGS,1 ), 2 , GFLAGS),"clk_ref_pcie0_phy" , clk_ref_pcie0_phy_p, 0 ,0 ), 12 , 2 , MFLAGS,1 ), 5 , GFLAGS),"clk_ref_pcie1_phy" , clk_ref_pcie0_phy_p, 0 ,0 ), 14 , 2 , MFLAGS,1 ), 8 , GFLAGS),"clk_ref_mphy_26m" , "ppll" , CLK_IS_CRITICAL,1 ), 0 , 8 , DFLAGS,1 ), 9 , GFLAGS),/* pmu */ "clk_200m_pmu_src" , "clk_gpll_div6" , 0 ,3 ), 2 , GFLAGS),"clk_100m_pmu_src" , "cpll" , 0 ,4 ), 4 , 5 , DFLAGS,3 ), 3 , GFLAGS),"clk_50m_pmu_src" , "clk_100m_pmu_src" , 0 , 1 , 2 ,3 ), 4 , GFLAGS),"hclk_pmu1_root" , mux_pmu200m_pmu100m_pmu50m_24m_p, CLK_IS_CRITICAL,4 ), 0 , 2 , MFLAGS,3 ), 0 , GFLAGS),"hclk_pmu_cm0_root" , mux_pmu200m_pmu100m_pmu50m_24m_p, 0 ,4 ), 2 , 2 , MFLAGS,3 ), 1 , GFLAGS),"pclk_pmu0_root" , mux_pmu100m_pmu50m_24m_p, 0 ,20 ), 0 , 2 , MFLAGS,7 ), 0 , GFLAGS),"pclk_pmu0" , "pclk_pmu0_root" , CLK_IS_CRITICAL,7 ), 3 , GFLAGS),"pclk_pmu1_root" , "pclk_pmu0_root" , CLK_IS_CRITICAL,7 ), 9 , GFLAGS),"pclk_pmu1" , "pclk_pmu1_root" , CLK_IS_CRITICAL,3 ), 15 , GFLAGS),"clk_pmu1" , "xin24m" , CLK_IS_CRITICAL,4 ), 2 , GFLAGS),"pclk_pmuphy_root" , "pclk_pmu1_root" , CLK_IS_CRITICAL,5 ), 0 , GFLAGS),"pclk_hdptx_apb" , "pclk_pmuphy_root" , 0 ,0 ), 1 , GFLAGS),"pclk_mipi_dcphy" , "pclk_pmuphy_root" , 0 ,0 ), 2 , GFLAGS),"pclk_csidphy" , "pclk_pmuphy_root" , 0 ,0 ), 8 , GFLAGS),"pclk_usbdpphy" , "pclk_pmuphy_root" , 0 ,0 ), 12 , GFLAGS),"clk_pmuphy_ref_src" , "cpll" , 0 ,0 ), 0 , 5 , DFLAGS,0 ), 13 , GFLAGS),"clk_usbdp_combo_phy_immortal" , "xin24m" , 0 ,0 ), 15 , GFLAGS),"clk_hdmitxhdp" , "xin24m" , 0 ,1 ), 13 , GFLAGS),"pclk_mphy" , "pclk_pmuphy_root" , 0 ,2 ), 0 , GFLAGS),"clk_ref_osc_mphy" , clk_ref_osc_mphy_p, 0 ,3 ), 0 , 2 , MFLAGS),"clk_ref_ufs_clkout" , "clk_ref_osc_mphy" , 0 ,2 ), 5 , GFLAGS),"fclk_pmu_cm0_core" , "hclk_pmu_cm0_root" , 0 ,3 ), 12 , GFLAGS),"clk_pmu_cm0_rtc" , mux_24m_32k_p, 0 ,4 ), 14 , 1 , MFLAGS, 9 , 5 , DFLAGS,3 ), 14 , GFLAGS),"pclk_pmu1wdt" , "pclk_pmu1_root" , 0 ,4 ), 5 , GFLAGS),"tclk_pmu1wdt" , mux_24m_32k_p, 0 ,4 ), 15 , 1 , MFLAGS,4 ), 6 , GFLAGS),"pclk_pmutimer" , "pclk_pmu1_root" , 0 ,4 ), 7 , GFLAGS),"clk_pmutimer_root" , mux_pmu100m_24m_32k_p, 0 ,5 ), 0 , 2 , MFLAGS,4 ), 8 , GFLAGS),"clk_pmutimer0" , "clk_pmutimer_root" , 0 ,4 ), 9 , GFLAGS),"clk_pmutimer1" , "clk_pmutimer_root" , 0 ,4 ), 10 , GFLAGS),"pclk_pmu1pwm" , "pclk_pmu1_root" , 0 ,4 ), 11 , GFLAGS),"clk_pmu1pwm" , mux_pmu100m_pmu50m_24m_p, 0 ,5 ), 2 , 2 , MFLAGS,4 ), 12 , GFLAGS),"clk_pmu1pwm_osc" , "xin24m" , 0 ,4 ), 13 , GFLAGS),"pclk_i2c0" , "pclk_pmu1_root" , 0 ,5 ), 1 , GFLAGS),"clk_i2c0" , mux_pmu200m_pmu100m_pmu50m_24m_p, 0 ,6 ), 7 , 2 , MFLAGS,5 ), 2 , GFLAGS),"sclk_uart1" , uart1_p, 0 ,8 ), 0 , 1 , MFLAGS,5 ), 5 , GFLAGS),"pclk_uart1" , "pclk_pmu1_root" , 0 ,5 ), 6 , GFLAGS),"clk_pdm0" , "clk_pdm0_src_top" , 0 ,5 ), 13 , GFLAGS),"hclk_pdm0" , "hclk_pmu1_root" , 0 ,5 ), 15 , GFLAGS),"mclk_pdm0" , "mclk_pdm0_src_top" , 0 ,6 ), 0 , GFLAGS),"hclk_vad" , "hclk_pmu1_root" , 0 ,6 ), 1 , GFLAGS),"clk_pdm0_out" , "clk_pdm0" , 0 ,6 ), 8 , GFLAGS),"clk_hptimer_src" , cpll_24m_p, CLK_IS_CRITICAL,11 ), 6 , 1 , MFLAGS, 1 , 5 , DFLAGS,6 ), 10 , GFLAGS),"pclk_gpio0" , "pclk_pmu0_root" , 0 ,7 ), 6 , GFLAGS),"dbclk_gpio0" , mux_24m_32k_p, 0 ,20 ), 2 , 1 , MFLAGS,7 ), 7 , GFLAGS),"clk_osc0_pmu1" , "xin24m" , CLK_IS_CRITICAL,7 ), 8 , GFLAGS),"clk_pmu1pwm_rc" , "clk_pvtm_clkout" , 0 ,5 ), 7 , GFLAGS),/* phy ref */ "clk_phy_ref_src" , clk_phy_ref_src_p, 0 ,4 , 1 , MFLAGS, grf_type_pmu0),"clk_usbphy_ref_src" , clk_usbphy_ref_src_p, 0 ,2 , 1 , MFLAGS, grf_type_pmu0),"clk_cpll_ref_src" , clk_cpll_ref_src_p, 0 ,1 , 1 , MFLAGS, grf_type_pmu0),"clk_aupll_ref_src" , clk_aupll_ref_src_p, 0 ,0 , 1 , MFLAGS, grf_type_pmu0),/* secure ns */ "aclk_secure_ns" , mux_350m_175m_116m_24m_p, CLK_IS_CRITICAL,0 ), 0 , 2 , MFLAGS,0 ), 0 , GFLAGS),"hclk_secure_ns" , mux_175m_116m_58m_24m_p, CLK_IS_CRITICAL,0 ), 2 , 2 , MFLAGS,0 ), 1 , GFLAGS),"pclk_secure_ns" , mux_116m_58m_24m_p, CLK_IS_CRITICAL,0 ), 4 , 2 , MFLAGS,0 ), 2 , GFLAGS),"hclk_crypto_ns" , "hclk_secure_ns" , 0 ,0 ), 3 , GFLAGS),"pclk_otpc_ns" , "pclk_secure_ns" , 0 ,0 ), 8 , GFLAGS),"clk_otpc_ns" , "xin24m" , 0 ,0 ), 9 , GFLAGS),"aclk_crypto_ns" , "aclk_secure_s" , 0 ,14 , GFLAGS),"hclk_trng_ns" , "hclk_secure_s" , 0 ,13 , GFLAGS),"clk_pka_crypto_ns" , "clk_pka_crypto_s" , 0 ,1 , GFLAGS),/* io */ "clk_vicap_i0clk" , "clk_csihost0_clkdata_i" , 0 ,59 ), 1 , GFLAGS),"clk_vicap_i1clk" , "clk_csihost1_clkdata_i" , 0 ,59 ), 2 , GFLAGS),"clk_vicap_i2clk" , "clk_csihost2_clkdata_i" , 0 ,59 ), 3 , GFLAGS),"clk_vicap_i3clk" , "clk_csihost3_clkdata_i" , 0 ,59 ), 4 , GFLAGS),"clk_vicap_i4clk" , "clk_csihost4_clkdata_i" , 0 ,59 ), 5 , GFLAGS),static void __init rk3576_clk_init(struct device_node *np)struct rockchip_clk_provider *ctx;unsigned long clk_nr_clks;void __iomem *reg_base;struct rockchip_aux_grf *ioc_grf_e;struct rockchip_aux_grf *pmu0_grf_e;struct regmap *ioc_grf;struct regmap *pmu0_grf;1 ;"rockchip,rk3576-pmu0-grf" );if (IS_ERR(pmu0_grf)) {"%s: could not get PMU0 GRF syscon\n" , __func__);return ;"rockchip,rk3576-ioc-grf" );if (IS_ERR(ioc_grf)) {"%s: could not get IOC GRF syscon\n" , __func__);return ;0 );if (!reg_base) {"%s: could not map cru region\n" , __func__);return ;if (IS_ERR(ctx)) {"%s: rockchip clk init failed\n" , __func__);goto err_unmap;sizeof (*pmu0_grf_e), GFP_KERNEL);if (!pmu0_grf_e)goto err_unmap;sizeof (*ioc_grf_e), GFP_KERNEL);if (!ioc_grf_e)goto err_free_pmu0;"armclk_l" ,"armclk_b" ,return ;return ;"rockchip,rk3576-cru" , rk3576_clk_init);struct clk_rk3576_inits {void (*inits)(struct device_node *np);static const struct clk_rk3576_inits clk_rk3576_cru_init = {static const struct of_device_id clk_rk3576_match_table[] = {"rockchip,rk3576-cru" ,static int clk_rk3576_probe(struct platform_device *pdev)const struct clk_rk3576_inits *init_data;struct device *dev = &pdev->dev;if (!init_data)return -EINVAL;if (init_data->inits)return 0 ;static struct platform_driver clk_rk3576_driver = {"clk-rk3576" ,true ,
Messung V0.5 in Prozent C=97 H=98 G=97
