// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2016 Rockchip Electronics Co. Ltd. * Author: Xing Zheng <zhengxing@rock-chips.com> #include <linux/clk-provider.h>#include <linux/module.h>#include <linux/io.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/platform_device.h>#include <linux/property.h>#include <linux/regmap.h>#include <dt-bindings/clock/rk3399-cru.h>#include "clk.h" enum rk3399_plls {enum rk3399_pmu_plls {static struct rockchip_pll_rate_table rk3399_pll_rates[] = {/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 2208000000 , 1 , 92 , 1 , 1 , 1 , 0 ),2184000000 , 1 , 91 , 1 , 1 , 1 , 0 ),2160000000 , 1 , 90 , 1 , 1 , 1 , 0 ),2136000000 , 1 , 89 , 1 , 1 , 1 , 0 ),2112000000 , 1 , 88 , 1 , 1 , 1 , 0 ),2088000000 , 1 , 87 , 1 , 1 , 1 , 0 ),2064000000 , 1 , 86 , 1 , 1 , 1 , 0 ),2040000000 , 1 , 85 , 1 , 1 , 1 , 0 ),2016000000 , 1 , 84 , 1 , 1 , 1 , 0 ),1992000000 , 1 , 83 , 1 , 1 , 1 , 0 ),1968000000 , 1 , 82 , 1 , 1 , 1 , 0 ),1944000000 , 1 , 81 , 1 , 1 , 1 , 0 ),1920000000 , 1 , 80 , 1 , 1 , 1 , 0 ),1896000000 , 1 , 79 , 1 , 1 , 1 , 0 ),1872000000 , 1 , 78 , 1 , 1 , 1 , 0 ),1848000000 , 1 , 77 , 1 , 1 , 1 , 0 ),1824000000 , 1 , 76 , 1 , 1 , 1 , 0 ),1800000000 , 1 , 75 , 1 , 1 , 1 , 0 ),1776000000 , 1 , 74 , 1 , 1 , 1 , 0 ),1752000000 , 1 , 73 , 1 , 1 , 1 , 0 ),1728000000 , 1 , 72 , 1 , 1 , 1 , 0 ),1704000000 , 1 , 71 , 1 , 1 , 1 , 0 ),1680000000 , 1 , 70 , 1 , 1 , 1 , 0 ),1656000000 , 1 , 69 , 1 , 1 , 1 , 0 ),1632000000 , 1 , 68 , 1 , 1 , 1 , 0 ),1608000000 , 1 , 67 , 1 , 1 , 1 , 0 ),1600000000 , 3 , 200 , 1 , 1 , 1 , 0 ),1584000000 , 1 , 66 , 1 , 1 , 1 , 0 ),1560000000 , 1 , 65 , 1 , 1 , 1 , 0 ),1536000000 , 1 , 64 , 1 , 1 , 1 , 0 ),1512000000 , 1 , 63 , 1 , 1 , 1 , 0 ),1488000000 , 1 , 62 , 1 , 1 , 1 , 0 ),1464000000 , 1 , 61 , 1 , 1 , 1 , 0 ),1440000000 , 1 , 60 , 1 , 1 , 1 , 0 ),1416000000 , 1 , 59 , 1 , 1 , 1 , 0 ),1392000000 , 1 , 58 , 1 , 1 , 1 , 0 ),1368000000 , 1 , 57 , 1 , 1 , 1 , 0 ),1344000000 , 1 , 56 , 1 , 1 , 1 , 0 ),1320000000 , 1 , 55 , 1 , 1 , 1 , 0 ),1296000000 , 1 , 54 , 1 , 1 , 1 , 0 ),1272000000 , 1 , 53 , 1 , 1 , 1 , 0 ),1248000000 , 1 , 52 , 1 , 1 , 1 , 0 ),1200000000 , 1 , 50 , 1 , 1 , 1 , 0 ),1188000000 , 2 , 99 , 1 , 1 , 1 , 0 ),1104000000 , 1 , 46 , 1 , 1 , 1 , 0 ),1100000000 , 12 , 550 , 1 , 1 , 1 , 0 ),1008000000 , 1 , 84 , 2 , 1 , 1 , 0 ),1000000000 , 1 , 125 , 3 , 1 , 1 , 0 ),984000000 , 1 , 82 , 2 , 1 , 1 , 0 ),960000000 , 1 , 80 , 2 , 1 , 1 , 0 ),936000000 , 1 , 78 , 2 , 1 , 1 , 0 ),912000000 , 1 , 76 , 2 , 1 , 1 , 0 ),900000000 , 4 , 300 , 2 , 1 , 1 , 0 ),888000000 , 1 , 74 , 2 , 1 , 1 , 0 ),864000000 , 1 , 72 , 2 , 1 , 1 , 0 ),840000000 , 1 , 70 , 2 , 1 , 1 , 0 ),816000000 , 1 , 68 , 2 , 1 , 1 , 0 ),800000000 , 1 , 100 , 3 , 1 , 1 , 0 ),700000000 , 6 , 350 , 2 , 1 , 1 , 0 ),696000000 , 1 , 58 , 2 , 1 , 1 , 0 ),676000000 , 3 , 169 , 2 , 1 , 1 , 0 ),600000000 , 1 , 75 , 3 , 1 , 1 , 0 ),594000000 , 1 , 99 , 4 , 1 , 1 , 0 ),533250000 , 8 , 711 , 4 , 1 , 1 , 0 ),504000000 , 1 , 63 , 3 , 1 , 1 , 0 ),500000000 , 6 , 250 , 2 , 1 , 1 , 0 ),408000000 , 1 , 68 , 2 , 2 , 1 , 0 ),312000000 , 1 , 52 , 2 , 2 , 1 , 0 ),297000000 , 1 , 99 , 4 , 2 , 1 , 0 ),216000000 , 1 , 72 , 4 , 2 , 1 , 0 ),148500000 , 1 , 99 , 4 , 4 , 1 , 0 ),106500000 , 1 , 71 , 4 , 4 , 1 , 0 ),96000000 , 1 , 64 , 4 , 4 , 1 , 0 ),74250000 , 2 , 99 , 4 , 4 , 1 , 0 ),65000000 , 1 , 65 , 6 , 4 , 1 , 0 ),54000000 , 1 , 54 , 6 , 4 , 1 , 0 ),27000000 , 1 , 27 , 6 , 4 , 1 , 0 ),/* sentinel */ }, /* CRU parents */ "xin24m" , "xin32k" };"clk_core_l_lpll_src" ,"clk_core_l_bpll_src" ,"clk_core_l_dpll_src" ,"clk_core_l_gpll_src" };"clk_core_b_lpll_src" ,"clk_core_b_bpll_src" ,"clk_core_b_dpll_src" ,"clk_core_b_gpll_src" };"clk_ddrc_lpll_src" ,"clk_ddrc_bpll_src" ,"clk_ddrc_dpll_src" ,"clk_ddrc_gpll_src" };"cpll_aclk_cci_src" ,"gpll_aclk_cci_src" ,"npll_aclk_cci_src" ,"vpll_aclk_cci_src" };"cpll_cci_trace" ,"gpll_cci_trace" };"cpll_cs" , "gpll_cs" ,"npll_cs" };"cpll_aclk_perihp_src" ,"gpll_aclk_perihp_src" };"cpll" , "gpll" };"cpll" , "gpll" , "npll" };"cpll" , "gpll" , "ppll" };"cpll" , "gpll" , "upll" };"npll" , "cpll" , "gpll" };"cpll" , "gpll" , "npll" ,"ppll" };"cpll" , "gpll" , "npll" ,"xin24m" };"cpll" , "gpll" , "npll" ,"clk_usbphy_480m" };"ppll" , "cpll" , "gpll" ,"npll" , "upll" };"cpll" , "gpll" , "npll" ,"upll" , "xin24m" };"cpll" , "gpll" , "npll" ,"ppll" , "upll" , "xin24m" };"vpll" , "cpll" , "gpll" };"vpll" , "cpll" , "gpll" ,"npll" };"vpll" , "cpll" , "gpll" ,"xin24m" };"dclk_vop0_div" ,"dclk_vop0_frac" };"dclk_vop1_div" ,"dclk_vop1_frac" };"clk_cifout_src" , "xin24m" };"xin24m" , "clk_usbphy_480m" };"xin24m" , "clk_pciephy_ref100m" };"xin24m" , "xin32k" ,"cpll" , "gpll" };"clk_pcie_core_cru" ,"clk_pcie_core_phy" };"cpll_aclk_emmc_src" ,"gpll_aclk_emmc_src" };"cpll_aclk_perilp0_src" ,"gpll_aclk_perilp0_src" };"cpll_fclk_cm0s_src" ,"gpll_fclk_cm0s_src" };"cpll_hclk_perilp1_src" ,"gpll_hclk_perilp1_src" };"clk_testout1_pll_src" , "xin24m" };"clk_testout2_pll_src" , "xin24m" };"clk_usbphy0_480m_src" ,"clk_usbphy1_480m_src" };"cpll_aclk_gmac_src" ,"gpll_aclk_gmac_src" };"clk_gmac" , "clkin_gmac" };"clk_spdif_div" , "clk_spdif_frac" ,"clkin_i2s" , "xin12m" };"clk_i2s0_div" , "clk_i2s0_frac" ,"clkin_i2s" , "xin12m" };"clk_i2s1_div" , "clk_i2s1_frac" ,"clkin_i2s" , "xin12m" };"clk_i2s2_div" , "clk_i2s2_frac" ,"clkin_i2s" , "xin12m" };"clk_i2s0" , "clk_i2s1" ,"clk_i2s2" };"clk_i2sout_src" , "xin12m" };"clk_uart0_div" , "clk_uart0_frac" , "xin24m" };"clk_uart1_div" , "clk_uart1_frac" , "xin24m" };"clk_uart2_div" , "clk_uart2_frac" , "xin24m" };"clk_uart3_div" , "clk_uart3_frac" , "xin24m" };/* PMU CRU parents */ "ppll" , "xin24m" };"xin24m" , "ppll" };"fclk_cm0s_pmu_ppll_src" , "xin24m" };"clk_wifi_div" , "clk_wifi_frac" };"clk_uart4_div" , "clk_uart4_frac" ,"xin24m" };"clk_testout2" , "clk_32k_suspend_pmu" };static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {"lpll" , mux_pll_p, 0 , RK3399_PLL_CON(0 ),3 ), 8 , 31 , 0 , rk3399_pll_rates),"bpll" , mux_pll_p, 0 , RK3399_PLL_CON(8 ),11 ), 8 , 31 , 0 , rk3399_pll_rates),"dpll" , mux_pll_p, 0 , RK3399_PLL_CON(16 ),19 ), 8 , 31 , 0 , NULL),"cpll" , mux_pll_p, 0 , RK3399_PLL_CON(24 ),27 ), 8 , 31 , ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),"gpll" , mux_pll_p, 0 , RK3399_PLL_CON(32 ),35 ), 8 , 31 , ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),"npll" , mux_pll_p, 0 , RK3399_PLL_CON(40 ),43 ), 8 , 31 , ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),"vpll" , mux_pll_p, 0 , RK3399_PLL_CON(48 ),51 ), 8 , 31 , ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {"ppll" , mux_pll_p, 0 , RK3399_PMU_PLL_CON(0 ),3 ), 8 , 31 , ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),#define MFLAGS CLK_MUX_HIWORD_MASK#define DFLAGS CLK_DIVIDER_HIWORD_MASK#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASKstatic struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =0 , "clk_spdif_mux" , mux_spdif_p, CLK_SET_RATE_PARENT,32 ), 13 , 2 , MFLAGS);static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =0 , "clk_i2s0_mux" , mux_i2s0_p, CLK_SET_RATE_PARENT,28 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =0 , "clk_i2s1_mux" , mux_i2s1_p, CLK_SET_RATE_PARENT,29 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =0 , "clk_i2s2_mux" , mux_i2s2_p, CLK_SET_RATE_PARENT,30 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata ="clk_uart0" , mux_uart0_p, CLK_SET_RATE_PARENT,33 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata ="clk_uart1" , mux_uart1_p, CLK_SET_RATE_PARENT,34 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata ="clk_uart2" , mux_uart2_p, CLK_SET_RATE_PARENT,35 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata ="clk_uart3" , mux_uart3_p, CLK_SET_RATE_PARENT,36 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata ="clk_uart4_pmu" , mux_uart4_pmu_p, CLK_SET_RATE_PARENT,5 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata ="dclk_vop0" , mux_dclk_vop0_p, CLK_SET_RATE_PARENT,49 ), 11 , 1 , MFLAGS);static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata ="dclk_vop1" , mux_dclk_vop1_p, CLK_SET_RATE_PARENT,50 ), 11 , 1 , MFLAGS);static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata ="clk_wifi_pmu" , mux_wifi_pmu_p, CLK_SET_RATE_PARENT,1 ), 14 , 1 , MFLAGS);static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {0 ] = RK3399_CLKSEL_CON(0 ),0 ] = 0 ,0 ] = 0 x1f,1 ,3 ,0 ,6 ,0 x3,static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {0 ] = RK3399_CLKSEL_CON(2 ),0 ] = 0 ,0 ] = 0 x1f,1 ,3 ,1 ,6 ,0 x3,#define RK3399_DIV_ACLKM_MASK 0 x1f#define RK3399_DIV_ACLKM_SHIFT 8 #define RK3399_DIV_ATCLK_MASK 0 x1f#define RK3399_DIV_ATCLK_SHIFT 0 #define RK3399_DIV_PCLK_DBG_MASK 0 x1f#define RK3399_DIV_PCLK_DBG_SHIFT 8 #define RK3399_CLKSEL0(_offs, _aclkm) \0 + _offs), \#define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \1 + _offs), \/* cluster_l: aclkm in clksel0, rest in clksel1 */ #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \## U, \0 , _aclkm), \0 , _atclk, _pdbg), \/* cluster_b: aclkm in clksel2, rest in clksel3 */ #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \## U, \2 , _aclkm), \2 , _atclk, _pdbg), \static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {1800000000 , 1 , 8 , 8 ),1704000000 , 1 , 8 , 8 ),1608000000 , 1 , 7 , 7 ),1512000000 , 1 , 7 , 7 ),1488000000 , 1 , 6 , 6 ),1416000000 , 1 , 6 , 6 ),1200000000 , 1 , 5 , 5 ),1008000000 , 1 , 5 , 5 ),816000000 , 1 , 4 , 4 ),696000000 , 1 , 3 , 3 ),600000000 , 1 , 3 , 3 ),408000000 , 1 , 2 , 2 ),312000000 , 1 , 1 , 1 ),216000000 , 1 , 1 , 1 ),96000000 , 1 , 1 , 1 ),static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {2208000000 , 1 , 11 , 11 ),2184000000 , 1 , 11 , 11 ),2088000000 , 1 , 10 , 10 ),2040000000 , 1 , 10 , 10 ),2016000000 , 1 , 9 , 9 ),1992000000 , 1 , 9 , 9 ),1896000000 , 1 , 9 , 9 ),1800000000 , 1 , 8 , 8 ),1704000000 , 1 , 8 , 8 ),1608000000 , 1 , 7 , 7 ),1512000000 , 1 , 7 , 7 ),1488000000 , 1 , 6 , 6 ),1416000000 , 1 , 6 , 6 ),1200000000 , 1 , 5 , 5 ),1008000000 , 1 , 5 , 5 ),816000000 , 1 , 4 , 4 ),696000000 , 1 , 3 , 3 ),600000000 , 1 , 3 , 3 ),408000000 , 1 , 2 , 2 ),312000000 , 1 , 1 , 1 ),216000000 , 1 , 1 , 1 ),96000000 , 1 , 1 , 1 ),static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {/* * CRU Clock-Architecture /* usbphy */ "clk_usb2phy0_ref" , "xin24m" , CLK_IGNORE_UNUSED,6 ), 5 , GFLAGS),"clk_usb2phy1_ref" , "xin24m" , CLK_IGNORE_UNUSED,6 ), 6 , GFLAGS),0 , "clk_usbphy0_480m_src" , "clk_usbphy0_480m" , 0 ,13 ), 12 , GFLAGS),0 , "clk_usbphy1_480m_src" , "clk_usbphy1_480m" , 0 ,13 ), 12 , GFLAGS),0 , "clk_usbphy_480m" , mux_usbphy_480m_p, 0 ,14 ), 6 , 1 , MFLAGS),0 , "upll" , mux_pll_src_24m_usbphy480m_p, 0 ,14 ), 15 , 1 , MFLAGS),"clk_hsicphy" , mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0 ,19 ), 0 , 2 , MFLAGS,6 ), 4 , GFLAGS),"aclk_usb3" , mux_pll_src_cpll_gpll_npll_p, 0 ,39 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,12 ), 0 , GFLAGS),"aclk_usb3_noc" , "aclk_usb3" , CLK_IGNORE_UNUSED,30 ), 0 , GFLAGS),"aclk_usb3otg0" , "aclk_usb3" , 0 ,30 ), 1 , GFLAGS),"aclk_usb3otg1" , "aclk_usb3" , 0 ,30 ), 2 , GFLAGS),"aclk_usb3_rksoc_axi_perf" , "aclk_usb3" , 0 ,30 ), 3 , GFLAGS),"aclk_usb3_grf" , "aclk_usb3" , 0 ,30 ), 4 , GFLAGS),"clk_usb3otg0_ref" , "xin24m" , 0 ,12 ), 1 , GFLAGS),"clk_usb3otg1_ref" , "xin24m" , 0 ,12 ), 2 , GFLAGS),"clk_usb3otg0_suspend" , mux_pll_p, 0 ,40 ), 15 , 1 , MFLAGS, 0 , 10 , DFLAGS,12 ), 3 , GFLAGS),"clk_usb3otg1_suspend" , mux_pll_p, 0 ,41 ), 15 , 1 , MFLAGS, 0 , 10 , DFLAGS,12 ), 4 , GFLAGS),"clk_uphy0_tcpdphy_ref" , mux_pll_p, 0 ,64 ), 15 , 1 , MFLAGS, 8 , 5 , DFLAGS,13 ), 4 , GFLAGS),"clk_uphy0_tcpdcore" , mux_pll_src_24m_32k_cpll_gpll_p, 0 ,64 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,13 ), 5 , GFLAGS),"clk_uphy1_tcpdphy_ref" , mux_pll_p, 0 ,65 ), 15 , 1 , MFLAGS, 8 , 5 , DFLAGS,13 ), 6 , GFLAGS),"clk_uphy1_tcpdcore" , mux_pll_src_24m_32k_cpll_gpll_p, 0 ,65 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,13 ), 7 , GFLAGS),/* little core */ 0 , "clk_core_l_lpll_src" , "lpll" , CLK_IGNORE_UNUSED,0 ), 0 , GFLAGS),0 , "clk_core_l_bpll_src" , "bpll" , CLK_IGNORE_UNUSED,0 ), 1 , GFLAGS),0 , "clk_core_l_dpll_src" , "dpll" , CLK_IGNORE_UNUSED,0 ), 2 , GFLAGS),0 , "clk_core_l_gpll_src" , "gpll" , CLK_IGNORE_UNUSED,0 ), 3 , GFLAGS),0 , "aclkm_core_l" , "armclkl" , CLK_IGNORE_UNUSED,0 ), 8 , 5 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 4 , GFLAGS),0 , "atclk_core_l" , "armclkl" , CLK_IGNORE_UNUSED,1 ), 0 , 5 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 5 , GFLAGS),"pclk_dbg_core_l" , "armclkl" , CLK_IGNORE_UNUSED,1 ), 8 , 5 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 6 , GFLAGS),"aclk_core_adb400_core_l_2_cci500" , "aclkm_core_l" , CLK_IGNORE_UNUSED,14 ), 12 , GFLAGS),"aclk_perf_core_l" , "aclkm_core_l" , CLK_IGNORE_UNUSED,14 ), 13 , GFLAGS),0 , "clk_dbg_pd_core_l" , "armclkl" , CLK_IGNORE_UNUSED,14 ), 9 , GFLAGS),"aclk_core_adb400_gic_2_core_l" , "armclkl" , CLK_IGNORE_UNUSED,14 ), 10 , GFLAGS),"aclk_core_adb400_core_l_2_gic" , "armclkl" , CLK_IGNORE_UNUSED,14 ), 11 , GFLAGS),"clk_pvtm_core_l" , "xin24m" , 0 ,0 ), 7 , GFLAGS),/* big core */ 0 , "clk_core_b_lpll_src" , "lpll" , CLK_IGNORE_UNUSED,1 ), 0 , GFLAGS),0 , "clk_core_b_bpll_src" , "bpll" , CLK_IGNORE_UNUSED,1 ), 1 , GFLAGS),0 , "clk_core_b_dpll_src" , "dpll" , CLK_IGNORE_UNUSED,1 ), 2 , GFLAGS),0 , "clk_core_b_gpll_src" , "gpll" , CLK_IGNORE_UNUSED,1 ), 3 , GFLAGS),0 , "aclkm_core_b" , "armclkb" , CLK_IGNORE_UNUSED,2 ), 8 , 5 , DFLAGS | CLK_DIVIDER_READ_ONLY,1 ), 4 , GFLAGS),0 , "atclk_core_b" , "armclkb" , CLK_IGNORE_UNUSED,3 ), 0 , 5 , DFLAGS | CLK_DIVIDER_READ_ONLY,1 ), 5 , GFLAGS),0 , "pclk_dbg_core_b" , "armclkb" , CLK_IGNORE_UNUSED,3 ), 8 , 5 , DFLAGS | CLK_DIVIDER_READ_ONLY,1 ), 6 , GFLAGS),"aclk_core_adb400_core_b_2_cci500" , "aclkm_core_b" , CLK_IGNORE_UNUSED,14 ), 5 , GFLAGS),"aclk_perf_core_b" , "aclkm_core_b" , CLK_IGNORE_UNUSED,14 ), 6 , GFLAGS),0 , "clk_dbg_pd_core_b" , "armclkb" , CLK_IGNORE_UNUSED,14 ), 1 , GFLAGS),"aclk_core_adb400_gic_2_core_b" , "armclkb" , CLK_IGNORE_UNUSED,14 ), 3 , GFLAGS),"aclk_core_adb400_core_b_2_gic" , "armclkb" , CLK_IGNORE_UNUSED,14 ), 4 , GFLAGS),"pclken_dbg_core_b" , "pclk_dbg_core_b" , CLK_IGNORE_UNUSED,3 ), 13 , 2 , DFLAGS | CLK_DIVIDER_READ_ONLY),0 , "pclk_dbg_cxcs_pd_core_b" , "pclk_dbg_core_b" , CLK_IGNORE_UNUSED,14 ), 2 , GFLAGS),"clk_pvtm_core_b" , "xin24m" , 0 ,1 ), 7 , GFLAGS),/* gmac */ 0 , "cpll_aclk_gmac_src" , "cpll" , CLK_IGNORE_UNUSED,6 ), 9 , GFLAGS),0 , "gpll_aclk_gmac_src" , "gpll" , CLK_IGNORE_UNUSED,6 ), 8 , GFLAGS),0 , "aclk_gmac_pre" , mux_aclk_gmac_p, 0 ,20 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS,6 ), 10 , GFLAGS),"aclk_gmac" , "aclk_gmac_pre" , 0 ,32 ), 0 , GFLAGS),"aclk_gmac_noc" , "aclk_gmac_pre" , CLK_IGNORE_UNUSED,32 ), 1 , GFLAGS),"aclk_perf_gmac" , "aclk_gmac_pre" , 0 ,32 ), 4 , GFLAGS),0 , "pclk_gmac_pre" , "aclk_gmac_pre" , 0 ,19 ), 8 , 3 , DFLAGS,6 ), 11 , GFLAGS),"pclk_gmac" , "pclk_gmac_pre" , 0 ,32 ), 2 , GFLAGS),"pclk_gmac_noc" , "pclk_gmac_pre" , CLK_IGNORE_UNUSED,32 ), 3 , GFLAGS),"clk_gmac" , mux_pll_src_cpll_gpll_npll_p, 0 ,20 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,5 ), 5 , GFLAGS),"clk_rmii_src" , mux_rmii_p, CLK_SET_RATE_PARENT,19 ), 4 , 1 , MFLAGS),"clk_mac_refout" , "clk_rmii_src" , 0 ,5 ), 6 , GFLAGS),"clk_mac_ref" , "clk_rmii_src" , 0 ,5 ), 7 , GFLAGS),"clk_rmii_rx" , "clk_rmii_src" , 0 ,5 ), 8 , GFLAGS),"clk_rmii_tx" , "clk_rmii_src" , 0 ,5 ), 9 , GFLAGS),/* spdif */ 0 , "clk_spdif_div" , mux_pll_src_cpll_gpll_p, 0 ,32 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,8 ), 13 , GFLAGS),0 , "clk_spdif_frac" , "clk_spdif_div" , 0 ,99 ), 0 ,8 ), 14 , GFLAGS,"clk_spdif" , "clk_spdif_mux" , CLK_SET_RATE_PARENT,8 ), 15 , GFLAGS),"clk_spdif_rec_dptx" , mux_pll_src_cpll_gpll_p, 0 ,32 ), 15 , 1 , MFLAGS, 8 , 5 , DFLAGS,10 ), 6 , GFLAGS),/* i2s */ 0 , "clk_i2s0_div" , mux_pll_src_cpll_gpll_p, 0 ,28 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,8 ), 3 , GFLAGS),0 , "clk_i2s0_frac" , "clk_i2s0_div" , CLK_SET_RATE_PARENT,96 ), 0 ,8 ), 4 , GFLAGS,"clk_i2s0" , "clk_i2s0_mux" , CLK_SET_RATE_PARENT,8 ), 5 , GFLAGS),0 , "clk_i2s1_div" , mux_pll_src_cpll_gpll_p, 0 ,29 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,8 ), 6 , GFLAGS),0 , "clk_i2s1_frac" , "clk_i2s1_div" , CLK_SET_RATE_PARENT,97 ), 0 ,8 ), 7 , GFLAGS,"clk_i2s1" , "clk_i2s1_mux" , CLK_SET_RATE_PARENT,8 ), 8 , GFLAGS),0 , "clk_i2s2_div" , mux_pll_src_cpll_gpll_p, 0 ,30 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,8 ), 9 , GFLAGS),0 , "clk_i2s2_frac" , "clk_i2s2_div" , CLK_SET_RATE_PARENT,98 ), 0 ,8 ), 10 , GFLAGS,"clk_i2s2" , "clk_i2s2_mux" , CLK_SET_RATE_PARENT,8 ), 11 , GFLAGS),0 , "clk_i2sout_src" , mux_i2sch_p, CLK_SET_RATE_PARENT,31 ), 0 , 2 , MFLAGS),"clk_i2sout" , mux_i2sout_p, CLK_SET_RATE_PARENT,31 ), 2 , 1 , MFLAGS,8 ), 12 , GFLAGS),/* uart */ 0 , "clk_uart0_src" , mux_pll_src_cpll_gpll_upll_p, 0 ,33 ), 12 , 2 , MFLAGS),0 , "clk_uart0_div" , "clk_uart0_src" , 0 ,33 ), 0 , 7 , DFLAGS,9 ), 0 , GFLAGS),0 , "clk_uart0_frac" , "clk_uart0_div" , 0 ,100 ), 0 ,9 ), 1 , GFLAGS,0 , "clk_uart_src" , mux_pll_src_cpll_gpll_p, 0 ,33 ), 15 , 1 , MFLAGS),0 , "clk_uart1_div" , "clk_uart_src" , 0 ,34 ), 0 , 7 , DFLAGS,9 ), 2 , GFLAGS),0 , "clk_uart1_frac" , "clk_uart1_div" , 0 ,101 ), 0 ,9 ), 3 , GFLAGS,0 , "clk_uart2_div" , "clk_uart_src" , 0 ,35 ), 0 , 7 , DFLAGS,9 ), 4 , GFLAGS),0 , "clk_uart2_frac" , "clk_uart2_div" , 0 ,102 ), 0 ,9 ), 5 , GFLAGS,0 , "clk_uart3_div" , "clk_uart_src" , 0 ,36 ), 0 , 7 , DFLAGS,9 ), 6 , GFLAGS),0 , "clk_uart3_frac" , "clk_uart3_div" , 0 ,103 ), 0 ,9 ), 7 , GFLAGS,"pclk_ddr" , mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,6 ), 15 , 1 , MFLAGS, 8 , 5 , DFLAGS,3 ), 4 , GFLAGS),"pclk_center_main_noc" , "pclk_ddr" , CLK_IGNORE_UNUSED,18 ), 10 , GFLAGS),"pclk_ddr_mon" , "pclk_ddr" , 0 ,18 ), 12 , GFLAGS),"pclk_cic" , "pclk_ddr" , CLK_IGNORE_UNUSED,18 ), 15 , GFLAGS),"pclk_ddr_sgrf" , "pclk_ddr" , CLK_IGNORE_UNUSED,19 ), 2 , GFLAGS),"clk_pvtm_ddr" , "xin24m" , 0 ,4 ), 11 , GFLAGS),"clk_dfimon0_timer" , "xin24m" , 0 ,3 ), 5 , GFLAGS),"clk_dfimon1_timer" , "xin24m" , 0 ,3 ), 6 , GFLAGS),/* cci */ 0 , "cpll_aclk_cci_src" , "cpll" , CLK_IGNORE_UNUSED,2 ), 0 , GFLAGS),0 , "gpll_aclk_cci_src" , "gpll" , CLK_IGNORE_UNUSED,2 ), 1 , GFLAGS),0 , "npll_aclk_cci_src" , "npll" , CLK_IGNORE_UNUSED,2 ), 2 , GFLAGS),0 , "vpll_aclk_cci_src" , "vpll" , CLK_IGNORE_UNUSED,2 ), 3 , GFLAGS),0 , "aclk_cci_pre" , mux_aclk_cci_p, CLK_IGNORE_UNUSED,5 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,2 ), 4 , GFLAGS),"aclk_adb400m_pd_core_l" , "aclk_cci_pre" , CLK_IGNORE_UNUSED,15 ), 0 , GFLAGS),"aclk_adb400m_pd_core_b" , "aclk_cci_pre" , CLK_IGNORE_UNUSED,15 ), 1 , GFLAGS),"aclk_cci" , "aclk_cci_pre" , CLK_IGNORE_UNUSED,15 ), 2 , GFLAGS),"aclk_cci_noc0" , "aclk_cci_pre" , CLK_IGNORE_UNUSED,15 ), 3 , GFLAGS),"aclk_cci_noc1" , "aclk_cci_pre" , CLK_IGNORE_UNUSED,15 ), 4 , GFLAGS),"aclk_cci_grf" , "aclk_cci_pre" , CLK_IGNORE_UNUSED,15 ), 7 , GFLAGS),0 , "cpll_cci_trace" , "cpll" , CLK_IGNORE_UNUSED,2 ), 5 , GFLAGS),0 , "gpll_cci_trace" , "gpll" , CLK_IGNORE_UNUSED,2 ), 6 , GFLAGS),"clk_cci_trace" , mux_cci_trace_p, CLK_IGNORE_UNUSED,5 ), 15 , 2 , MFLAGS, 8 , 5 , DFLAGS,2 ), 7 , GFLAGS),0 , "cpll_cs" , "cpll" , CLK_IGNORE_UNUSED,2 ), 8 , GFLAGS),0 , "gpll_cs" , "gpll" , CLK_IGNORE_UNUSED,2 ), 9 , GFLAGS),0 , "npll_cs" , "npll" , CLK_IGNORE_UNUSED,2 ), 10 , GFLAGS),0 , "clk_cs" , mux_cs_p, CLK_IGNORE_UNUSED,4 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS),0 , "clk_dbg_cxcs" , "clk_cs" , CLK_IGNORE_UNUSED,15 ), 5 , GFLAGS),0 , "clk_dbg_noc" , "clk_cs" , CLK_IGNORE_UNUSED,15 ), 6 , GFLAGS),/* vcodec */ 0 , "aclk_vcodec_pre" , mux_pll_src_cpll_gpll_npll_ppll_p, 0 ,7 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,4 ), 0 , GFLAGS),0 , "hclk_vcodec_pre" , "aclk_vcodec_pre" , 0 ,7 ), 8 , 5 , DFLAGS,4 ), 1 , GFLAGS),"hclk_vcodec" , "hclk_vcodec_pre" , 0 ,17 ), 2 , GFLAGS),0 , "hclk_vcodec_noc" , "hclk_vcodec_pre" , CLK_IGNORE_UNUSED,17 ), 3 , GFLAGS),"aclk_vcodec" , "aclk_vcodec_pre" , 0 ,17 ), 0 , GFLAGS),0 , "aclk_vcodec_noc" , "aclk_vcodec_pre" , CLK_IGNORE_UNUSED,17 ), 1 , GFLAGS),/* vdu */ "clk_vdu_core" , mux_pll_src_cpll_gpll_npll_p, 0 ,9 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,4 ), 4 , GFLAGS),"clk_vdu_ca" , mux_pll_src_cpll_gpll_npll_p, 0 ,9 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,4 ), 5 , GFLAGS),0 , "aclk_vdu_pre" , mux_pll_src_cpll_gpll_npll_ppll_p, 0 ,8 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,4 ), 2 , GFLAGS),0 , "hclk_vdu_pre" , "aclk_vdu_pre" , 0 ,8 ), 8 , 5 , DFLAGS,4 ), 3 , GFLAGS),"hclk_vdu" , "hclk_vdu_pre" , 0 ,17 ), 10 , GFLAGS),"hclk_vdu_noc" , "hclk_vdu_pre" , CLK_IGNORE_UNUSED,17 ), 11 , GFLAGS),"aclk_vdu" , "aclk_vdu_pre" , 0 ,17 ), 8 , GFLAGS),"aclk_vdu_noc" , "aclk_vdu_pre" , CLK_IGNORE_UNUSED,17 ), 9 , GFLAGS),/* iep */ 0 , "aclk_iep_pre" , mux_pll_src_cpll_gpll_npll_ppll_p, 0 ,10 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,4 ), 6 , GFLAGS),0 , "hclk_iep_pre" , "aclk_iep_pre" , 0 ,10 ), 8 , 5 , DFLAGS,4 ), 7 , GFLAGS),"hclk_iep" , "hclk_iep_pre" , 0 ,16 ), 2 , GFLAGS),"hclk_iep_noc" , "hclk_iep_pre" , CLK_IGNORE_UNUSED,16 ), 3 , GFLAGS),"aclk_iep" , "aclk_iep_pre" , 0 ,16 ), 0 , GFLAGS),"aclk_iep_noc" , "aclk_iep_pre" , CLK_IGNORE_UNUSED,16 ), 1 , GFLAGS),/* rga */ "clk_rga_core" , mux_pll_src_cpll_gpll_npll_ppll_p, 0 ,12 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,4 ), 10 , GFLAGS),0 , "aclk_rga_pre" , mux_pll_src_cpll_gpll_npll_ppll_p, 0 ,11 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,4 ), 8 , GFLAGS),0 , "hclk_rga_pre" , "aclk_rga_pre" , 0 ,11 ), 8 , 5 , DFLAGS,4 ), 9 , GFLAGS),"hclk_rga" , "hclk_rga_pre" , 0 ,16 ), 10 , GFLAGS),"hclk_rga_noc" , "hclk_rga_pre" , CLK_IGNORE_UNUSED,16 ), 11 , GFLAGS),"aclk_rga" , "aclk_rga_pre" , 0 ,16 ), 8 , GFLAGS),"aclk_rga_noc" , "aclk_rga_pre" , CLK_IGNORE_UNUSED,16 ), 9 , GFLAGS),/* center */ 0 , "aclk_center" , mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,12 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,3 ), 7 , GFLAGS),"aclk_center_main_noc" , "aclk_center" , CLK_IGNORE_UNUSED,19 ), 0 , GFLAGS),"aclk_center_peri_noc" , "aclk_center" , CLK_IGNORE_UNUSED,19 ), 1 , GFLAGS),/* gpu */ 0 , "aclk_gpu_pre" , mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,13 ), 5 , 3 , MFLAGS, 0 , 5 , DFLAGS,13 ), 0 , GFLAGS),"aclk_gpu" , "aclk_gpu_pre" , 0 ,30 ), 8 , GFLAGS),"aclk_perf_gpu" , "aclk_gpu_pre" , 0 ,30 ), 10 , GFLAGS),"aclk_gpu_grf" , "aclk_gpu_pre" , 0 ,30 ), 11 , GFLAGS),"aclk_pvtm_gpu" , "xin24m" , 0 ,13 ), 1 , GFLAGS),/* perihp */ 0 , "cpll_aclk_perihp_src" , "cpll" , CLK_IGNORE_UNUSED,5 ), 1 , GFLAGS),0 , "gpll_aclk_perihp_src" , "gpll" , CLK_IGNORE_UNUSED,5 ), 0 , GFLAGS),"aclk_perihp" , mux_aclk_perihp_p, CLK_IGNORE_UNUSED,14 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS,5 ), 2 , GFLAGS),"hclk_perihp" , "aclk_perihp" , CLK_IGNORE_UNUSED,14 ), 8 , 2 , DFLAGS,5 ), 3 , GFLAGS),"pclk_perihp" , "aclk_perihp" , CLK_IGNORE_UNUSED,14 ), 12 , 2 , DFLAGS,5 ), 4 , GFLAGS),"aclk_perf_pcie" , "aclk_perihp" , 0 ,20 ), 2 , GFLAGS),"aclk_pcie" , "aclk_perihp" , 0 ,20 ), 10 , GFLAGS),0 , "aclk_perihp_noc" , "aclk_perihp" , CLK_IGNORE_UNUSED,20 ), 12 , GFLAGS),"hclk_host0" , "hclk_perihp" , 0 ,20 ), 5 , GFLAGS),"hclk_host0_arb" , "hclk_perihp" , 0 ,20 ), 6 , GFLAGS),"hclk_host1" , "hclk_perihp" , 0 ,20 ), 7 , GFLAGS),"hclk_host1_arb" , "hclk_perihp" , 0 ,20 ), 8 , GFLAGS),"hclk_hsic" , "hclk_perihp" , 0 ,20 ), 9 , GFLAGS),0 , "hclk_perihp_noc" , "hclk_perihp" , CLK_IGNORE_UNUSED,20 ), 13 , GFLAGS),0 , "hclk_ahb1tom" , "hclk_perihp" , CLK_IGNORE_UNUSED,20 ), 15 , GFLAGS),"pclk_perihp_grf" , "pclk_perihp" , CLK_IGNORE_UNUSED,20 ), 4 , GFLAGS),"pclk_pcie" , "pclk_perihp" , 0 ,20 ), 11 , GFLAGS),0 , "pclk_perihp_noc" , "pclk_perihp" , CLK_IGNORE_UNUSED,20 ), 14 , GFLAGS),"pclk_hsicphy" , "pclk_perihp" , 0 ,31 ), 8 , GFLAGS),/* sdio & sdmmc */ "hclk_sd" , mux_pll_src_cpll_gpll_p, 0 ,13 ), 15 , 1 , MFLAGS, 8 , 5 , DFLAGS,12 ), 13 , GFLAGS),"hclk_sdmmc" , "hclk_sd" , 0 ,33 ), 8 , GFLAGS),0 , "hclk_sdmmc_noc" , "hclk_sd" , CLK_IGNORE_UNUSED,33 ), 9 , GFLAGS),"clk_sdio" , mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0 ,15 ), 8 , 3 , MFLAGS, 0 , 7 , DFLAGS,6 ), 0 , GFLAGS),"clk_sdmmc" , mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0 ,16 ), 8 , 3 , MFLAGS, 0 , 7 , DFLAGS,6 ), 1 , GFLAGS),"sdmmc_drv" , "clk_sdmmc" , RK3399_SDMMC_CON0, 1 ),"sdmmc_sample" , "clk_sdmmc" , RK3399_SDMMC_CON1, 1 ),"sdio_drv" , "clk_sdio" , RK3399_SDIO_CON0, 1 ),"sdio_sample" , "clk_sdio" , RK3399_SDIO_CON1, 1 ),/* pcie */ "clk_pcie_pm" , mux_pll_src_cpll_gpll_npll_24m_p, 0 ,17 ), 8 , 3 , MFLAGS, 0 , 7 , DFLAGS,6 ), 2 , GFLAGS),"clk_pciephy_ref100m" , "npll" , 0 ,18 ), 11 , 5 , DFLAGS,12 ), 6 , GFLAGS),"clk_pciephy_ref" , mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,18 ), 10 , 1 , MFLAGS),0 , "clk_pcie_core_cru" , mux_pll_src_cpll_gpll_npll_p, 0 ,18 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,6 ), 3 , GFLAGS),"clk_pcie_core" , mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,18 ), 7 , 1 , MFLAGS),/* emmc */ "clk_emmc" , mux_pll_src_cpll_gpll_npll_upll_24m_p, 0 ,22 ), 8 , 3 , MFLAGS, 0 , 7 , DFLAGS,6 ), 14 , GFLAGS),0 , "cpll_aclk_emmc_src" , "cpll" , CLK_IGNORE_UNUSED,6 ), 13 , GFLAGS),0 , "gpll_aclk_emmc_src" , "gpll" , CLK_IGNORE_UNUSED,6 ), 12 , GFLAGS),"aclk_emmc" , mux_aclk_emmc_p, CLK_IGNORE_UNUSED,21 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS),"aclk_emmccore" , "aclk_emmc" , CLK_IGNORE_UNUSED,32 ), 8 , GFLAGS),"aclk_emmc_noc" , "aclk_emmc" , CLK_IGNORE_UNUSED,32 ), 9 , GFLAGS),"aclk_emmcgrf" , "aclk_emmc" , CLK_IGNORE_UNUSED,32 ), 10 , GFLAGS),/* perilp0 */ 0 , "cpll_aclk_perilp0_src" , "cpll" , CLK_IGNORE_UNUSED,7 ), 1 , GFLAGS),0 , "gpll_aclk_perilp0_src" , "gpll" , CLK_IGNORE_UNUSED,7 ), 0 , GFLAGS),"aclk_perilp0" , mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,23 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS,7 ), 2 , GFLAGS),"hclk_perilp0" , "aclk_perilp0" , CLK_IGNORE_UNUSED,23 ), 8 , 2 , DFLAGS,7 ), 3 , GFLAGS),"pclk_perilp0" , "aclk_perilp0" , 0 ,23 ), 12 , 3 , DFLAGS,7 ), 4 , GFLAGS),/* aclk_perilp0 gates */ "aclk_intmem" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23 ), 0 , GFLAGS),"aclk_tzma" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23 ), 1 , GFLAGS),"clk_intmem0" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23 ), 2 , GFLAGS),"clk_intmem1" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23 ), 3 , GFLAGS),"clk_intmem2" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23 ), 4 , GFLAGS),"clk_intmem3" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23 ), 5 , GFLAGS),"clk_intmem4" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23 ), 6 , GFLAGS),"clk_intmem5" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23 ), 7 , GFLAGS),"aclk_dcf" , "aclk_perilp0" , 0 , RK3399_CLKGATE_CON(23 ), 8 , GFLAGS),"aclk_dmac0_perilp" , "aclk_perilp0" , 0 , RK3399_CLKGATE_CON(25 ), 5 , GFLAGS),"aclk_dmac1_perilp" , "aclk_perilp0" , 0 , RK3399_CLKGATE_CON(25 ), 6 , GFLAGS),"aclk_perilp0_noc" , "aclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25 ), 7 , GFLAGS),/* hclk_perilp0 gates */ "hclk_rom" , "hclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24 ), 4 , GFLAGS),"hclk_m_crypto0" , "hclk_perilp0" , 0 , RK3399_CLKGATE_CON(24 ), 5 , GFLAGS),"hclk_s_crypto0" , "hclk_perilp0" , 0 , RK3399_CLKGATE_CON(24 ), 6 , GFLAGS),"hclk_m_crypto1" , "hclk_perilp0" , 0 , RK3399_CLKGATE_CON(24 ), 14 , GFLAGS),"hclk_s_crypto1" , "hclk_perilp0" , 0 , RK3399_CLKGATE_CON(24 ), 15 , GFLAGS),"hclk_perilp0_noc" , "hclk_perilp0" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25 ), 8 , GFLAGS),/* pclk_perilp0 gates */ "pclk_dcf" , "pclk_perilp0" , 0 , RK3399_CLKGATE_CON(23 ), 9 , GFLAGS),/* crypto */ "clk_crypto0" , mux_pll_src_cpll_gpll_ppll_p, 0 ,24 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,7 ), 7 , GFLAGS),"clk_crypto1" , mux_pll_src_cpll_gpll_ppll_p, 0 ,26 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,7 ), 8 , GFLAGS),/* cm0s_perilp */ 0 , "cpll_fclk_cm0s_src" , "cpll" , 0 ,7 ), 6 , GFLAGS),0 , "gpll_fclk_cm0s_src" , "gpll" , 0 ,7 ), 5 , GFLAGS),"fclk_cm0s" , mux_fclk_cm0s_p, 0 ,24 ), 15 , 1 , MFLAGS, 8 , 5 , DFLAGS,7 ), 9 , GFLAGS),/* fclk_cm0s gates */ "sclk_m0_perilp" , "fclk_cm0s" , 0 , RK3399_CLKGATE_CON(24 ), 8 , GFLAGS),"hclk_m0_perilp" , "fclk_cm0s" , 0 , RK3399_CLKGATE_CON(24 ), 9 , GFLAGS),"dclk_m0_perilp" , "fclk_cm0s" , 0 , RK3399_CLKGATE_CON(24 ), 10 , GFLAGS),"clk_m0_perilp_dec" , "fclk_cm0s" , 0 , RK3399_CLKGATE_CON(24 ), 11 , GFLAGS),"hclk_m0_perilp_noc" , "fclk_cm0s" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25 ), 11 , GFLAGS),/* perilp1 */ 0 , "cpll_hclk_perilp1_src" , "cpll" , CLK_IGNORE_UNUSED,8 ), 1 , GFLAGS),0 , "gpll_hclk_perilp1_src" , "gpll" , CLK_IGNORE_UNUSED,8 ), 0 , GFLAGS),"hclk_perilp1" , mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,25 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS),"pclk_perilp1" , "hclk_perilp1" , CLK_IGNORE_UNUSED,25 ), 8 , 3 , DFLAGS,8 ), 2 , GFLAGS),/* hclk_perilp1 gates */ 0 , "hclk_perilp1_noc" , "hclk_perilp1" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25 ), 9 , GFLAGS),0 , "hclk_sdio_noc" , "hclk_perilp1" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25 ), 12 , GFLAGS),"hclk_i2s0" , "hclk_perilp1" , 0 , RK3399_CLKGATE_CON(34 ), 0 , GFLAGS),"hclk_i2s1" , "hclk_perilp1" , 0 , RK3399_CLKGATE_CON(34 ), 1 , GFLAGS),"hclk_i2s2" , "hclk_perilp1" , 0 , RK3399_CLKGATE_CON(34 ), 2 , GFLAGS),"hclk_spdif" , "hclk_perilp1" , 0 , RK3399_CLKGATE_CON(34 ), 3 , GFLAGS),"hclk_sdio" , "hclk_perilp1" , 0 , RK3399_CLKGATE_CON(34 ), 4 , GFLAGS),"pclk_spi5" , "hclk_perilp1" , 0 , RK3399_CLKGATE_CON(34 ), 5 , GFLAGS),0 , "hclk_sdioaudio_noc" , "hclk_perilp1" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34 6 , GFLAGS),/* pclk_perilp1 gates */ "pclk_uart0" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(22 ), 0 , GFLAGS),"pclk_uart1" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(22 ), 1 , GFLAGS),"pclk_uart2" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(22 ), 2 , GFLAGS),"pclk_uart3" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(22 ), 3 , GFLAGS),"pclk_rki2c7" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(22 ), 5 , GFLAGS),"pclk_rki2c1" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(22 ), 6 , GFLAGS),"pclk_rki2c5" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(22 ), 7 , GFLAGS),"pclk_rki2c6" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(22 ), 8 , GFLAGS),"pclk_rki2c2" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(22 ), 9 , GFLAGS),"pclk_rki2c3" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(22 ), 10 , GFLAGS),"pclk_mailbox0" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(22 ), 11 , GFLAGS),"pclk_saradc" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(22 ), 12 , GFLAGS),"pclk_tsadc" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(22 ), 13 , GFLAGS),"pclk_efuse1024ns" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(22 ), 14 , GFLAGS),"pclk_efuse1024s" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(22 ), 15 , GFLAGS),"pclk_spi0" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(23 ), 10 , GFLAGS),"pclk_spi1" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(23 ), 11 , GFLAGS),"pclk_spi2" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(23 ), 12 , GFLAGS),"pclk_spi4" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(23 ), 13 , GFLAGS),"pclk_perilp_sgrf" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(24 ), 13 0 , "pclk_perilp1_noc" , "pclk_perilp1" , 0 , RK3399_CLKGATE_CON(25 ), 10 , GFLAGS),/* saradc */ "clk_saradc" , "xin24m" , 0 ,26 ), 8 , 8 , DFLAGS,9 ), 11 , GFLAGS),/* tsadc */ "clk_tsadc" , mux_pll_p, 0 ,27 ), 15 , 1 , MFLAGS, 0 , 10 , DFLAGS,9 ), 10 , GFLAGS),/* cif_testout */ 0 , "clk_testout1_pll_src" , mux_pll_src_cpll_gpll_npll_p, 0 ,38 ), 6 , 2 , MFLAGS),"clk_testout1" , mux_clk_testout1_p, 0 ,38 ), 5 , 1 , MFLAGS, 0 , 5 , DFLAGS,13 ), 14 , GFLAGS),0 , "clk_testout2_pll_src" , mux_pll_src_cpll_gpll_npll_p, 0 ,38 ), 14 , 2 , MFLAGS),"clk_testout2" , mux_clk_testout2_p, 0 ,38 ), 13 , 1 , MFLAGS, 8 , 5 , DFLAGS,13 ), 15 , GFLAGS),/* vio */ "aclk_vio" , mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,42 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,11 ), 0 , GFLAGS),"pclk_vio" , "aclk_vio" , 0 ,43 ), 0 , 5 , DFLAGS,11 ), 1 , GFLAGS),"aclk_vio_noc" , "aclk_vio" , CLK_IGNORE_UNUSED,29 ), 0 , GFLAGS),"pclk_mipi_dsi0" , "pclk_vio" , 0 ,29 ), 1 , GFLAGS),"pclk_mipi_dsi1" , "pclk_vio" , 0 ,29 ), 2 , GFLAGS),"pclk_vio_grf" , "pclk_vio" , CLK_IGNORE_UNUSED,29 ), 12 , GFLAGS),/* hdcp */ "aclk_hdcp" , mux_pll_src_cpll_gpll_ppll_p, 0 ,42 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,11 ), 12 , GFLAGS),"hclk_hdcp" , "aclk_hdcp" , 0 ,43 ), 5 , 5 , DFLAGS,11 ), 3 , GFLAGS),"pclk_hdcp" , "aclk_hdcp" , 0 ,43 ), 10 , 5 , DFLAGS,11 ), 10 , GFLAGS),"aclk_hdcp_noc" , "aclk_hdcp" , CLK_IGNORE_UNUSED,29 ), 4 , GFLAGS),"aclk_hdcp22" , "aclk_hdcp" , 0 ,29 ), 10 , GFLAGS),"hclk_hdcp_noc" , "hclk_hdcp" , CLK_IGNORE_UNUSED,29 ), 5 , GFLAGS),"hclk_hdcp22" , "hclk_hdcp" , 0 ,29 ), 9 , GFLAGS),"pclk_hdcp_noc" , "pclk_hdcp" , CLK_IGNORE_UNUSED,29 ), 3 , GFLAGS),"pclk_hdmi_ctrl" , "pclk_hdcp" , 0 ,29 ), 6 , GFLAGS),"pclk_dp_ctrl" , "pclk_hdcp" , 0 ,29 ), 7 , GFLAGS),"pclk_hdcp22" , "pclk_hdcp" , 0 ,29 ), 8 , GFLAGS),"pclk_gasket" , "pclk_hdcp" , 0 ,29 ), 11 , GFLAGS),/* edp */ "clk_dp_core" , mux_pll_src_npll_cpll_gpll_p, 0 ,46 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,11 ), 8 , GFLAGS),"pclk_edp" , mux_pll_src_cpll_gpll_p, 0 ,44 ), 15 , 1 , MFLAGS, 8 , 6 , DFLAGS,11 ), 11 , GFLAGS),"pclk_edp_noc" , "pclk_edp" , CLK_IGNORE_UNUSED,32 ), 12 , GFLAGS),"pclk_edp_ctrl" , "pclk_edp" , 0 ,32 ), 13 , GFLAGS),/* hdmi */ "clk_hdmi_sfr" , "xin24m" , 0 ,11 ), 6 , GFLAGS),"clk_hdmi_cec" , mux_pll_p, 0 ,45 ), 15 , 1 , MFLAGS, 0 , 10 , DFLAGS,11 ), 7 , GFLAGS),/* vop0 */ "aclk_vop0_pre" , mux_pll_src_vpll_cpll_gpll_npll_p, 0 ,47 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,10 ), 8 , GFLAGS),0 , "hclk_vop0_pre" , "aclk_vop0_pre" , 0 ,47 ), 8 , 5 , DFLAGS,10 ), 9 , GFLAGS),"aclk_vop0" , "aclk_vop0_pre" , 0 ,28 ), 3 , GFLAGS),"aclk_vop0_noc" , "aclk_vop0_pre" , CLK_IGNORE_UNUSED,28 ), 1 , GFLAGS),"hclk_vop0" , "hclk_vop0_pre" , 0 ,28 ), 2 , GFLAGS),"hclk_vop0_noc" , "hclk_vop0_pre" , CLK_IGNORE_UNUSED,28 ), 0 , GFLAGS),"dclk_vop0_div" , mux_pll_src_vpll_cpll_gpll_p, 0 ,49 ), 8 , 2 , MFLAGS, 0 , 8 , DFLAGS,10 ), 12 , GFLAGS),"dclk_vop0_frac" , "dclk_vop0_div" , 0 ,106 ), 0 ,"clk_vop0_pwm" , mux_pll_src_vpll_cpll_gpll_24m_p, 0 ,51 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,10 ), 14 , GFLAGS),/* vop1 */ "aclk_vop1_pre" , mux_pll_src_vpll_cpll_gpll_npll_p, 0 ,48 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,10 ), 10 , GFLAGS),0 , "hclk_vop1_pre" , "aclk_vop1_pre" , 0 ,48 ), 8 , 5 , DFLAGS,10 ), 11 , GFLAGS),"aclk_vop1" , "aclk_vop1_pre" , 0 ,28 ), 7 , GFLAGS),"aclk_vop1_noc" , "aclk_vop1_pre" , CLK_IGNORE_UNUSED,28 ), 5 , GFLAGS),"hclk_vop1" , "hclk_vop1_pre" , 0 ,28 ), 6 , GFLAGS),"hclk_vop1_noc" , "hclk_vop1_pre" , CLK_IGNORE_UNUSED,28 ), 4 , GFLAGS),"dclk_vop1_div" , mux_pll_src_vpll_cpll_gpll_p, 0 ,50 ), 8 , 2 , MFLAGS, 0 , 8 , DFLAGS,10 ), 13 , GFLAGS),"dclk_vop1_frac" , "dclk_vop1_div" , 0 ,107 ), 0 ,"clk_vop1_pwm" , mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,52 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,10 ), 15 , GFLAGS),/* isp */ "aclk_isp0" , mux_pll_src_cpll_gpll_ppll_p, 0 ,53 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,12 ), 8 , GFLAGS),"hclk_isp0" , "aclk_isp0" , 0 ,53 ), 8 , 5 , DFLAGS,12 ), 9 , GFLAGS),"aclk_isp0_noc" , "aclk_isp0" , CLK_IGNORE_UNUSED,27 ), 1 , GFLAGS),"aclk_isp0_wrapper" , "aclk_isp0" , 0 ,27 ), 5 , GFLAGS),"hclk_isp1_wrapper" , "aclk_isp0" , 0 ,27 ), 7 , GFLAGS),"hclk_isp0_noc" , "hclk_isp0" , CLK_IGNORE_UNUSED,27 ), 0 , GFLAGS),"hclk_isp0_wrapper" , "hclk_isp0" , 0 ,27 ), 4 , GFLAGS),"clk_isp0" , mux_pll_src_cpll_gpll_npll_p, 0 ,55 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,11 ), 4 , GFLAGS),"aclk_isp1" , mux_pll_src_cpll_gpll_ppll_p, 0 ,54 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,12 ), 10 , GFLAGS),"hclk_isp1" , "aclk_isp1" , 0 ,54 ), 8 , 5 , DFLAGS,12 ), 11 , GFLAGS),"aclk_isp1_noc" , "aclk_isp1" , CLK_IGNORE_UNUSED,27 ), 3 , GFLAGS),"hclk_isp1_noc" , "hclk_isp1" , CLK_IGNORE_UNUSED,27 ), 2 , GFLAGS),"aclk_isp1_wrapper" , "hclk_isp1" , 0 ,27 ), 8 , GFLAGS),"clk_isp1" , mux_pll_src_cpll_gpll_npll_p, 0 ,55 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,11 ), 5 , GFLAGS),/* * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system, * so we ignore the mux and make clocks nodes as following, * * pclkin_cifinv --|-------\ * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper * pclkin_cif --|-------/ "pclkin_isp1_wrapper" , "pclkin_cif" , 0 ,27 ), 6 , GFLAGS),/* cif */ 0 , "clk_cifout_src" , mux_pll_src_cpll_gpll_npll_p, 0 ,56 ), 6 , 2 , MFLAGS,10 ), 7 , GFLAGS),"clk_cifout" , mux_clk_cif_p, CLK_SET_RATE_PARENT,56 ), 5 , 1 , MFLAGS, 0 , 5 , DFLAGS),/* gic */ "aclk_gic_pre" , mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,56 ), 15 , 1 , MFLAGS, 8 , 5 , DFLAGS,12 ), 12 , GFLAGS),"aclk_gic" , "aclk_gic_pre" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33 ), 0 , GFLAGS),"aclk_gic_noc" , "aclk_gic_pre" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33 ), 1 , GFLAGS),"aclk_gic_adb400_core_l_2_gic" , "aclk_gic_pre" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33 ), 2 , GFLAGS),"aclk_gic_adb400_core_b_2_gic" , "aclk_gic_pre" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33 ), 3 , GFLAGS),"aclk_gic_adb400_gic_2_core_l" , "aclk_gic_pre" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33 ), 4 , GFLAGS),"aclk_gic_adb400_gic_2_core_b" , "aclk_gic_pre" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33 ), 5 , GFLAGS),/* alive */ /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */ "pclk_alive" , "gpll" , 0 ,57 ), 0 , 5 , DFLAGS),"pclk_usbphy_mux_g" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21 ), 4 , GFLAGS),"pclk_uphy0_tcphy_g" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21 ), 5 , GFLAGS),"pclk_uphy0_tcpd_g" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21 ), 6 , GFLAGS),"pclk_uphy1_tcphy_g" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21 ), 8 , GFLAGS),"pclk_uphy1_tcpd_g" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21 ), 9 , GFLAGS),"pclk_grf" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31 ), 1 , GFLAGS),"pclk_intr_arb" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31 ), 2 , GFLAGS),"pclk_gpio2" , "pclk_alive" , 0 , RK3399_CLKGATE_CON(31 ), 3 , GFLAGS),"pclk_gpio3" , "pclk_alive" , 0 , RK3399_CLKGATE_CON(31 ), 4 , GFLAGS),"pclk_gpio4" , "pclk_alive" , 0 , RK3399_CLKGATE_CON(31 ), 5 , GFLAGS),"pclk_timer0" , "pclk_alive" , 0 , RK3399_CLKGATE_CON(31 ), 6 , GFLAGS),"pclk_timer1" , "pclk_alive" , 0 , RK3399_CLKGATE_CON(31 ), 7 , GFLAGS),"pclk_pmu_intr_arb" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31 ), 9 , GFLAGS),"pclk_sgrf" , "pclk_alive" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31 ), 10 , GFLAGS),/* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */ "pclk_wdt" , "pclk_alive" ),"clk_mipidphy_ref" , "xin24m" , 0 , RK3399_CLKGATE_CON(11 ), 14 , GFLAGS),"clk_dphy_pll" , "clk_mipidphy_ref" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21 ), 0 , GFLAGS),"clk_mipidphy_cfg" , "xin24m" , 0 , RK3399_CLKGATE_CON(11 ), 15 , GFLAGS),"clk_dphy_tx0_cfg" , "clk_mipidphy_cfg" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21 ), 1 , GFLAGS),"clk_dphy_tx1rx1_cfg" , "clk_mipidphy_cfg" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21 ), 2 , GFLAGS),"clk_dphy_rx0_cfg" , "clk_mipidphy_cfg" , CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21 ), 3 , GFLAGS),/* testout */ 0 , "clk_test_pre" , mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,58 ), 7 , 1 , MFLAGS),0 , "clk_test_frac" , "clk_test_pre" , 0 ,105 ), 0 ,13 ), 9 , GFLAGS),0 , "clk_test_24m" , "xin24m" , 0 ,57 ), 6 , 10 , DFLAGS),/* spi */ "clk_spi0" , mux_pll_src_cpll_gpll_p, 0 ,59 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,9 ), 12 , GFLAGS),"clk_spi1" , mux_pll_src_cpll_gpll_p, 0 ,59 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,9 ), 13 , GFLAGS),"clk_spi2" , mux_pll_src_cpll_gpll_p, 0 ,60 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,9 ), 14 , GFLAGS),"clk_spi4" , mux_pll_src_cpll_gpll_p, 0 ,60 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,9 ), 15 , GFLAGS),"clk_spi5" , mux_pll_src_cpll_gpll_p, 0 ,58 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,13 ), 13 , GFLAGS),/* i2c */ "clk_i2c1" , mux_pll_src_cpll_gpll_p, 0 ,61 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,10 ), 0 , GFLAGS),"clk_i2c2" , mux_pll_src_cpll_gpll_p, 0 ,62 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,10 ), 2 , GFLAGS),"clk_i2c3" , mux_pll_src_cpll_gpll_p, 0 ,63 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,10 ), 4 , GFLAGS),"clk_i2c5" , mux_pll_src_cpll_gpll_p, 0 ,61 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,10 ), 1 , GFLAGS),"clk_i2c6" , mux_pll_src_cpll_gpll_p, 0 ,62 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,10 ), 3 , GFLAGS),"clk_i2c7" , mux_pll_src_cpll_gpll_p, 0 ,63 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,10 ), 5 , GFLAGS),/* timer */ "clk_timer00" , "xin24m" , 0 , RK3399_CLKGATE_CON(26 ), 0 , GFLAGS),"clk_timer01" , "xin24m" , 0 , RK3399_CLKGATE_CON(26 ), 1 , GFLAGS),"clk_timer02" , "xin24m" , 0 , RK3399_CLKGATE_CON(26 ), 2 , GFLAGS),"clk_timer03" , "xin24m" , 0 , RK3399_CLKGATE_CON(26 ), 3 , GFLAGS),"clk_timer04" , "xin24m" , 0 , RK3399_CLKGATE_CON(26 ), 4 , GFLAGS),"clk_timer05" , "xin24m" , 0 , RK3399_CLKGATE_CON(26 ), 5 , GFLAGS),"clk_timer06" , "xin24m" , 0 , RK3399_CLKGATE_CON(26 ), 6 , GFLAGS),"clk_timer07" , "xin24m" , 0 , RK3399_CLKGATE_CON(26 ), 7 , GFLAGS),"clk_timer08" , "xin24m" , 0 , RK3399_CLKGATE_CON(26 ), 8 , GFLAGS),"clk_timer09" , "xin24m" , 0 , RK3399_CLKGATE_CON(26 ), 9 , GFLAGS),"clk_timer10" , "xin24m" , 0 , RK3399_CLKGATE_CON(26 ), 10 , GFLAGS),"clk_timer11" , "xin24m" , 0 , RK3399_CLKGATE_CON(26 ), 11 , GFLAGS),/* clk_test */ /* clk_test_pre is controlled by CRU_MISC_CON[3] */ 0 , "clk_test" , "clk_test_pre" , CLK_IGNORE_UNUSED,58 ), 0 , 5 , DFLAGS,13 ), 11 , GFLAGS),/* ddrc */ 0 , "clk_ddrc_lpll_src" , "lpll" , 0 , RK3399_CLKGATE_CON(3 ),0 , GFLAGS),0 , "clk_ddrc_bpll_src" , "bpll" , 0 , RK3399_CLKGATE_CON(3 ),1 , GFLAGS),0 , "clk_ddrc_dpll_src" , "dpll" , 0 , RK3399_CLKGATE_CON(3 ),2 , GFLAGS),0 , "clk_ddrc_gpll_src" , "gpll" , 0 , RK3399_CLKGATE_CON(3 ),3 , GFLAGS),"sclk_ddrc" , mux_ddrclk_p, 0 ,6 ), 4 , 2 , 0 , 0 , ROCKCHIP_DDRCLK_SIP),static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {/* * PMU CRU Clock-Architecture 0 , "fclk_cm0s_pmu_ppll_src" , "ppll" , 0 ,0 ), 1 , GFLAGS),"fclk_cm0s_src_pmu" , mux_fclk_cm0s_pmu_ppll_p, 0 0 ), 15 , 1 , MFLAGS, 8 , 5 , DFLAGS),"clk_spi3_pmu" , mux_24m_ppll_p, 0 ,1 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,0 ), 2 , GFLAGS),0 , "clk_wifi_div" , mux_ppll_24m_p, CLK_IGNORE_UNUSED,1 ), 13 , 1 , MFLAGS, 8 , 5 , DFLAGS,0 ), 8 , GFLAGS),0 , "clk_wifi_frac" , "clk_wifi_div" , 0 ,7 ), 0 ,0 , "clk_timer_src_pmu" , mux_pll_p, CLK_IGNORE_UNUSED,1 ), 15 , 1 , MFLAGS),"clk_i2c0_pmu" , "ppll" , 0 ,2 ), 0 , 7 , DFLAGS,0 ), 9 , GFLAGS),"clk_i2c4_pmu" , "ppll" , 0 ,3 ), 0 , 7 , DFLAGS,0 ), 10 , GFLAGS),"clk_i2c8_pmu" , "ppll" , 0 ,2 ), 8 , 7 , DFLAGS,0 ), 11 , GFLAGS),0 , "clk_32k_suspend_pmu" , "xin24m" , CLK_IGNORE_UNUSED,4 ), 0 , 10 , DFLAGS),0 , "clk_testout_2io" , mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,4 ), 15 , 1 , MFLAGS),0 , "clk_uart4_div" , mux_24m_ppll_p, 0 ,5 ), 10 , 1 , MFLAGS, 0 , 7 , DFLAGS,0 ), 5 , GFLAGS),0 , "clk_uart4_frac" , "clk_uart4_div" , 0 ,6 ), 0 ,0 ), 6 , GFLAGS,"pclk_pmu_src" , "ppll" , CLK_IGNORE_UNUSED,0 ), 0 , 5 , DFLAGS),/* pmu clock gates */ "clk_timer0_pmu" , "clk_timer_src_pmu" , 0 , RK3399_PMU_CLKGATE_CON(0 ), 3 , GFLAGS),"clk_timer1_pmu" , "clk_timer_src_pmu" , 0 , RK3399_PMU_CLKGATE_CON(0 ), 4 , GFLAGS),"clk_pvtm_pmu" , "xin24m" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0 ), 7 , GFLAGS),"pclk_pmu" , "pclk_pmu_src" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1 ), 0 , GFLAGS),"pclk_pmugrf_pmu" , "pclk_pmu_src" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1 ), 1 , GFLAGS),"pclk_intmem1_pmu" , "pclk_pmu_src" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1 ), 2 , GFLAGS),"pclk_gpio0_pmu" , "pclk_pmu_src" , 0 , RK3399_PMU_CLKGATE_CON(1 ), 3 "pclk_gpio1_pmu" , "pclk_pmu_src" , 0 , RK3399_PMU_CLKGATE_CON(1 ), 4 "pclk_sgrf_pmu" , "pclk_pmu_src" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1 ), 5 , GFLAGS),"pclk_noc_pmu" , "pclk_pmu_src" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1 ), 6 , GFLAGS),"pclk_i2c0_pmu" , "pclk_pmu_src" , 0 , RK3399_PMU_CLKGATE_CON(1 ), 7 , GFLAGS),"pclk_i2c4_pmu" , "pclk_pmu_src" , 0 , RK3399_PMU_CLKGATE_CON(1 ), 8 , GFLAGS),"pclk_i2c8_pmu" , "pclk_pmu_src" , 0 , RK3399_PMU_CLKGATE_CON(1 ), 9 , GFLAGS),"pclk_rkpwm_pmu" , "pclk_pmu_src" , 0 , RK3399_PMU_CLKGATE_CON(1 ), 10 "pclk_spi3_pmu" , "pclk_pmu_src" , 0 , RK3399_PMU_CLKGATE_CON(1 ), 11 , GFLAGS),"pclk_timer_pmu" , "pclk_pmu_src" , 0 , RK3399_PMU_CLKGATE_CON(1 ), 12 "pclk_mailbox_pmu" , "pclk_pmu_src" , 0 , RK3399_PMU_CLKGATE_CON(1 ), 13 , GFLAGS),"pclk_uart4_pmu" , "pclk_pmu_src" , 0 , RK3399_PMU_CLKGATE_CON(1 ), 14 "pclk_wdt_m0_pmu" , "pclk_pmu_src" , 0 , RK3399_PMU_CLKGATE_CON(1 ), 15 , GFLAGS),"fclk_cm0s_pmu" , "fclk_cm0s_src_pmu" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2 ), 0 , GFLAGS),"sclk_cm0s_pmu" , "fclk_cm0s_src_pmu" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2 ), 1 , GFLAGS),"hclk_cm0s_pmu" , "fclk_cm0s_src_pmu" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2 ), 2 , GFLAGS),"dclk_cm0s_pmu" , "fclk_cm0s_src_pmu" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2 ), 3 , GFLAGS),"hclk_noc_pmu" , "fclk_cm0s_src_pmu" , CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2 ), 5 , GFLAGS),static const char *const rk3399_cru_critical_clocks[] __initconst = {"aclk_cci_pre" ,"aclk_gic" ,"aclk_gic_noc" ,"aclk_hdcp_noc" ,"hclk_hdcp_noc" ,"pclk_hdcp_noc" ,"pclk_perilp0" ,"pclk_perilp0" ,"hclk_perilp0" ,"hclk_perilp0_noc" ,"pclk_perilp1" ,"pclk_perilp1_noc" ,"pclk_perihp" ,"pclk_perihp_noc" ,"hclk_perihp" ,"aclk_perihp" ,"aclk_perihp_noc" ,"aclk_perilp0" ,"aclk_perilp0_noc" ,"hclk_perilp1" ,"hclk_perilp1_noc" ,"aclk_dmac0_perilp" ,"aclk_emmc_noc" ,"gpll_hclk_perilp1_src" ,"gpll_aclk_perilp0_src" ,"gpll_aclk_perihp_src" ,"aclk_vio_noc" ,/* ddrc */ "sclk_ddrc" ,"armclkl" ,"armclkb" ,static const char *const rk3399_pmucru_critical_clocks[] __initconst = {"ppll" ,"pclk_pmu_src" ,"fclk_cm0s_src_pmu" ,"clk_timer_src_pmu" ,"pclk_rkpwm_pmu" ,static void __init rk3399_clk_init(struct device_node *np)struct rockchip_clk_provider *ctx;unsigned long clk_nr_clks;void __iomem *reg_base;0 );if (!reg_base) {"%s: could not map cru region\n" , __func__);return ;1 ;if (IS_ERR(ctx)) {"%s: rockchip clk init failed\n" , __func__);return ;1 );"armclkl" ,"armclkb" ,21 , reg_base + RK3399_SOFTRST_CON(0 ),"rockchip,rk3399-cru" , rk3399_clk_init);static void __init rk3399_pmu_clk_init(struct device_node *np)struct rockchip_clk_provider *ctx;unsigned long clkpmu_nr_clks;void __iomem *reg_base;0 );if (!reg_base) {"%s: could not map cru pmu region\n" , __func__);return ;1 ;if (IS_ERR(ctx)) {"%s: rockchip pmu clk init failed\n" , __func__);return ;1 );2 , reg_base + RK3399_PMU_SOFTRST_CON(0 ),"rockchip,rk3399-pmucru" , rk3399_pmu_clk_init);struct clk_rk3399_inits {void (*inits)(struct device_node *np);static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {static const struct clk_rk3399_inits clk_rk3399_cru_init = {static const struct of_device_id clk_rk3399_match_table[] = {"rockchip,rk3399-cru" ,"rockchip,rk3399-pmucru" ,static int __init clk_rk3399_probe(struct platform_device *pdev)struct device_node *np = pdev->dev.of_node;const struct clk_rk3399_inits *init_data;if (init_data->inits)return 0 ;static struct platform_driver clk_rk3399_driver = {"clk-rk3399" ,true ,
Messung V0.5 in Prozent C=97 H=94 G=95
