// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko@sntech.de> #include <linux/clk-provider.h>#include <linux/io.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/syscore_ops.h>#include <dt-bindings/clock/rk3288-cru.h>#include "clk.h" #define RK3288_GRF_SOC_CON(x) (0 x244 + x * 4 )#define RK3288_GRF_SOC_STATUS1 0 x284enum rk3288_variant {enum rk3288_plls {static struct rockchip_pll_rate_table rk3288_pll_rates[] = {2208000000 , 1 , 92 , 1 ),2184000000 , 1 , 91 , 1 ),2160000000 , 1 , 90 , 1 ),2136000000 , 1 , 89 , 1 ),2112000000 , 1 , 88 , 1 ),2088000000 , 1 , 87 , 1 ),2064000000 , 1 , 86 , 1 ),2040000000 , 1 , 85 , 1 ),2016000000 , 1 , 84 , 1 ),1992000000 , 1 , 83 , 1 ),1968000000 , 1 , 82 , 1 ),1944000000 , 1 , 81 , 1 ),1920000000 , 1 , 80 , 1 ),1896000000 , 1 , 79 , 1 ),1872000000 , 1 , 78 , 1 ),1848000000 , 1 , 77 , 1 ),1824000000 , 1 , 76 , 1 ),1800000000 , 1 , 75 , 1 ),1776000000 , 1 , 74 , 1 ),1752000000 , 1 , 73 , 1 ),1728000000 , 1 , 72 , 1 ),1704000000 , 1 , 71 , 1 ),1680000000 , 1 , 70 , 1 ),1656000000 , 1 , 69 , 1 ),1632000000 , 1 , 68 , 1 ),1608000000 , 1 , 67 , 1 ),1560000000 , 1 , 65 , 1 ),1512000000 , 1 , 63 , 1 ),1488000000 , 1 , 62 , 1 ),1464000000 , 1 , 61 , 1 ),1440000000 , 1 , 60 , 1 ),1416000000 , 1 , 59 , 1 ),1392000000 , 1 , 58 , 1 ),1368000000 , 1 , 57 , 1 ),1344000000 , 1 , 56 , 1 ),1320000000 , 1 , 55 , 1 ),1296000000 , 1 , 54 , 1 ),1272000000 , 1 , 53 , 1 ),1248000000 , 1 , 52 , 1 ),1224000000 , 1 , 51 , 1 ),1200000000 , 1 , 50 , 1 ),1188000000 , 2 , 99 , 1 ),1176000000 , 1 , 49 , 1 ),1128000000 , 1 , 47 , 1 ),1104000000 , 1 , 46 , 1 ),1008000000 , 1 , 84 , 2 ),912000000 , 1 , 76 , 2 ),891000000 , 8 , 594 , 2 ),888000000 , 1 , 74 , 2 ),816000000 , 1 , 68 , 2 ),798000000 , 2 , 133 , 2 ),792000000 , 1 , 66 , 2 ),768000000 , 1 , 64 , 2 ),742500000 , 8 , 495 , 2 ),696000000 , 1 , 58 , 2 ),621000000 , 1 , 207 , 8 , 1 ),600000000 , 1 , 50 , 2 ),594000000 , 1 , 198 , 8 , 1 ),552000000 , 1 , 46 , 2 ),504000000 , 1 , 84 , 4 ),500000000 , 3 , 125 , 2 ),456000000 , 1 , 76 , 4 ),428000000 , 1 , 107 , 6 ),408000000 , 1 , 68 , 4 ),400000000 , 3 , 100 , 2 ),394000000 , 1 , 197 , 12 , 1 ),384000000 , 2 , 128 , 4 ),360000000 , 1 , 60 , 4 ),356000000 , 1 , 178 , 12 , 1 ),324000000 , 1 , 189 , 14 , 1 ),312000000 , 1 , 52 , 4 ),308000000 , 1 , 154 , 12 , 1 ),303000000 , 1 , 202 , 16 , 1 ),300000000 , 1 , 75 , 6 ),297750000 , 2 , 397 , 16 , 1 ),293250000 , 2 , 391 , 16 , 1 ),292500000 , 1 , 195 , 16 , 1 ),273600000 , 1 , 114 , 10 ),273000000 , 1 , 182 , 16 , 1 ),270000000 , 1 , 180 , 16 , 1 ),266250000 , 2 , 355 , 16 , 1 ),256500000 , 1 , 171 , 16 , 1 ),252000000 , 1 , 84 , 8 ),250500000 , 1 , 167 , 16 , 1 ),243428571 , 1 , 142 , 14 , 1 ),238000000 , 1 , 119 , 12 ),219750000 , 2 , 293 , 16 , 1 ),216000000 , 1 , 144 , 16 , 1 ),213000000 , 1 , 142 , 16 , 1 ),195428571 , 1 , 114 , 14 ),160000000 , 1 , 80 , 12 ),157500000 , 1 , 105 , 16 ),126000000 , 1 , 84 , 16 ),/* sentinel */ }, #define RK3288_DIV_ACLK_CORE_M0_MASK 0 xf#define RK3288_DIV_ACLK_CORE_M0_SHIFT 0 #define RK3288_DIV_ACLK_CORE_MP_MASK 0 xf#define RK3288_DIV_ACLK_CORE_MP_SHIFT 4 #define RK3288_DIV_L2RAM_MASK 0 x7#define RK3288_DIV_L2RAM_SHIFT 0 #define RK3288_DIV_ATCLK_MASK 0 x1f#define RK3288_DIV_ATCLK_SHIFT 4 #define RK3288_DIV_PCLK_DBGPRE_MASK 0 x1f#define RK3288_DIV_PCLK_DBGPRE_SHIFT 9 #define RK3288_CLKSEL0(_core_m0, _core_mp) \0 ), \#define RK3288_CLKSEL37(_l2ram, _atclk, _pclk_dbg_pre) \37 ), \#define RK3288_CPUCLK_RATE(_prate, _core_m0, _core_mp, _l2ram, _atclk, _pdbg) \static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {1800000000 , 1 , 3 , 1 , 3 , 3 ),1704000000 , 1 , 3 , 1 , 3 , 3 ),1608000000 , 1 , 3 , 1 , 3 , 3 ),1512000000 , 1 , 3 , 1 , 3 , 3 ),1416000000 , 1 , 3 , 1 , 3 , 3 ),1200000000 , 1 , 3 , 1 , 3 , 3 ),1008000000 , 1 , 3 , 1 , 3 , 3 ),816000000 , 1 , 3 , 1 , 3 , 3 ),696000000 , 1 , 3 , 1 , 3 , 3 ),600000000 , 1 , 3 , 1 , 3 , 3 ),408000000 , 1 , 3 , 1 , 3 , 3 ),312000000 , 1 , 3 , 1 , 3 , 3 ),216000000 , 1 , 3 , 1 , 3 , 3 ),126000000 , 1 , 3 , 1 , 3 , 3 ),static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {0 ] = RK3288_CLKSEL_CON(0 ),0 ] = 8 ,0 ] = 0 x1f,1 ,1 ,0 ,15 ,0 x1,"xin24m" , "xin32k" };"apll_core" , "gpll_core" };"dpll_ddr" , "gpll_ddr" };"cpll_aclk_cpu" , "gpll_aclk_cpu" };"cpll" , "gpll" };"npll" , "cpll" , "gpll" };"cpll" , "gpll" , "npll" };"cpll" , "gpll" , "unstable:usbphy480m_src" };"cpll" , "gpll" , "unstable:usbphy480m_src" , "npll" "cpll" , "gpll" , "xin24m" , "xin24m" };"i2s_src" , "i2s_frac" , "ext_i2s" , "xin12m" };"i2s_pre" , "xin12m" };"spdif_pre" , "spdif_frac" , "xin12m" };"spdif_8ch_pre" , "spdif_8ch_frac" , "xin12m" };"uart0_src" , "uart0_frac" , "xin24m" };"uart1_src" , "uart1_frac" , "xin24m" };"uart2_src" , "uart2_frac" , "xin24m" };"uart3_src" , "uart3_frac" , "xin24m" };"uart4_src" , "uart4_frac" , "xin24m" };"vip_src" , "xin24m" };"mac_pll_src" , "ext_gmac" };"hsadc_src" , "ext_hsadc" };"ext_edp_24m" , "xin24m" };"cpll" , "gpll" , "npll" , "xin27m" };"aclk_vdpu" , "aclk_vepu" };"sclk_otgphy1_480m" , "sclk_otgphy2_480m" ,"sclk_otgphy0_480m" };"cpll" , "gpll" , "usbphy480m_src" };"hsicphy12m_xin12m" , "hsicphy12m_usbphy" };static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {"apll" , mux_pll_p, 0 , RK3288_PLL_CON(0 ),0 , 6 , 0 , rk3288_pll_rates),"dpll" , mux_pll_p, 0 , RK3288_PLL_CON(4 ),4 , 5 , 0 , NULL),"cpll" , mux_pll_p, 0 , RK3288_PLL_CON(8 ),8 , 7 , ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),"gpll" , mux_pll_p, 0 , RK3288_PLL_CON(12 ),12 , 8 , ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),"npll" , mux_pll_p, 0 , RK3288_PLL_CON(16 ),14 , 9 , ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),static struct clk_div_table div_hclk_cpu_t[] = {0 , .div = 1 },1 , .div = 2 },3 , .div = 4 },/* sentinel */}, #define MFLAGS CLK_MUX_HIWORD_MASK#define DFLAGS CLK_DIVIDER_HIWORD_MASK#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASKstatic struct rockchip_clk_branch rk3288_i2s_fracmux __initdata =0 , "i2s_pre" , mux_i2s_pre_p, CLK_SET_RATE_PARENT,4 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3288_spdif_fracmux __initdata =0 , "spdif_mux" , mux_spdif_p, CLK_SET_RATE_PARENT,5 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3288_spdif_8ch_fracmux __initdata =0 , "spdif_8ch_mux" , mux_spdif_8ch_p, CLK_SET_RATE_PARENT,40 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3288_uart0_fracmux __initdata ="sclk_uart0" , mux_uart0_p, CLK_SET_RATE_PARENT,13 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3288_uart1_fracmux __initdata ="sclk_uart1" , mux_uart1_p, CLK_SET_RATE_PARENT,14 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3288_uart2_fracmux __initdata ="sclk_uart2" , mux_uart2_p, CLK_SET_RATE_PARENT,15 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3288_uart3_fracmux __initdata ="sclk_uart3" , mux_uart3_p, CLK_SET_RATE_PARENT,16 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3288_uart4_fracmux __initdata ="sclk_uart4" , mux_uart4_p, CLK_SET_RATE_PARENT,3 ), 8 , 2 , MFLAGS);static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {/* * Clock-Architecture Diagram 1 0 , "apll_core" , "apll" , CLK_IGNORE_UNUSED,0 ), 1 , GFLAGS),0 , "gpll_core" , "gpll" , CLK_IGNORE_UNUSED,0 ), 2 , GFLAGS),0 , "armcore0" , "armclk" , CLK_IGNORE_UNUSED,36 ), 0 , 3 , DFLAGS | CLK_DIVIDER_READ_ONLY,12 ), 0 , GFLAGS),0 , "armcore1" , "armclk" , CLK_IGNORE_UNUSED,36 ), 4 , 3 , DFLAGS | CLK_DIVIDER_READ_ONLY,12 ), 1 , GFLAGS),0 , "armcore2" , "armclk" , CLK_IGNORE_UNUSED,36 ), 8 , 3 , DFLAGS | CLK_DIVIDER_READ_ONLY,12 ), 2 , GFLAGS),0 , "armcore3" , "armclk" , CLK_IGNORE_UNUSED,36 ), 12 , 3 , DFLAGS | CLK_DIVIDER_READ_ONLY,12 ), 3 , GFLAGS),0 , "l2ram" , "armclk" , CLK_IGNORE_UNUSED,37 ), 0 , 3 , DFLAGS | CLK_DIVIDER_READ_ONLY,12 ), 4 , GFLAGS),0 , "aclk_core_m0" , "armclk" , CLK_IGNORE_UNUSED,0 ), 0 , 4 , DFLAGS | CLK_DIVIDER_READ_ONLY,12 ), 5 , GFLAGS),0 , "aclk_core_mp" , "armclk" , CLK_IGNORE_UNUSED,0 ), 4 , 4 , DFLAGS | CLK_DIVIDER_READ_ONLY,12 ), 6 , GFLAGS),0 , "atclk" , "armclk" , 0 ,37 ), 4 , 5 , DFLAGS | CLK_DIVIDER_READ_ONLY,12 ), 7 , GFLAGS),0 , "pclk_dbg_pre" , "armclk" , CLK_IGNORE_UNUSED,37 ), 9 , 5 , DFLAGS | CLK_DIVIDER_READ_ONLY,12 ), 8 , GFLAGS),0 , "pclk_dbg" , "pclk_dbg_pre" , 0 ,12 ), 9 , GFLAGS),0 , "cs_dbg" , "pclk_dbg_pre" , CLK_IGNORE_UNUSED,12 ), 10 , GFLAGS),0 , "pclk_core_niu" , "pclk_dbg_pre" , 0 ,12 ), 11 , GFLAGS),0 , "dpll_ddr" , "dpll" , CLK_IGNORE_UNUSED,0 ), 8 , GFLAGS),0 , "gpll_ddr" , "gpll" , 0 ,0 ), 9 , GFLAGS),0 , "ddrphy" , mux_ddrphy_p, CLK_IGNORE_UNUSED,26 ), 2 , 1 , MFLAGS, 0 , 2 ,0 , "gpll_aclk_cpu" , "gpll" , CLK_IGNORE_UNUSED,0 ), 10 , GFLAGS),0 , "cpll_aclk_cpu" , "cpll" , CLK_IGNORE_UNUSED,0 ), 11 , GFLAGS),0 , "aclk_cpu_src" , mux_aclk_cpu_src_p, CLK_IGNORE_UNUSED,1 ), 15 , 1 , MFLAGS, 3 , 5 , DFLAGS),0 , "aclk_cpu_pre" , "aclk_cpu_src" , CLK_SET_RATE_PARENT,1 ), 0 , 3 , DFLAGS),"aclk_cpu" , "aclk_cpu_pre" , CLK_IGNORE_UNUSED,0 ), 3 , GFLAGS),"pclk_cpu" , "aclk_cpu_pre" , CLK_IGNORE_UNUSED,1 ), 12 , 3 , DFLAGS,0 ), 5 , GFLAGS),"hclk_cpu" , "aclk_cpu_pre" , CLK_IGNORE_UNUSED,1 ), 8 , 2 , DFLAGS, div_hclk_cpu_t,0 ), 4 , GFLAGS),0 , "c2c_host" , "aclk_cpu_src" , 0 ,13 ), 8 , GFLAGS),"crypto" , "aclk_cpu_pre" , 0 ,26 ), 6 , 2 , DFLAGS,5 ), 4 , GFLAGS),0 , "aclk_bus_2pmu" , "aclk_cpu_pre" , CLK_IGNORE_UNUSED,0 ), 7 , GFLAGS),0 , "xin12m" , "xin24m" , 0 , 1 , 2 ),0 , "i2s_src" , mux_pll_src_cpll_gpll_p, 0 ,4 ), 15 , 1 , MFLAGS, 0 , 7 , DFLAGS,4 ), 1 , GFLAGS),0 , "i2s_frac" , "i2s_src" , CLK_SET_RATE_PARENT,8 ), 0 ,4 ), 2 , GFLAGS,"i2s0_clkout" , mux_i2s_clkout_p, 0 ,4 ), 12 , 1 , MFLAGS,4 ), 0 , GFLAGS),"sclk_i2s0" , "i2s_pre" , CLK_SET_RATE_PARENT,4 ), 3 , GFLAGS),0 , "spdif_src" , mux_pll_src_cpll_gpll_p, 0 ,5 ), 15 , 1 , MFLAGS),0 , "spdif_pre" , "spdif_src" , CLK_SET_RATE_PARENT,5 ), 0 , 7 , DFLAGS,4 ), 4 , GFLAGS),0 , "spdif_frac" , "spdif_src" , CLK_SET_RATE_PARENT,9 ), 0 ,4 ), 5 , GFLAGS,"sclk_spdif" , "spdif_mux" , CLK_SET_RATE_PARENT,4 ), 6 , GFLAGS),0 , "spdif_8ch_pre" , "spdif_src" , CLK_SET_RATE_PARENT,40 ), 0 , 7 , DFLAGS,4 ), 7 , GFLAGS),0 , "spdif_8ch_frac" , "spdif_8ch_pre" , CLK_SET_RATE_PARENT,41 ), 0 ,4 ), 8 , GFLAGS,"sclk_spdif_8ch" , "spdif_8ch_mux" , CLK_SET_RATE_PARENT,4 ), 9 , GFLAGS),0 , "sclk_acc_efuse" , "xin24m" , 0 ,0 ), 12 , GFLAGS),"sclk_timer0" , "xin24m" , 0 ,1 ), 0 , GFLAGS),"sclk_timer1" , "xin24m" , 0 ,1 ), 1 , GFLAGS),"sclk_timer2" , "xin24m" , 0 ,1 ), 2 , GFLAGS),"sclk_timer3" , "xin24m" , 0 ,1 ), 3 , GFLAGS),"sclk_timer4" , "xin24m" , 0 ,1 ), 4 , GFLAGS),"sclk_timer5" , "xin24m" , 0 ,1 ), 5 , GFLAGS),/* * Clock-Architecture Diagram 2 0 , "aclk_vepu" , mux_pll_src_cpll_gpll_usb480m_p, 0 ,32 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,3 ), 9 , GFLAGS),0 , "aclk_vdpu" , mux_pll_src_cpll_gpll_usb480m_p, 0 ,32 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,3 ), 11 , GFLAGS),0 , "aclk_vcodec_pre" , mux_aclk_vcodec_pre_p, CLK_SET_RATE_PARENT,0 ), 7 , 1 , MFLAGS, grf_type_sys),"aclk_vcodec" , "aclk_vcodec_pre" , 0 ,9 ), 0 , GFLAGS),0 , "hclk_vcodec_pre" , "aclk_vcodec_pre" , 0 , 1 , 4 ,3 ), 10 , GFLAGS),"hclk_vcodec" , "hclk_vcodec_pre" , 0 ,9 ), 1 , GFLAGS),0 , "aclk_vio0" , mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,31 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,3 ), 0 , GFLAGS),0 , "aclk_vio1" , mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,31 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,3 ), 2 , GFLAGS),0 , "aclk_rga_pre" , mux_pll_src_cpll_gpll_usb480m_p, 0 ,30 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,3 ), 5 , GFLAGS),"sclk_rga" , mux_pll_src_cpll_gpll_usb480m_p, 0 ,30 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,3 ), 4 , GFLAGS),"dclk_vop0" , mux_pll_src_cpll_gpll_npll_p, 0 ,27 ), 0 , 2 , MFLAGS, 8 , 8 , DFLAGS,3 ), 1 , GFLAGS),"dclk_vop1" , mux_pll_src_cpll_gpll_npll_p, 0 ,29 ), 6 , 2 , MFLAGS, 8 , 8 , DFLAGS,3 ), 3 , GFLAGS),"sclk_edp_24m" , mux_edp_24m_p, 0 ,28 ), 15 , 1 , MFLAGS,3 ), 12 , GFLAGS),"sclk_edp" , mux_pll_src_cpll_gpll_npll_p, 0 ,28 ), 6 , 2 , MFLAGS, 0 , 6 , DFLAGS,3 ), 13 , GFLAGS),"sclk_isp" , mux_pll_src_cpll_gpll_npll_p, 0 ,6 ), 6 , 2 , MFLAGS, 0 , 6 , DFLAGS,3 ), 14 , GFLAGS),"sclk_isp_jpe" , mux_pll_src_cpll_gpll_npll_p, 0 ,6 ), 14 , 2 , MFLAGS, 8 , 6 , DFLAGS,3 ), 15 , GFLAGS),"sclk_hdmi_hdcp" , "xin24m" , 0 ,5 ), 12 , GFLAGS),"sclk_hdmi_cec" , "xin32k" , 0 ,5 ), 11 , GFLAGS),"aclk_hevc" , mux_pll_src_cpll_gpll_npll_p, 0 ,39 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,13 ), 13 , GFLAGS),"hclk_hevc" , "aclk_hevc" , 0 ,40 ), 12 , 2 , DFLAGS),"sclk_hevc_cabac" , mux_pll_src_cpll_gpll_npll_p, 0 ,42 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,13 ), 14 , GFLAGS),"sclk_hevc_core" , mux_pll_src_cpll_gpll_npll_p, 0 ,42 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,13 ), 15 , GFLAGS),0 , "vip_src" , mux_pll_src_cpll_gpll_p, 0 ,26 ), 8 , 1 , MFLAGS,3 ), 7 , GFLAGS),"sclk_vip_out" , mux_vip_out_p, 0 ,26 ), 15 , 1 , MFLAGS, 9 , 5 , DFLAGS),0 , "pclk_pd_alive" , "gpll" , 0 ,33 ), 8 , 5 , DFLAGS),0 , "pclk_pd_pmu" , "gpll" , CLK_IGNORE_UNUSED,33 ), 0 , 5 , DFLAGS,5 ), 8 , GFLAGS),"sclk_gpu" , mux_pll_src_cpll_gll_usb_npll_p, 0 ,34 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,5 ), 7 , GFLAGS),0 , "aclk_peri_src" , mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,10 ), 15 , 1 , MFLAGS, 0 , 5 , DFLAGS,2 ), 0 , GFLAGS),"pclk_peri" , "aclk_peri_src" , 0 ,10 ), 12 , 2 , DFLAGS | CLK_DIVIDER_POWER_OF_TWO,2 ), 3 , GFLAGS),"hclk_peri" , "aclk_peri_src" , CLK_IGNORE_UNUSED,10 ), 8 , 2 , DFLAGS | CLK_DIVIDER_POWER_OF_TWO,2 ), 2 , GFLAGS),"aclk_peri" , "aclk_peri_src" , CLK_IGNORE_UNUSED,2 ), 1 , GFLAGS),/* * Clock-Architecture Diagram 3 "sclk_spi0" , mux_pll_src_cpll_gpll_p, 0 ,25 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,2 ), 9 , GFLAGS),"sclk_spi1" , mux_pll_src_cpll_gpll_p, 0 ,25 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,2 ), 10 , GFLAGS),"sclk_spi2" , mux_pll_src_cpll_gpll_p, 0 ,39 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,2 ), 11 , GFLAGS),"sclk_sdmmc" , mux_mmc_src_p, 0 ,11 ), 6 , 2 , MFLAGS, 0 , 6 , DFLAGS,13 ), 0 , GFLAGS),"sclk_sdio0" , mux_mmc_src_p, 0 ,12 ), 6 , 2 , MFLAGS, 0 , 6 , DFLAGS,13 ), 1 , GFLAGS),"sclk_sdio1" , mux_mmc_src_p, 0 ,34 ), 14 , 2 , MFLAGS, 8 , 6 , DFLAGS,13 ), 2 , GFLAGS),"sclk_emmc" , mux_mmc_src_p, 0 ,12 ), 14 , 2 , MFLAGS, 8 , 6 , DFLAGS,13 ), 3 , GFLAGS),"sdmmc_drv" , "sclk_sdmmc" , RK3288_SDMMC_CON0, 1 ),"sdmmc_sample" , "sclk_sdmmc" , RK3288_SDMMC_CON1, 0 ),"sdio0_drv" , "sclk_sdio0" , RK3288_SDIO0_CON0, 1 ),"sdio0_sample" , "sclk_sdio0" , RK3288_SDIO0_CON1, 0 ),"sdio1_drv" , "sclk_sdio1" , RK3288_SDIO1_CON0, 1 ),"sdio1_sample" , "sclk_sdio1" , RK3288_SDIO1_CON1, 0 ),"emmc_drv" , "sclk_emmc" , RK3288_EMMC_CON0, 1 ),"emmc_sample" , "sclk_emmc" , RK3288_EMMC_CON1, 0 ),0 , "sclk_tspout" , mux_tspout_p, 0 ,35 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,4 ), 11 , GFLAGS),0 , "sclk_tsp" , mux_pll_src_cpll_gpll_npll_p, 0 ,35 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,4 ), 10 , GFLAGS),"sclk_otgphy0" , "xin24m" , CLK_IGNORE_UNUSED,13 ), 4 , GFLAGS),"sclk_otgphy1" , "xin24m" , CLK_IGNORE_UNUSED,13 ), 5 , GFLAGS),"sclk_otgphy2" , "xin24m" , CLK_IGNORE_UNUSED,13 ), 6 , GFLAGS),"sclk_otg_adp" , "xin32k" , CLK_IGNORE_UNUSED,13 ), 7 , GFLAGS),"sclk_tsadc" , "xin32k" , 0 ,2 ), 0 , 6 , DFLAGS,2 ), 7 , GFLAGS),"sclk_saradc" , "xin24m" , 0 ,24 ), 8 , 8 , DFLAGS,2 ), 8 , GFLAGS),"sclk_ps2c" , "xin24m" , 0 ,5 ), 13 , GFLAGS),"sclk_nandc0" , mux_pll_src_cpll_gpll_p, 0 ,38 ), 7 , 1 , MFLAGS, 0 , 5 , DFLAGS,5 ), 5 , GFLAGS),"sclk_nandc1" , mux_pll_src_cpll_gpll_p, 0 ,38 ), 15 , 1 , MFLAGS, 8 , 5 , DFLAGS,5 ), 6 , GFLAGS),0 , "uart0_src" , mux_pll_src_cpll_gll_usb_npll_p, 0 ,13 ), 13 , 2 , MFLAGS, 0 , 7 , DFLAGS,1 ), 8 , GFLAGS),0 , "uart0_frac" , "uart0_src" , CLK_SET_RATE_PARENT,17 ), 0 ,1 ), 9 , GFLAGS,0 , "uart_src" , mux_pll_src_cpll_gpll_p, 0 ,13 ), 15 , 1 , MFLAGS),0 , "uart1_src" , "uart_src" , 0 ,14 ), 0 , 7 , DFLAGS,1 ), 10 , GFLAGS),0 , "uart1_frac" , "uart1_src" , CLK_SET_RATE_PARENT,18 ), 0 ,1 ), 11 , GFLAGS,0 , "uart2_src" , "uart_src" , 0 ,15 ), 0 , 7 , DFLAGS,1 ), 12 , GFLAGS),0 , "uart2_frac" , "uart2_src" , CLK_SET_RATE_PARENT,19 ), 0 ,1 ), 13 , GFLAGS,0 , "uart3_src" , "uart_src" , 0 ,16 ), 0 , 7 , DFLAGS,1 ), 14 , GFLAGS),0 , "uart3_frac" , "uart3_src" , CLK_SET_RATE_PARENT,20 ), 0 ,1 ), 15 , GFLAGS,0 , "uart4_src" , "uart_src" , 0 ,3 ), 0 , 7 , DFLAGS,2 ), 12 , GFLAGS),0 , "uart4_frac" , "uart4_src" , CLK_SET_RATE_PARENT,7 ), 0 ,2 ), 13 , GFLAGS,0 , "mac_pll_src" , mux_pll_src_npll_cpll_gpll_p, 0 ,21 ), 0 , 2 , MFLAGS, 8 , 5 , DFLAGS,2 ), 5 , GFLAGS),"mac_clk" , mux_mac_p, CLK_SET_RATE_PARENT,21 ), 4 , 1 , MFLAGS),"sclk_macref_out" , "mac_clk" , 0 ,5 ), 3 , GFLAGS),"sclk_macref" , "mac_clk" , 0 ,5 ), 2 , GFLAGS),"sclk_mac_rx" , "mac_clk" , 0 ,5 ), 0 , GFLAGS),"sclk_mac_tx" , "mac_clk" , 0 ,5 ), 1 , GFLAGS),0 , "hsadc_src" , mux_pll_src_cpll_gpll_p, 0 ,22 ), 0 , 1 , MFLAGS, 8 , 8 , DFLAGS,2 ), 6 , GFLAGS),0 , "sclk_hsadc_out" , mux_hsadcout_p, 0 ,22 ), 4 , 1 , MFLAGS),"sclk_hsadc" , "sclk_hsadc_out" ,22 ), 7 , IFLAGS),0 , "jtag" , "ext_jtag" , 0 ,4 ), 14 , GFLAGS),"usbphy480m_src" , mux_usbphy480m_p, 0 ,13 ), 11 , 2 , MFLAGS,5 ), 14 , GFLAGS),"sclk_hsicphy480m" , mux_hsicphy480m_p, 0 ,29 ), 0 , 2 , MFLAGS,3 ), 6 , GFLAGS),0 , "hsicphy12m_xin12m" , "xin12m" , 0 ,13 ), 9 , GFLAGS),0 , "hsicphy12m_usbphy" , "sclk_hsicphy480m" , 0 ,11 ), 8 , 6 , DFLAGS),"sclk_hsicphy12m" , mux_hsicphy12m_p, 0 ,22 ), 4 , 1 , MFLAGS),/* * Clock-Architecture Diagram 4 /* aclk_cpu gates */ 0 , "sclk_intmem0" , "aclk_cpu" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10 ), 5 , GFLAGS),0 , "sclk_intmem1" , "aclk_cpu" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10 ), 6 , GFLAGS),0 , "sclk_intmem2" , "aclk_cpu" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10 ), 7 , GFLAGS),"aclk_dmac1" , "aclk_cpu" , 0 , RK3288_CLKGATE_CON(10 ), 12 , GFLAGS),0 , "aclk_strc_sys" , "aclk_cpu" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10 ), 13 , GFLAGS),0 , "aclk_intmem" , "aclk_cpu" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10 ), 4 , GFLAGS),"aclk_crypto" , "aclk_cpu" , 0 , RK3288_CLKGATE_CON(11 ), 6 , GFLAGS),0 , "aclk_ccp" , "aclk_cpu" , 0 , RK3288_CLKGATE_CON(11 ), 8 , GFLAGS),/* hclk_cpu gates */ "hclk_crypto" , "hclk_cpu" , 0 , RK3288_CLKGATE_CON(11 ), 7 , GFLAGS),"hclk_i2s0" , "hclk_cpu" , 0 , RK3288_CLKGATE_CON(10 ), 8 , GFLAGS),"hclk_rom" , "hclk_cpu" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10 ), 9 , GFLAGS),"hclk_spdif" , "hclk_cpu" , 0 , RK3288_CLKGATE_CON(10 ), 10 , GFLAGS),"hclk_spdif_8ch" , "hclk_cpu" , 0 , RK3288_CLKGATE_CON(10 ), 11 , GFLAGS),/* pclk_cpu gates */ "pclk_pwm" , "pclk_cpu" , 0 , RK3288_CLKGATE_CON(10 ), 0 , GFLAGS),"pclk_timer" , "pclk_cpu" , 0 , RK3288_CLKGATE_CON(10 ), 1 , GFLAGS),"pclk_i2c0" , "pclk_cpu" , 0 , RK3288_CLKGATE_CON(10 ), 2 , GFLAGS),"pclk_i2c2" , "pclk_cpu" , 0 , RK3288_CLKGATE_CON(10 ), 3 , GFLAGS),"pclk_ddrupctl0" , "pclk_cpu" , 0 , RK3288_CLKGATE_CON(10 ), 14 , GFLAGS),"pclk_publ0" , "pclk_cpu" , 0 , RK3288_CLKGATE_CON(10 ), 15 , GFLAGS),"pclk_ddrupctl1" , "pclk_cpu" , 0 , RK3288_CLKGATE_CON(11 ), 0 , GFLAGS),"pclk_publ1" , "pclk_cpu" , 0 , RK3288_CLKGATE_CON(11 ), 1 , GFLAGS),"pclk_efuse_1024" , "pclk_cpu" , 0 , RK3288_CLKGATE_CON(11 ), 2 , GFLAGS),"pclk_tzpc" , "pclk_cpu" , 0 , RK3288_CLKGATE_CON(11 ), 3 , GFLAGS),"pclk_uart2" , "pclk_cpu" , 0 , RK3288_CLKGATE_CON(11 ), 9 , GFLAGS),"pclk_efuse_256" , "pclk_cpu" , 0 , RK3288_CLKGATE_CON(11 ), 10 , GFLAGS),"pclk_rkpwm" , "pclk_cpu" , 0 , RK3288_CLKGATE_CON(11 ), 11 , GFLAGS),/* ddrctrl [DDR Controller PHY clock] gates */ 0 , "nclk_ddrupctl0" , "ddrphy" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11 ), 4 , GFLAGS),0 , "nclk_ddrupctl1" , "ddrphy" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11 ), 5 , GFLAGS),/* ddrphy gates */ 0 , "sclk_ddrphy0" , "ddrphy" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4 ), 12 , GFLAGS),0 , "sclk_ddrphy1" , "ddrphy" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4 ), 13 , GFLAGS),/* aclk_peri gates */ 0 , "aclk_peri_axi_matrix" , "aclk_peri" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6 ), 2 , GFLAGS),"aclk_dmac2" , "aclk_peri" , 0 , RK3288_CLKGATE_CON(6 ), 3 , GFLAGS),0 , "aclk_peri_niu" , "aclk_peri" , 0 , RK3288_CLKGATE_CON(7 ), 11 , GFLAGS),"aclk_mmu" , "aclk_peri" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8 ), 12 , GFLAGS),"aclk_gmac" , "aclk_peri" , 0 , RK3288_CLKGATE_CON(8 ), 0 , GFLAGS),"hclk_gps" , "aclk_peri" , 0 , RK3288_CLKGATE_CON(8 ), 2 , GFLAGS),/* hclk_peri gates */ 0 , "hclk_peri_matrix" , "hclk_peri" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6 ), 0 , GFLAGS),"hclk_otg0" , "hclk_peri" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7 ), 4 , GFLAGS),"hclk_host0" , "hclk_peri" , 0 , RK3288_CLKGATE_CON(7 ), 6 , GFLAGS),"hclk_host1" , "hclk_peri" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7 ), 7 , GFLAGS),"hclk_hsic" , "hclk_peri" , 0 , RK3288_CLKGATE_CON(7 ), 8 , GFLAGS),0 , "hclk_usb_peri" , "hclk_peri" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7 ), 9 , GFLAGS),0 , "hclk_peri_ahb_arbi" , "hclk_peri" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7 ), 10 0 , "hclk_emem" , "hclk_peri" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7 ), 12 , GFLAGS),0 , "hclk_mem" , "hclk_peri" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7 ), 13 , GFLAGS),"hclk_nandc0" , "hclk_peri" , 0 , RK3288_CLKGATE_CON(7 ), 14 , GFLAGS),"hclk_nandc1" , "hclk_peri" , 0 , RK3288_CLKGATE_CON(7 ), 15 , GFLAGS),"hclk_tsp" , "hclk_peri" , 0 , RK3288_CLKGATE_CON(8 ), 8 , GFLAGS),"hclk_sdmmc" , "hclk_peri" , 0 , RK3288_CLKGATE_CON(8 ), 3 , GFLAGS),"hclk_sdio0" , "hclk_peri" , 0 , RK3288_CLKGATE_CON(8 ), 4 , GFLAGS),"hclk_sdio1" , "hclk_peri" , 0 , RK3288_CLKGATE_CON(8 ), 5 , GFLAGS),"hclk_emmc" , "hclk_peri" , 0 , RK3288_CLKGATE_CON(8 ), 6 , GFLAGS),"hclk_hsadc" , "hclk_peri" , 0 , RK3288_CLKGATE_CON(8 ), 7 , GFLAGS),0 , "pmu_hclk_otg0" , "hclk_peri" , 0 , RK3288_CLKGATE_CON(7 ), 5 , GFLAGS),/* pclk_peri gates */ 0 , "pclk_peri_matrix" , "pclk_peri" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6 ), 1 , GFLAGS),"pclk_spi0" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(6 ), 4 , GFLAGS),"pclk_spi1" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(6 ), 5 , GFLAGS),"pclk_spi2" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(6 ), 6 , GFLAGS),"pclk_ps2c" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(6 ), 7 , GFLAGS),"pclk_uart0" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(6 ), 8 , GFLAGS),"pclk_uart1" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(6 ), 9 , GFLAGS),"pclk_i2c4" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(6 ), 15 , GFLAGS),"pclk_uart3" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(6 ), 11 , GFLAGS),"pclk_uart4" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(6 ), 12 , GFLAGS),"pclk_i2c1" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(6 ), 13 , GFLAGS),"pclk_i2c3" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(6 ), 14 , GFLAGS),"pclk_saradc" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(7 ), 1 , GFLAGS),"pclk_tsadc" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(7 ), 2 , GFLAGS),"pclk_sim" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(7 ), 3 , GFLAGS),"pclk_i2c5" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(7 ), 0 , GFLAGS),"pclk_gmac" , "pclk_peri" , 0 , RK3288_CLKGATE_CON(8 ), 1 , GFLAGS),"sclk_lcdc_pwm0" , "xin24m" , 0 , RK3288_CLKGATE_CON(13 ), 10 , GFLAGS),"sclk_lcdc_pwm1" , "xin24m" , 0 , RK3288_CLKGATE_CON(13 ), 11 , GFLAGS),"sclk_pvtm_core" , "xin24m" , 0 , RK3288_CLKGATE_CON(5 ), 9 , GFLAGS),"sclk_pvtm_gpu" , "xin24m" , 0 , RK3288_CLKGATE_CON(5 ), 10 , GFLAGS),"sclk_mipidsi_24m" , "xin24m" , 0 , RK3288_CLKGATE_CON(5 ), 15 , GFLAGS),/* sclk_gpu gates */ "aclk_gpu" , "sclk_gpu" , 0 , RK3288_CLKGATE_CON(18 ), 0 , GFLAGS),/* pclk_pd_alive gates */ "pclk_gpio8" , "pclk_pd_alive" , 0 , RK3288_CLKGATE_CON(14 ), 8 , GFLAGS),"pclk_gpio7" , "pclk_pd_alive" , 0 , RK3288_CLKGATE_CON(14 ), 7 , GFLAGS),"pclk_gpio1" , "pclk_pd_alive" , 0 , RK3288_CLKGATE_CON(14 ), 1 , GFLAGS),"pclk_gpio2" , "pclk_pd_alive" , 0 , RK3288_CLKGATE_CON(14 ), 2 , GFLAGS),"pclk_gpio3" , "pclk_pd_alive" , 0 , RK3288_CLKGATE_CON(14 ), 3 , GFLAGS),"pclk_gpio4" , "pclk_pd_alive" , 0 , RK3288_CLKGATE_CON(14 ), 4 , GFLAGS),"pclk_gpio5" , "pclk_pd_alive" , 0 , RK3288_CLKGATE_CON(14 ), 5 , GFLAGS),"pclk_gpio6" , "pclk_pd_alive" , 0 , RK3288_CLKGATE_CON(14 ), 6 , GFLAGS),"pclk_grf" , "pclk_pd_alive" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14 ), 11 , GFLAGS),0 , "pclk_alive_niu" , "pclk_pd_alive" , 0 , RK3288_CLKGATE_CON(14 ), 12 , GFLAGS),/* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */ "pclk_wdt" , "pclk_pd_alive" ),/* pclk_pd_pmu gates */ "pclk_pmu" , "pclk_pd_pmu" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17 ), 0 0 , "pclk_intmem1" , "pclk_pd_pmu" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17 ), 1 , GFLAGS),0 , "pclk_pmu_niu" , "pclk_pd_pmu" , 0 , RK3288_CLKGATE_CON(17 ), 2 , GFLAGS),"pclk_sgrf" , "pclk_pd_pmu" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17 ), 3 , GFLAGS),"pclk_gpio0" , "pclk_pd_pmu" , 0 , RK3288_CLKGATE_CON(17 ), 4 , GFLAGS),/* hclk_vio gates */ "hclk_rga" , "hclk_vio" , 0 , RK3288_CLKGATE_CON(15 ), 1 , GFLAGS),"hclk_vop0" , "hclk_vio" , 0 , RK3288_CLKGATE_CON(15 ), 6 , GFLAGS),"hclk_vop1" , "hclk_vio" , 0 , RK3288_CLKGATE_CON(15 ), 8 , GFLAGS),"hclk_vio_ahb_arbi" , "hclk_vio" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15 ), 9 , GFLAGS),"hclk_vio_niu" , "hclk_vio" , 0 , RK3288_CLKGATE_CON(15 ), 10 , GFLAGS),"hclk_vip" , "hclk_vio" , 0 , RK3288_CLKGATE_CON(15 ), 15 , GFLAGS),"hclk_iep" , "hclk_vio" , 0 , RK3288_CLKGATE_CON(15 ), 3 , GFLAGS),"hclk_isp" , "hclk_vio" , 0 , RK3288_CLKGATE_CON(16 ), 1 , GFLAGS),"hclk_vio2_h2p" , "hclk_vio" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16 ), 10 , GFLAGS),"pclk_mipi_dsi0" , "hclk_vio" , 0 , RK3288_CLKGATE_CON(16 ), 4 , GFLAGS),"pclk_mipi_dsi1" , "hclk_vio" , 0 , RK3288_CLKGATE_CON(16 ), 5 , GFLAGS),"pclk_mipi_csi" , "hclk_vio" , 0 , RK3288_CLKGATE_CON(16 ), 6 , GFLAGS),"pclk_lvds_phy" , "hclk_vio" , 0 , RK3288_CLKGATE_CON(16 ), 7 , GFLAGS),"pclk_edp_ctrl" , "hclk_vio" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16 ), 8 , GFLAGS),"pclk_hdmi_ctrl" , "hclk_vio" , 0 , RK3288_CLKGATE_CON(16 ), 9 , GFLAGS),"pclk_vio2_h2p" , "hclk_vio" , CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16 ), 11 , GFLAGS),/* aclk_vio0 gates */ "aclk_vop0" , "aclk_vio0" , 0 , RK3288_CLKGATE_CON(15 ), 5 , GFLAGS),"aclk_iep" , "aclk_vio0" , 0 , RK3288_CLKGATE_CON(15 ), 2 , GFLAGS),"aclk_vio0_niu" , "aclk_vio0" , 0 , RK3288_CLKGATE_CON(15 ), 11 , GFLAGS),"aclk_vip" , "aclk_vio0" , 0 , RK3288_CLKGATE_CON(15 ), 14 , GFLAGS),/* aclk_vio1 gates */ "aclk_vop1" , "aclk_vio1" , 0 , RK3288_CLKGATE_CON(15 ), 7 , GFLAGS),"aclk_isp" , "aclk_vio1" , 0 , RK3288_CLKGATE_CON(16 ), 2 , GFLAGS),"aclk_vio1_niu" , "aclk_vio1" , 0 , RK3288_CLKGATE_CON(15 ), 12 , GFLAGS),/* aclk_rga_pre gates */ "aclk_rga" , "aclk_rga_pre" , 0 , RK3288_CLKGATE_CON(15 ), 0 , GFLAGS),"aclk_rga_niu" , "aclk_rga_pre" , 0 , RK3288_CLKGATE_CON(15 ), 13 , GFLAGS),/* * Other ungrouped clocks. 0 , "pclk_vip_in" , "ext_vip" , 0 , RK3288_CLKGATE_CON(16 ), 0 , GFLAGS),0 , "pclk_vip" , "pclk_vip_in" , RK3288_CLKSEL_CON(29 ), 4 , IFLAGS),"pclk_isp_in" , "ext_isp" , 0 , RK3288_CLKGATE_CON(16 ), 3 , GFLAGS),0 , "pclk_isp" , "pclk_isp_in" , RK3288_CLKSEL_CON(29 ), 3 , IFLAGS),static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {0 , "hclk_vio" , "aclk_vio1" , 0 ,28 ), 8 , 5 , DFLAGS),static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {0 , "hclk_vio" , "aclk_vio0" , 0 ,28 ), 8 , 5 , DFLAGS),static const char *const rk3288_critical_clocks[] __initconst = {"aclk_cpu" ,"aclk_peri" ,"aclk_peri_niu" ,"aclk_vio0_niu" ,"aclk_vio1_niu" ,"aclk_rga_niu" ,"hclk_peri" ,"hclk_vio_niu" ,"pclk_alive_niu" ,"pclk_pd_pmu" ,"pclk_pmu_niu" ,"pmu_hclk_otg0" ,/* pwm-regulators on some boards, so handoff-critical later */ "pclk_rkpwm" ,static void __iomem *rk3288_cru_base;/* * Some CRU registers will be reset in maskrom when the system * wakes up from fastboot. * So save them before suspend, restore them after resume. static const int rk3288_saved_cru_reg_ids[] = {0 ),1 ),10 ),33 ),37 ),/* We turn aclk_dmac1 on for suspend; this will restore it */ 10 ),static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];static int rk3288_clk_suspend(void )int i, reg_id;for (i = 0 ; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {/* * Going into deep sleep (specifically setting PMU_CLR_DMA in * RK3288_PMU_PWRMODE_CON1) appears to fail unless * "aclk_dmac1" is on. 1 << (12 + 16 ),10 ));/* * Switch PLLs other than DPLL (for SDRAM) to slow mode to * avoid crashes on resume. The Mask ROM on the system will * put APLL, CPLL, and GPLL into slow mode at resume time * anyway (which is why we restore them), but we might not * even make it to the Mask ROM if this isn't done at suspend * time. * * NOTE: only APLL truly matters here, but we'll do them all. 0 xf3030000, rk3288_cru_base + RK3288_MODE_CON);return 0 ;static void rk3288_clk_resume(void )int i, reg_id;for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1 ; i >= 0 ; i--) {0 xffff0000,static void rk3288_clk_shutdown(void )0 xf3030000, rk3288_cru_base + RK3288_MODE_CON);static struct syscore_ops rk3288_clk_syscore_ops = {static void __init rk3288_common_init(struct device_node *np,enum rk3288_variant soc)struct rockchip_clk_provider *ctx;unsigned long clk_nr_clks;0 );if (!rk3288_cru_base) {"%s: could not map cru region\n" , __func__);return ;1 ;if (IS_ERR(ctx)) {"%s: rockchip clk init failed\n" , __func__);return ;if (soc == RK3288W_CRU)else "armclk" ,12 ,0 ),static void __init rk3288_clk_init(struct device_node *np)"rockchip,rk3288-cru" , rk3288_clk_init);static void __init rk3288w_clk_init(struct device_node *np)"rockchip,rk3288w-cru" , rk3288w_clk_init);
Messung V0.5 in Prozent C=97 H=94 G=95
