// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) 2018 Rockchip Electronics Co. Ltd. * Author: Elaine Zhang<zhangqing@rock-chips.com> #include <linux/clk-provider.h>#include <linux/io.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/syscore_ops.h>#include <dt-bindings/clock/px30-cru.h>#include "clk.h" #define PX30_GRF_SOC_STATUS0 0 x480enum px30_plls {enum px30_pmu_plls {static struct rockchip_pll_rate_table px30_pll_rates[] = {/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 1608000000 , 1 , 67 , 1 , 1 , 1 , 0 ),1584000000 , 1 , 66 , 1 , 1 , 1 , 0 ),1560000000 , 1 , 65 , 1 , 1 , 1 , 0 ),1536000000 , 1 , 64 , 1 , 1 , 1 , 0 ),1512000000 , 1 , 63 , 1 , 1 , 1 , 0 ),1488000000 , 1 , 62 , 1 , 1 , 1 , 0 ),1464000000 , 1 , 61 , 1 , 1 , 1 , 0 ),1440000000 , 1 , 60 , 1 , 1 , 1 , 0 ),1416000000 , 1 , 59 , 1 , 1 , 1 , 0 ),1392000000 , 1 , 58 , 1 , 1 , 1 , 0 ),1368000000 , 1 , 57 , 1 , 1 , 1 , 0 ),1344000000 , 1 , 56 , 1 , 1 , 1 , 0 ),1320000000 , 1 , 55 , 1 , 1 , 1 , 0 ),1296000000 , 1 , 54 , 1 , 1 , 1 , 0 ),1272000000 , 1 , 53 , 1 , 1 , 1 , 0 ),1248000000 , 1 , 52 , 1 , 1 , 1 , 0 ),1200000000 , 1 , 50 , 1 , 1 , 1 , 0 ),1188000000 , 2 , 99 , 1 , 1 , 1 , 0 ),1104000000 , 1 , 46 , 1 , 1 , 1 , 0 ),1100000000 , 12 , 550 , 1 , 1 , 1 , 0 ),1008000000 , 1 , 84 , 2 , 1 , 1 , 0 ),1000000000 , 6 , 500 , 2 , 1 , 1 , 0 ),984000000 , 1 , 82 , 2 , 1 , 1 , 0 ),960000000 , 1 , 80 , 2 , 1 , 1 , 0 ),936000000 , 1 , 78 , 2 , 1 , 1 , 0 ),912000000 , 1 , 76 , 2 , 1 , 1 , 0 ),900000000 , 4 , 300 , 2 , 1 , 1 , 0 ),888000000 , 1 , 74 , 2 , 1 , 1 , 0 ),864000000 , 1 , 72 , 2 , 1 , 1 , 0 ),840000000 , 1 , 70 , 2 , 1 , 1 , 0 ),816000000 , 1 , 68 , 2 , 1 , 1 , 0 ),800000000 , 6 , 400 , 2 , 1 , 1 , 0 ),700000000 , 6 , 350 , 2 , 1 , 1 , 0 ),696000000 , 1 , 58 , 2 , 1 , 1 , 0 ),624000000 , 1 , 52 , 2 , 1 , 1 , 0 ),600000000 , 1 , 75 , 3 , 1 , 1 , 0 ),594000000 , 2 , 99 , 2 , 1 , 1 , 0 ),504000000 , 1 , 63 , 3 , 1 , 1 , 0 ),500000000 , 6 , 250 , 2 , 1 , 1 , 0 ),408000000 , 1 , 68 , 2 , 2 , 1 , 0 ),312000000 , 1 , 52 , 2 , 2 , 1 , 0 ),216000000 , 1 , 72 , 4 , 2 , 1 , 0 ),96000000 , 1 , 64 , 4 , 4 , 1 , 0 ),/* sentinel */ }, #define PX30_DIV_ACLKM_MASK 0 x7#define PX30_DIV_ACLKM_SHIFT 12 #define PX30_DIV_PCLK_DBG_MASK 0 xf#define PX30_DIV_PCLK_DBG_SHIFT 8 #define PX30_CLKSEL0(_aclk_core, _pclk_dbg) \0 ), \#define PX30_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = {1608000000 , 1 , 7 ),1584000000 , 1 , 7 ),1560000000 , 1 , 7 ),1536000000 , 1 , 7 ),1512000000 , 1 , 7 ),1488000000 , 1 , 5 ),1464000000 , 1 , 5 ),1440000000 , 1 , 5 ),1416000000 , 1 , 5 ),1392000000 , 1 , 5 ),1368000000 , 1 , 5 ),1344000000 , 1 , 5 ),1320000000 , 1 , 5 ),1296000000 , 1 , 5 ),1272000000 , 1 , 5 ),1248000000 , 1 , 5 ),1224000000 , 1 , 5 ),1200000000 , 1 , 5 ),1104000000 , 1 , 5 ),1008000000 , 1 , 5 ),912000000 , 1 , 5 ),816000000 , 1 , 3 ),696000000 , 1 , 3 ),600000000 , 1 , 3 ),408000000 , 1 , 1 ),312000000 , 1 , 1 ),216000000 , 1 , 1 ),96000000 , 1 , 1 ),static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = {0 ] = PX30_CLKSEL_CON(0 ),0 ] = 0 ,0 ] = 0 xf,1 ,1 ,0 ,7 ,0 x1,"xin24m" };"xin24m" , "usb480m_phy" , "clk_rtc32k_pmu" };"apll_core" , "gpll_core" };"dpll_ddr" , "gpll_ddr" };"clk_ddrphy1x" , "clk_stdby_2wrap" };"gpll" , "dummy_cpll" , "usb480m" , "npll" };"cpll" , "npll" };"npll" , "cpll" };"gpll" , "dummy_cpll" };"gpll" , "npll" };"gpll" , "xin24m" };"gpll" , "dummy_cpll" , "npll" };"gpll" , "dummy_cpll" , "npll" , "xin24m" };"gpll" , "xin24m" , "npll" };"clk_pdm_src" , "clk_pdm_frac" };"clk_i2s0_tx_src" , "clk_i2s0_tx_frac" , "mclk_i2s0_tx_in" , "xin12m" };"clk_i2s0_rx_src" , "clk_i2s0_rx_frac" , "mclk_i2s0_rx_in" , "xin12m" };"clk_i2s1_src" , "clk_i2s1_frac" , "i2s1_clkin" , "xin12m" };"clk_i2s2_src" , "clk_i2s2_frac" , "i2s2_clkin" , "xin12m" };"clk_i2s0_tx" , "xin12m" , "clk_i2s0_rx" };"clk_i2s0_rx" , "xin12m" , "clk_i2s0_tx" };"clk_i2s1" , "xin12m" };"clk_i2s2" , "xin12m" };"clk_i2s0_tx_mux" , "clk_i2s0_rx_mux" };"clk_i2s0_rx_mux" , "clk_i2s0_tx_mux" };"gpll" , "xin24m" , "usb480m" , "npll" };"clk_uart1_src" , "clk_uart1_np5" , "clk_uart1_frac" };"clk_uart2_src" , "clk_uart2_np5" , "clk_uart2_frac" };"clk_uart3_src" , "clk_uart3_np5" , "clk_uart3_frac" };"clk_uart4_src" , "clk_uart4_np5" , "clk_uart4_frac" };"clk_uart5_src" , "clk_uart5_np5" , "clk_uart5_frac" };"xin24m" , "dummy_cpll" , "npll" , "usb480m" };"dclk_vopb_src" , "dclk_vopb_frac" , "xin24m" };"dclk_vopl_src" , "dclk_vopl_frac" , "xin24m" };"clk_nandc_div" , "clk_nandc_div50" };"clk_sdio_div" , "clk_sdio_div50" };"clk_emmc_div" , "clk_emmc_div50" };"clk_sdmmc_div" , "clk_sdmmc_div50" };"clk_gmac_src" , "gmac_clkin" };"clk_gmac_rx_tx_div20" , "clk_gmac_rx_tx_div2" };"xin32k" , "pmu_pvtm_32k" , "clk_rtc32k_frac" , };"xin24m" , "clk_wifi_pmu_src" };"clk_uart0_pmu_src" , "clk_uart0_np5" , "clk_uart0_frac" };"xin24m" , "clk_ref24m_pmu" };"xin24m" , "clk_ref24m_pmu" };"clk_gpu_div" , "clk_gpu_np5" };static struct rockchip_pll_clock px30_pll_clks[] __initdata = {"apll" , mux_pll_p,0 , PX30_PLL_CON(0 ),0 , 0 , 0 , px30_pll_rates),"dpll" , mux_pll_p,0 , PX30_PLL_CON(8 ),4 , 1 , 0 , NULL),"cpll" , mux_pll_p,0 , PX30_PLL_CON(16 ),2 , 2 , 0 , px30_pll_rates),"npll" , mux_pll_p,0 , PX30_PLL_CON(24 ),6 , 4 , 0 , px30_pll_rates),static struct rockchip_pll_clock px30_pmu_pll_clks[] __initdata = {"gpll" , mux_pll_p, 0 , PX30_PMU_PLL_CON(0 ),0 , 3 , 0 , px30_pll_rates),#define MFLAGS CLK_MUX_HIWORD_MASK#define DFLAGS CLK_DIVIDER_HIWORD_MASK#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)static struct rockchip_clk_branch px30_pdm_fracmux __initdata =0 , "clk_pdm_mux" , mux_pdm_p, CLK_SET_RATE_PARENT,26 ), 15 , 1 , MFLAGS);static struct rockchip_clk_branch px30_i2s0_tx_fracmux __initdata =0 , "clk_i2s0_tx_mux" , mux_i2s0_tx_p, CLK_SET_RATE_PARENT,28 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch px30_i2s0_rx_fracmux __initdata =0 , "clk_i2s0_rx_mux" , mux_i2s0_rx_p, CLK_SET_RATE_PARENT,58 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch px30_i2s1_fracmux __initdata =0 , "clk_i2s1_mux" , mux_i2s1_p, CLK_SET_RATE_PARENT,30 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch px30_i2s2_fracmux __initdata =0 , "clk_i2s2_mux" , mux_i2s2_p, CLK_SET_RATE_PARENT,32 ), 10 , 2 , MFLAGS);static struct rockchip_clk_branch px30_uart1_fracmux __initdata =0 , "clk_uart1_mux" , mux_uart1_p, CLK_SET_RATE_PARENT,35 ), 14 , 2 , MFLAGS);static struct rockchip_clk_branch px30_uart2_fracmux __initdata =0 , "clk_uart2_mux" , mux_uart2_p, CLK_SET_RATE_PARENT,38 ), 14 , 2 , MFLAGS);static struct rockchip_clk_branch px30_uart3_fracmux __initdata =0 , "clk_uart3_mux" , mux_uart3_p, CLK_SET_RATE_PARENT,41 ), 14 , 2 , MFLAGS);static struct rockchip_clk_branch px30_uart4_fracmux __initdata =0 , "clk_uart4_mux" , mux_uart4_p, CLK_SET_RATE_PARENT,44 ), 14 , 2 , MFLAGS);static struct rockchip_clk_branch px30_uart5_fracmux __initdata =0 , "clk_uart5_mux" , mux_uart5_p, CLK_SET_RATE_PARENT,47 ), 14 , 2 , MFLAGS);static struct rockchip_clk_branch px30_dclk_vopb_fracmux __initdata =0 , "dclk_vopb_mux" , mux_dclk_vopb_p, CLK_SET_RATE_PARENT,5 ), 14 , 2 , MFLAGS);static struct rockchip_clk_branch px30_dclk_vopl_fracmux __initdata =0 , "dclk_vopl_mux" , mux_dclk_vopl_p, CLK_SET_RATE_PARENT,8 ), 14 , 2 , MFLAGS);static struct rockchip_clk_branch px30_rtc32k_pmu_fracmux __initdata ="clk_rtc32k_pmu" , mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT,0 ), 14 , 2 , MFLAGS);static struct rockchip_clk_branch px30_uart0_pmu_fracmux __initdata =0 , "clk_uart0_pmu_mux" , mux_uart0_pmu_p, CLK_SET_RATE_PARENT,4 ), 14 , 2 , MFLAGS);static struct rockchip_clk_branch px30_clk_branches[] __initdata = {/* * Clock-Architecture Diagram 1 "usb480m" , mux_usb480m_p, CLK_SET_RATE_PARENT,8 , 2 , MFLAGS),0 , "xin12m" , "xin24m" , 0 , 1 , 2 ),/* * Clock-Architecture Diagram 3 /* PD_CORE */ 0 , "apll_core" , "apll" , CLK_IGNORE_UNUSED,0 ), 0 , GFLAGS),0 , "gpll_core" , "gpll" , CLK_IGNORE_UNUSED,0 ), 0 , GFLAGS),0 , "pclk_dbg" , "armclk" , CLK_IGNORE_UNUSED,0 ), 8 , 4 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 2 , GFLAGS),0 , "aclk_core" , "armclk" , CLK_IGNORE_UNUSED,0 ), 12 , 3 , DFLAGS | CLK_DIVIDER_READ_ONLY,0 ), 1 , GFLAGS),0 , "aclk_core_niu" , "aclk_core" , CLK_IGNORE_UNUSED,0 ), 4 , GFLAGS),0 , "aclk_core_prf" , "aclk_core" , CLK_IGNORE_UNUSED,17 ), 5 , GFLAGS),0 , "pclk_dbg_niu" , "pclk_dbg" , CLK_IGNORE_UNUSED,0 ), 5 , GFLAGS),0 , "pclk_core_dbg" , "pclk_dbg" , CLK_IGNORE_UNUSED,0 ), 6 , GFLAGS),0 , "pclk_core_grf" , "pclk_dbg" , CLK_IGNORE_UNUSED,17 ), 6 , GFLAGS),0 , "clk_jtag" , "jtag_clkin" , CLK_IGNORE_UNUSED,0 ), 3 , GFLAGS),"clk_pvtm" , "xin24m" , 0 ,17 ), 4 , GFLAGS),/* PD_GPU */ 0 , "clk_gpu_src" , mux_4plls_p, 0 ,1 ), 6 , 2 , MFLAGS,0 ), 8 , GFLAGS),0 , "clk_gpu_div" , "clk_gpu_src" , 0 ,1 ), 0 , 4 , DFLAGS,0 ), 12 , GFLAGS),0 , "clk_gpu_np5" , "clk_gpu_src" , 0 ,1 ), 8 , 4 , DFLAGS,0 ), 9 , GFLAGS),"clk_gpu" , mux_gpu_p, CLK_SET_RATE_PARENT,1 ), 15 , 1 , MFLAGS,0 ), 10 , GFLAGS),0 , "aclk_gpu" , "clk_gpu" , CLK_IGNORE_UNUSED,1 ), 13 , 2 , DFLAGS,17 ), 10 , GFLAGS),0 , "aclk_gpu_niu" , "aclk_gpu" , CLK_IGNORE_UNUSED,0 ), 11 , GFLAGS),0 , "aclk_gpu_prf" , "aclk_gpu" , CLK_IGNORE_UNUSED,17 ), 8 , GFLAGS),0 , "pclk_gpu_grf" , "aclk_gpu" , CLK_IGNORE_UNUSED,17 ), 9 , GFLAGS),/* * Clock-Architecture Diagram 4 /* PD_DDR */ 0 , "dpll_ddr" , "dpll" , CLK_IGNORE_UNUSED,0 ), 7 , GFLAGS),0 , "gpll_ddr" , "gpll" , CLK_IGNORE_UNUSED,0 ), 13 , GFLAGS),"sclk_ddrc" , mux_ddrphy_p, CLK_IGNORE_UNUSED,2 ), 7 , 1 , MFLAGS, 0 , 3 , DFLAGS | CLK_DIVIDER_POWER_OF_TWO),0 , "clk_ddrphy4x" , mux_ddrphy_p, CLK_IGNORE_UNUSED,2 ), 7 , 1 , MFLAGS, 0 , 3 , DFLAGS),0 , "clk_ddrphy1x" , "clk_ddrphy4x" , CLK_IGNORE_UNUSED, 1 , 4 ,0 ), 14 , GFLAGS),0 , "clk_stdby_2wrap" , "clk_ddrphy4x" , CLK_IGNORE_UNUSED, 1 , 4 ,1 ), 0 , GFLAGS),0 , "clk_ddrstdby" , mux_ddrstdby_p, CLK_IGNORE_UNUSED,2 ), 4 , 1 , MFLAGS,1 ), 13 , GFLAGS),0 , "aclk_split" , "clk_ddrphy1x" , CLK_IGNORE_UNUSED,1 ), 15 , GFLAGS),0 , "clk_msch" , "clk_ddrphy1x" , CLK_IGNORE_UNUSED,1 ), 8 , GFLAGS),0 , "aclk_ddrc" , "clk_ddrphy1x" , CLK_IGNORE_UNUSED,1 ), 5 , GFLAGS),0 , "clk_core_ddrc" , "clk_ddrphy1x" , CLK_IGNORE_UNUSED,1 ), 6 , GFLAGS),0 , "aclk_cmd_buff" , "clk_ddrphy1x" , CLK_IGNORE_UNUSED,1 ), 6 , GFLAGS),0 , "clk_ddrmon" , "clk_ddrphy1x" , CLK_IGNORE_UNUSED,1 ), 11 , GFLAGS),0 , "clk_ddrmon_timer" , "xin24m" , CLK_IGNORE_UNUSED,0 ), 15 , GFLAGS),"pclk_ddr" , "gpll" , CLK_IGNORE_UNUSED,2 ), 8 , 5 , DFLAGS,1 ), 1 , GFLAGS),0 , "pclk_ddrmon" , "pclk_ddr" , CLK_IGNORE_UNUSED,1 ), 10 , GFLAGS),0 , "pclk_ddrc" , "pclk_ddr" , CLK_IGNORE_UNUSED,1 ), 7 , GFLAGS),0 , "pclk_msch" , "pclk_ddr" , CLK_IGNORE_UNUSED,1 ), 9 , GFLAGS),0 , "pclk_stdby" , "pclk_ddr" , CLK_IGNORE_UNUSED,1 ), 12 , GFLAGS),0 , "pclk_ddr_grf" , "pclk_ddr" , CLK_IGNORE_UNUSED,1 ), 14 , GFLAGS),0 , "pclk_cmdbuff" , "pclk_ddr" , CLK_IGNORE_UNUSED,1 ), 3 , GFLAGS),/* * Clock-Architecture Diagram 5 /* PD_VI */ "aclk_vi_pre" , mux_gpll_cpll_npll_p, 0 ,11 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,4 ), 8 , GFLAGS),"hclk_vi_pre" , "aclk_vi_pre" , 0 ,11 ), 8 , 4 , DFLAGS,4 ), 12 , GFLAGS),"clk_isp" , mux_gpll_cpll_npll_p, 0 ,12 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,4 ), 9 , GFLAGS),"clk_cif_out" , mux_cif_out_p, 0 ,13 ), 6 , 2 , MFLAGS, 0 , 6 , DFLAGS,4 ), 11 , GFLAGS),"pclkin_isp" , "ext_pclkin" , 0 ,4 ), 13 , GFLAGS),"pclkin_cif" , "ext_pclkin" , 0 ,4 ), 14 , GFLAGS),/* * Clock-Architecture Diagram 6 /* PD_VO */ "aclk_vo_pre" , mux_gpll_cpll_npll_p, 0 ,3 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,2 ), 0 , GFLAGS),"hclk_vo_pre" , "aclk_vo_pre" , 0 ,3 ), 8 , 4 , DFLAGS,2 ), 12 , GFLAGS),"pclk_vo_pre" , "aclk_vo_pre" , 0 ,3 ), 12 , 4 , DFLAGS,2 ), 13 , GFLAGS),"clk_rga_core" , mux_gpll_cpll_npll_p, 0 ,4 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,2 ), 1 , GFLAGS),"clk_vopb_pwm" , mux_gpll_xin24m_p, 0 ,7 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,2 ), 5 , GFLAGS),0 , "dclk_vopb_src" , mux_cpll_npll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,5 ), 11 , 1 , MFLAGS, 0 , 8 , DFLAGS,2 ), 2 , GFLAGS),0 , "dclk_vopb_frac" , "dclk_vopb_src" , CLK_SET_RATE_PARENT,6 ), 0 ,2 ), 3 , GFLAGS,"dclk_vopb" , "dclk_vopb_mux" , CLK_SET_RATE_PARENT,2 ), 4 , GFLAGS),0 , "dclk_vopl_src" , mux_npll_cpll_p, 0 ,8 ), 11 , 1 , MFLAGS, 0 , 8 , DFLAGS,2 ), 6 , GFLAGS),0 , "dclk_vopl_frac" , "dclk_vopl_src" , CLK_SET_RATE_PARENT,9 ), 0 ,2 ), 7 , GFLAGS,"dclk_vopl" , "dclk_vopl_mux" , CLK_SET_RATE_PARENT,2 ), 8 , GFLAGS),/* PD_VPU */ 0 , "aclk_vpu_pre" , mux_gpll_cpll_npll_p, 0 ,10 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,4 ), 0 , GFLAGS),0 , "hclk_vpu_pre" , "aclk_vpu_pre" , 0 ,10 ), 8 , 4 , DFLAGS,4 ), 2 , GFLAGS),"sclk_core_vpu" , mux_gpll_cpll_npll_p, 0 ,13 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,4 ), 1 , GFLAGS),/* * Clock-Architecture Diagram 7 "aclk_peri_src" , mux_gpll_cpll_p, 0 ,14 ), 15 , 1 , MFLAGS,5 ), 7 , GFLAGS),"aclk_peri_pre" , "aclk_peri_src" , CLK_IGNORE_UNUSED,14 ), 0 , 5 , DFLAGS,5 ), 8 , GFLAGS),"hclk_peri_pre" , "aclk_peri_src" , CLK_IGNORE_UNUSED,14 ), 8 , 5 , DFLAGS),/* PD_MMC_NAND */ "hclk_mmc_nand" , "hclk_peri_pre" , 0 ,6 ), 0 , GFLAGS),"clk_nandc_div" , mux_gpll_cpll_npll_p, 0 ,15 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,5 ), 11 , GFLAGS),"clk_nandc_div50" , mux_gpll_cpll_npll_p, 0 ,15 ), 6 , 2 , MFLAGS, 8 , 5 , DFLAGS,5 ), 12 , GFLAGS),"clk_nandc" , mux_nandc_p,15 ), 15 , 1 , MFLAGS,5 ), 13 , GFLAGS),"clk_sdio_div" , mux_gpll_cpll_npll_xin24m_p, 0 ,18 ), 14 , 2 , MFLAGS, 0 , 8 , DFLAGS,6 ), 1 , GFLAGS),"clk_sdio_div50" ,0 ,18 ), 14 , 2 , MFLAGS,19 ), 0 , 8 , DFLAGS,6 ), 2 , GFLAGS),"clk_sdio" , mux_sdio_p,19 ), 15 , 1 , MFLAGS,6 ), 3 , GFLAGS),"clk_emmc_div" , mux_gpll_cpll_npll_xin24m_p, 0 ,20 ), 14 , 2 , MFLAGS, 0 , 8 , DFLAGS,6 ), 4 , GFLAGS),"clk_emmc_div50" , mux_gpll_cpll_npll_xin24m_p, 0 ,20 ), 14 , 2 , MFLAGS,21 ), 0 , 8 , DFLAGS,6 ), 5 , GFLAGS),"clk_emmc" , mux_emmc_p,21 ), 15 , 1 , MFLAGS,6 ), 6 , GFLAGS),"clk_sfc" , mux_gpll_cpll_p, 0 ,22 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,6 ), 7 , GFLAGS),"sdmmc_drv" , "clk_sdmmc" ,1 ),"sdmmc_sample" , "clk_sdmmc" ,1 ),"sdio_drv" , "clk_sdio" ,1 ),"sdio_sample" , "clk_sdio" ,1 ),"emmc_drv" , "clk_emmc" ,1 ),"emmc_sample" , "clk_emmc" ,1 ),/* PD_SDCARD */ 0 , "hclk_sdmmc_pre" , "hclk_peri_pre" , 0 ,6 ), 12 , GFLAGS),"clk_sdmmc_div" , mux_gpll_cpll_npll_xin24m_p, 0 ,16 ), 14 , 2 , MFLAGS, 0 , 8 , DFLAGS,6 ), 13 , GFLAGS),"clk_sdmmc_div50" , mux_gpll_cpll_npll_xin24m_p, 0 ,16 ), 14 , 2 , MFLAGS,17 ), 0 , 8 , DFLAGS,6 ), 14 , GFLAGS),"clk_sdmmc" , mux_sdmmc_p,17 ), 15 , 1 , MFLAGS,6 ), 15 , GFLAGS),/* PD_USB */ "hclk_usb" , "hclk_peri_pre" , 0 ,7 ), 2 , GFLAGS),"clk_otg_adp" , "clk_rtc32k_pmu" , 0 ,7 ), 3 , GFLAGS),/* PD_GMAC */ "clk_gmac_src" , mux_gpll_cpll_npll_p, 0 ,22 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,7 ), 11 , GFLAGS),"clk_gmac" , mux_gmac_p, CLK_SET_RATE_PARENT,23 ), 6 , 1 , MFLAGS),"clk_mac_ref" , "clk_gmac" , 0 ,7 ), 15 , GFLAGS),"clk_gmac_rx_tx" , "clk_gmac" , 0 ,7 ), 13 , GFLAGS),0 , "clk_gmac_rx_tx_div2" , "clk_gmac_rx_tx" , 0 , 1 , 2 ),0 , "clk_gmac_rx_tx_div20" , "clk_gmac_rx_tx" , 0 , 1 , 20 ),"clk_gmac_rmii_sel" , mux_gmac_rmii_sel_p, CLK_SET_RATE_PARENT,23 ), 7 , 1 , MFLAGS),0 , "aclk_gmac_pre" , "aclk_peri_pre" , 0 ,7 ), 10 , GFLAGS),0 , "pclk_gmac_pre" , "aclk_gmac_pre" , 0 ,23 ), 0 , 4 , DFLAGS,7 ), 12 , GFLAGS),"clk_mac_out" , mux_gpll_cpll_npll_p, 0 ,12 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,8 ), 5 , GFLAGS),/* * Clock-Architecture Diagram 8 /* PD_BUS */ "aclk_bus_src" , mux_gpll_cpll_p, CLK_IGNORE_UNUSED,23 ), 15 , 1 , MFLAGS,8 ), 6 , GFLAGS),"hclk_bus_pre" , "aclk_bus_src" , CLK_IGNORE_UNUSED,24 ), 0 , 5 , DFLAGS,8 ), 8 , GFLAGS),"aclk_bus_pre" , "aclk_bus_src" , CLK_IGNORE_UNUSED,23 ), 8 , 5 , DFLAGS,8 ), 7 , GFLAGS),"pclk_bus_pre" , "aclk_bus_pre" , CLK_IGNORE_UNUSED,24 ), 8 , 2 , DFLAGS,8 ), 9 , GFLAGS),0 , "pclk_top_pre" , "pclk_bus_pre" , CLK_IGNORE_UNUSED,8 ), 10 , GFLAGS),0 , "clk_pdm_src" , mux_gpll_xin24m_npll_p, 0 ,26 ), 8 , 2 , MFLAGS, 0 , 7 , DFLAGS,9 ), 9 , GFLAGS),0 , "clk_pdm_frac" , "clk_pdm_src" , CLK_SET_RATE_PARENT,27 ), 0 ,9 ), 10 , GFLAGS,"clk_pdm" , "clk_pdm_mux" , CLK_SET_RATE_PARENT,9 ), 11 , GFLAGS),0 , "clk_i2s0_tx_src" , mux_gpll_npll_p, 0 ,28 ), 8 , 1 , MFLAGS, 0 , 7 , DFLAGS,9 ), 12 , GFLAGS),0 , "clk_i2s0_tx_frac" , "clk_i2s0_tx_src" , CLK_SET_RATE_PARENT,29 ), 0 ,9 ), 13 , GFLAGS,"clk_i2s0_tx" , mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT,28 ), 12 , 1 , MFLAGS,9 ), 14 , GFLAGS),0 , "clk_i2s0_tx_out_pre" , mux_i2s0_tx_out_p, 0 ,28 ), 14 , 2 , MFLAGS,9 ), 15 , GFLAGS),"clk_i2s0_tx_out" , "clk_i2s0_tx_out_pre" , CLK_SET_RATE_PARENT,10 ), 8 , CLK_GATE_HIWORD_MASK),0 , "clk_i2s0_rx_src" , mux_gpll_npll_p, 0 ,58 ), 8 , 1 , MFLAGS, 0 , 7 , DFLAGS,17 ), 0 , GFLAGS),0 , "clk_i2s0_rx_frac" , "clk_i2s0_rx_src" , CLK_SET_RATE_PARENT,59 ), 0 ,17 ), 1 , GFLAGS,"clk_i2s0_rx" , mux_i2s0_rx_tx_p, CLK_SET_RATE_PARENT,58 ), 12 , 1 , MFLAGS,17 ), 2 , GFLAGS),0 , "clk_i2s0_rx_out_pre" , mux_i2s0_rx_out_p, 0 ,58 ), 14 , 2 , MFLAGS,17 ), 3 , GFLAGS),"clk_i2s0_rx_out" , "clk_i2s0_rx_out_pre" , CLK_SET_RATE_PARENT,10 ), 11 , CLK_GATE_HIWORD_MASK),0 , "clk_i2s1_src" , mux_gpll_npll_p, 0 ,30 ), 8 , 1 , MFLAGS, 0 , 7 , DFLAGS,10 ), 0 , GFLAGS),0 , "clk_i2s1_frac" , "clk_i2s1_src" , CLK_SET_RATE_PARENT,31 ), 0 ,10 ), 1 , GFLAGS,"clk_i2s1" , "clk_i2s1_mux" , CLK_SET_RATE_PARENT,10 ), 2 , GFLAGS),0 , "clk_i2s1_out_pre" , mux_i2s1_out_p, 0 ,30 ), 15 , 1 , MFLAGS,10 ), 3 , GFLAGS),"clk_i2s1_out" , "clk_i2s1_out_pre" , CLK_SET_RATE_PARENT,10 ), 9 , CLK_GATE_HIWORD_MASK),0 , "clk_i2s2_src" , mux_gpll_npll_p, 0 ,32 ), 8 , 1 , MFLAGS, 0 , 7 , DFLAGS,10 ), 4 , GFLAGS),0 , "clk_i2s2_frac" , "clk_i2s2_src" , CLK_SET_RATE_PARENT,33 ), 0 ,10 ), 5 , GFLAGS,"clk_i2s2" , "clk_i2s2_mux" , CLK_SET_RATE_PARENT,10 ), 6 , GFLAGS),0 , "clk_i2s2_out_pre" , mux_i2s2_out_p, 0 ,32 ), 15 , 1 , MFLAGS,10 ), 7 , GFLAGS),"clk_i2s2_out" , "clk_i2s2_out_pre" , CLK_SET_RATE_PARENT,10 ), 10 , CLK_GATE_HIWORD_MASK),"clk_uart1_src" , mux_uart_src_p, CLK_SET_RATE_NO_REPARENT,34 ), 14 , 2 , MFLAGS, 0 , 5 , DFLAGS,10 ), 12 , GFLAGS),0 , "clk_uart1_np5" , "clk_uart1_src" , 0 ,35 ), 0 , 5 , DFLAGS,10 ), 13 , GFLAGS),0 , "clk_uart1_frac" , "clk_uart1_src" , CLK_SET_RATE_PARENT,36 ), 0 ,10 ), 14 , GFLAGS,"clk_uart1" , "clk_uart1_mux" , CLK_SET_RATE_PARENT,10 ), 15 , GFLAGS),"clk_uart2_src" , mux_uart_src_p, 0 ,37 ), 14 , 2 , MFLAGS, 0 , 5 , DFLAGS,11 ), 0 , GFLAGS),0 , "clk_uart2_np5" , "clk_uart2_src" , 0 ,38 ), 0 , 5 , DFLAGS,11 ), 1 , GFLAGS),0 , "clk_uart2_frac" , "clk_uart2_src" , CLK_SET_RATE_PARENT,39 ), 0 ,11 ), 2 , GFLAGS,"clk_uart2" , "clk_uart2_mux" , CLK_SET_RATE_PARENT,11 ), 3 , GFLAGS),0 , "clk_uart3_src" , mux_uart_src_p, 0 ,40 ), 14 , 2 , MFLAGS, 0 , 5 , DFLAGS,11 ), 4 , GFLAGS),0 , "clk_uart3_np5" , "clk_uart3_src" , 0 ,41 ), 0 , 5 , DFLAGS,11 ), 5 , GFLAGS),0 , "clk_uart3_frac" , "clk_uart3_src" , CLK_SET_RATE_PARENT,42 ), 0 ,11 ), 6 , GFLAGS,"clk_uart3" , "clk_uart3_mux" , CLK_SET_RATE_PARENT,11 ), 7 , GFLAGS),0 , "clk_uart4_src" , mux_uart_src_p, 0 ,43 ), 14 , 2 , MFLAGS, 0 , 5 , DFLAGS,11 ), 8 , GFLAGS),0 , "clk_uart4_np5" , "clk_uart4_src" , 0 ,44 ), 0 , 5 , DFLAGS,11 ), 9 , GFLAGS),0 , "clk_uart4_frac" , "clk_uart4_src" , CLK_SET_RATE_PARENT,45 ), 0 ,11 ), 10 , GFLAGS,"clk_uart4" , "clk_uart4_mux" , CLK_SET_RATE_PARENT,11 ), 11 , GFLAGS),0 , "clk_uart5_src" , mux_uart_src_p, 0 ,46 ), 14 , 2 , MFLAGS, 0 , 5 , DFLAGS,11 ), 12 , GFLAGS),0 , "clk_uart5_np5" , "clk_uart5_src" , 0 ,47 ), 0 , 5 , DFLAGS,11 ), 13 , GFLAGS),0 , "clk_uart5_frac" , "clk_uart5_src" , CLK_SET_RATE_PARENT,48 ), 0 ,11 ), 14 , GFLAGS,"clk_uart5" , "clk_uart5_mux" , CLK_SET_RATE_PARENT,11 ), 15 , GFLAGS),"clk_i2c0" , mux_gpll_xin24m_p, 0 ,49 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,12 ), 0 , GFLAGS),"clk_i2c1" , mux_gpll_xin24m_p, 0 ,49 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,12 ), 1 , GFLAGS),"clk_i2c2" , mux_gpll_xin24m_p, 0 ,50 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,12 ), 2 , GFLAGS),"clk_i2c3" , mux_gpll_xin24m_p, 0 ,50 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,12 ), 3 , GFLAGS),"clk_pwm0" , mux_gpll_xin24m_p, 0 ,52 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,12 ), 5 , GFLAGS),"clk_pwm1" , mux_gpll_xin24m_p, 0 ,52 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,12 ), 6 , GFLAGS),"clk_spi0" , mux_gpll_xin24m_p, 0 ,53 ), 7 , 1 , MFLAGS, 0 , 7 , DFLAGS,12 ), 7 , GFLAGS),"clk_spi1" , mux_gpll_xin24m_p, 0 ,53 ), 15 , 1 , MFLAGS, 8 , 7 , DFLAGS,12 ), 8 , GFLAGS),"sclk_timer0" , "xin24m" , 0 ,13 ), 0 , GFLAGS),"sclk_timer1" , "xin24m" , 0 ,13 ), 1 , GFLAGS),"sclk_timer2" , "xin24m" , 0 ,13 ), 2 , GFLAGS),"sclk_timer3" , "xin24m" , 0 ,13 ), 3 , GFLAGS),"sclk_timer4" , "xin24m" , 0 ,13 ), 4 , GFLAGS),"sclk_timer5" , "xin24m" , 0 ,13 ), 5 , GFLAGS),"clk_tsadc" , "xin24m" , 0 ,54 ), 0 , 11 , DFLAGS,12 ), 9 , GFLAGS),"clk_saradc" , "xin24m" , 0 ,55 ), 0 , 11 , DFLAGS,12 ), 10 , GFLAGS),"clk_otp" , "xin24m" , 0 ,56 ), 0 , 3 , DFLAGS,12 ), 11 , GFLAGS),"clk_otp_usr" , "clk_otp" , 0 ,56 ), 4 , 2 , DFLAGS,13 ), 6 , GFLAGS),0 , "clk_cpu_boost" , "xin24m" , CLK_IGNORE_UNUSED,12 ), 12 , GFLAGS),/* PD_CRYPTO */ 0 , "aclk_crypto_pre" , "aclk_bus_pre" , 0 ,8 ), 12 , GFLAGS),0 , "hclk_crypto_pre" , "hclk_bus_pre" , 0 ,8 ), 13 , GFLAGS),"clk_crypto" , mux_gpll_cpll_npll_p, 0 ,25 ), 6 , 2 , MFLAGS, 0 , 5 , DFLAGS,8 ), 14 , GFLAGS),"clk_crypto_apk" , mux_gpll_cpll_npll_p, 0 ,25 ), 14 , 2 , MFLAGS, 8 , 5 , DFLAGS,8 ), 15 , GFLAGS),/* * Clock-Architecture Diagram 9 /* PD_BUS_TOP */ 0 , "pclk_top_niu" , "pclk_top_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16 ), 0 , GFLAGS),0 , "pclk_top_cru" , "pclk_top_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16 ), 1 , GFLAGS),"pclk_otp_phy" , "pclk_top_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16 ), 2 , GFLAGS),0 , "pclk_ddrphy" , "pclk_top_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16 ), 3 , GFLAGS),"pclk_mipidsiphy" , "pclk_top_pre" , 0 , PX30_CLKGATE_CON(16 ), 4 , GFLAGS),"pclk_mipicsiphy" , "pclk_top_pre" , 0 , PX30_CLKGATE_CON(16 ), 5 , GFLAGS),"pclk_usb_grf" , "pclk_top_pre" , 0 , PX30_CLKGATE_CON(16 ), 6 , GFLAGS),0 , "pclk_cpu_hoost" , "pclk_top_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16 ), 7 , GFLAGS),/* PD_VI */ 0 , "aclk_vi_niu" , "aclk_vi_pre" , 0 , PX30_CLKGATE_CON(4 ), 15 , GFLAGS),"aclk_cif" , "aclk_vi_pre" , 0 , PX30_CLKGATE_CON(5 ), 1 , GFLAGS),"aclk_isp" , "aclk_vi_pre" , 0 , PX30_CLKGATE_CON(5 ), 3 , GFLAGS),0 , "hclk_vi_niu" , "hclk_vi_pre" , 0 , PX30_CLKGATE_CON(5 ), 0 , GFLAGS),"hclk_cif" , "hclk_vi_pre" , 0 , PX30_CLKGATE_CON(5 ), 2 , GFLAGS),"hclk_isp" , "hclk_vi_pre" , 0 , PX30_CLKGATE_CON(5 ), 4 , GFLAGS),/* PD_VO */ 0 , "aclk_vo_niu" , "aclk_vo_pre" , 0 , PX30_CLKGATE_CON(3 ), 0 , GFLAGS),"aclk_vopb" , "aclk_vo_pre" , 0 , PX30_CLKGATE_CON(3 ), 3 , GFLAGS),"aclk_rga" , "aclk_vo_pre" , 0 , PX30_CLKGATE_CON(3 ), 7 , GFLAGS),"aclk_vopl" , "aclk_vo_pre" , 0 , PX30_CLKGATE_CON(3 ), 5 , GFLAGS),0 , "hclk_vo_niu" , "hclk_vo_pre" , 0 , PX30_CLKGATE_CON(3 ), 1 , GFLAGS),"hclk_vopb" , "hclk_vo_pre" , 0 , PX30_CLKGATE_CON(3 ), 4 , GFLAGS),"hclk_rga" , "hclk_vo_pre" , 0 , PX30_CLKGATE_CON(3 ), 8 , GFLAGS),"hclk_vopl" , "hclk_vo_pre" , 0 , PX30_CLKGATE_CON(3 ), 6 , GFLAGS),0 , "pclk_vo_niu" , "pclk_vo_pre" , 0 , PX30_CLKGATE_CON(3 ), 2 , GFLAGS),"pclk_mipi_dsi" , "pclk_vo_pre" , 0 , PX30_CLKGATE_CON(3 ), 9 , GFLAGS),/* PD_BUS */ 0 , "aclk_bus_niu" , "aclk_bus_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13 ), 8 , GFLAGS),0 , "aclk_intmem" , "aclk_bus_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13 ), 11 , GFLAGS),"aclk_gic" , "aclk_bus_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13 ), 12 , GFLAGS),"aclk_dcf" , "aclk_bus_pre" , 0 , PX30_CLKGATE_CON(13 ), 15 , GFLAGS),/* aclk_dmac is controlled by sgrf_soc_con1[11]. */ "aclk_dmac" , "aclk_bus_pre" ),0 , "hclk_bus_niu" , "hclk_bus_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13 ), 9 , GFLAGS),0 , "hclk_rom" , "hclk_bus_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13 ), 14 , GFLAGS),"hclk_pdm" , "hclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 1 , GFLAGS),"hclk_i2s0" , "hclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 2 , GFLAGS),"hclk_i2s1" , "hclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 3 , GFLAGS),"hclk_i2s2" , "hclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 4 , GFLAGS),0 , "pclk_bus_niu" , "pclk_bus_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13 ), 10 , GFLAGS),"pclk_dcf" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 0 , GFLAGS),"pclk_uart1" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 5 , GFLAGS),"pclk_uart2" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 6 , GFLAGS),"pclk_uart3" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 7 , GFLAGS),"pclk_uart4" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 8 , GFLAGS),"pclk_uart5" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 9 , GFLAGS),"pclk_i2c0" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 10 , GFLAGS),"pclk_i2c1" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 11 , GFLAGS),"pclk_i2c2" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 12 , GFLAGS),"pclk_i2c3" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 13 , GFLAGS),"pclk_i2c4" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 14 , GFLAGS),"pclk_pwm0" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(14 ), 15 , GFLAGS),"pclk_pwm1" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(15 ), 0 , GFLAGS),"pclk_spi0" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(15 ), 1 , GFLAGS),"pclk_spi1" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(15 ), 2 , GFLAGS),"pclk_saradc" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(15 ), 3 , GFLAGS),"pclk_tsadc" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(15 ), 4 , GFLAGS),"pclk_timer" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(15 ), 5 , GFLAGS),"pclk_otp_ns" , "pclk_bus_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15 ), 6 , GFLAGS),"pclk_wdt_ns" , "pclk_bus_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15 ), 7 , GFLAGS),"pclk_gpio1" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(15 ), 8 , GFLAGS),"pclk_gpio2" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(15 ), 9 , GFLAGS),"pclk_gpio3" , "pclk_bus_pre" , 0 , PX30_CLKGATE_CON(15 ), 10 , GFLAGS),0 , "pclk_grf" , "pclk_bus_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15 ), 11 , GFLAGS),0 , "pclk_sgrf" , "pclk_bus_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15 ), 12 , GFLAGS),/* PD_VPU */ 0 , "hclk_vpu_niu" , "hclk_vpu_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4 ), 7 , GFLAGS),"hclk_vpu" , "hclk_vpu_pre" , 0 , PX30_CLKGATE_CON(4 ), 6 , GFLAGS),0 , "aclk_vpu_niu" , "aclk_vpu_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4 ), 5 , GFLAGS),"aclk_vpu" , "aclk_vpu_pre" , 0 , PX30_CLKGATE_CON(4 ), 4 , GFLAGS),/* PD_CRYPTO */ 0 , "hclk_crypto_niu" , "hclk_crypto_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9 ), 3 , GFLAGS),"hclk_crypto" , "hclk_crypto_pre" , 0 , PX30_CLKGATE_CON(9 ), 5 , GFLAGS),0 , "aclk_crypto_niu" , "aclk_crypto_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9 ), 2 , GFLAGS),"aclk_crypto" , "aclk_crypto_pre" , 0 , PX30_CLKGATE_CON(9 ), 4 , GFLAGS),/* PD_SDCARD */ 0 , "hclk_sdmmc_niu" , "hclk_sdmmc_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7 ), 0 , GFLAGS),"hclk_sdmmc" , "hclk_sdmmc_pre" , 0 , PX30_CLKGATE_CON(7 ), 1 , GFLAGS),/* PD_PERI */ 0 , "aclk_peri_niu" , "aclk_peri_pre" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(5 ), 9 , GFLAGS),/* PD_MMC_NAND */ "hclk_nandc" , "hclk_mmc_nand" , 0 , PX30_CLKGATE_CON(5 ), 15 , GFLAGS),0 , "hclk_mmc_nand_niu" , "hclk_mmc_nand" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(6 ), 8 , GFLAGS),"hclk_sdio" , "hclk_mmc_nand" , 0 , PX30_CLKGATE_CON(6 ), 9 , GFLAGS),"hclk_emmc" , "hclk_mmc_nand" , 0 , PX30_CLKGATE_CON(6 ), 10 , GFLAGS),"hclk_sfc" , "hclk_mmc_nand" , 0 , PX30_CLKGATE_CON(6 ), 11 , GFLAGS),/* PD_USB */ 0 , "hclk_usb_niu" , "hclk_usb" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7 ), 4 , GFLAGS),"hclk_otg" , "hclk_usb" , 0 , PX30_CLKGATE_CON(7 ), 5 , GFLAGS),"hclk_host" , "hclk_usb" , 0 , PX30_CLKGATE_CON(7 ), 6 , GFLAGS),"hclk_host_arb" , "hclk_usb" , CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7 ), 8 , GFLAGS),/* PD_GMAC */ 0 , "aclk_gmac_niu" , "aclk_gmac_pre" , CLK_IGNORE_UNUSED,8 ), 0 , GFLAGS),"aclk_gmac" , "aclk_gmac_pre" , 0 ,8 ), 2 , GFLAGS),0 , "pclk_gmac_niu" , "pclk_gmac_pre" , CLK_IGNORE_UNUSED,8 ), 1 , GFLAGS),"pclk_gmac" , "pclk_gmac_pre" , 0 ,8 ), 3 , GFLAGS),static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {/* * Clock-Architecture Diagram 2 0 , "clk_rtc32k_frac" , "xin24m" , CLK_IGNORE_UNUSED,1 ), 0 ,0 ), 13 , GFLAGS,"xin24m_div" , "xin24m" , CLK_IGNORE_UNUSED,0 ), 8 , 5 , DFLAGS,0 ), 12 , GFLAGS),0 , "clk_wifi_pmu_src" , "gpll" , 0 ,2 ), 8 , 6 , DFLAGS,0 ), 14 , GFLAGS),"clk_wifi_pmu" , mux_wifi_pmu_p, CLK_SET_RATE_PARENT,2 ), 15 , 1 , MFLAGS,0 ), 15 , GFLAGS),0 , "clk_uart0_pmu_src" , mux_uart_src_p, 0 ,3 ), 14 , 2 , MFLAGS, 0 , 5 , DFLAGS,1 ), 0 , GFLAGS),0 , "clk_uart0_np5" , "clk_uart0_pmu_src" , 0 ,4 ), 0 , 5 , DFLAGS,1 ), 1 , GFLAGS),0 , "clk_uart0_frac" , "clk_uart0_pmu_src" , CLK_SET_RATE_PARENT,5 ), 0 ,1 ), 2 , GFLAGS,"clk_uart0_pmu" , "clk_uart0_pmu_mux" , CLK_SET_RATE_PARENT,1 ), 3 , GFLAGS),"clk_pvtm_pmu" , "xin24m" , 0 ,1 ), 4 , GFLAGS),"pclk_pmu_pre" , "gpll" , 0 ,0 ), 0 , 5 , DFLAGS,0 ), 0 , GFLAGS),"clk_ref24m_pmu" , "gpll" , 0 ,2 ), 0 , 6 , DFLAGS,1 ), 8 , GFLAGS),"clk_usbphy_ref" , mux_usbphy_ref_p, CLK_SET_RATE_PARENT,2 ), 6 , 1 , MFLAGS,1 ), 9 , GFLAGS),"clk_mipidsiphy_ref" , mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,2 ), 7 , 1 , MFLAGS,1 ), 10 , GFLAGS),/* * Clock-Architecture Diagram 9 /* PD_PMU */ 0 , "pclk_pmu_niu" , "pclk_pmu_pre" , CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0 ), 1 , GFLAGS),0 , "pclk_pmu_sgrf" , "pclk_pmu_pre" , CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0 ), 2 0 , "pclk_pmu_grf" , "pclk_pmu_pre" , CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0 ), 3 , GFLAGS),0 , "pclk_pmu" , "pclk_pmu_pre" , CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0 ), 4 , GFLAGS),0 , "pclk_pmu_mem" , "pclk_pmu_pre" , CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0 ), 5 , GFLAGS),"pclk_gpio0_pmu" , "pclk_pmu_pre" , 0 , PX30_PMU_CLKGATE_CON(0 ), 6 , GFLAGS),"pclk_uart0_pmu" , "pclk_pmu_pre" , 0 , PX30_PMU_CLKGATE_CON(0 ), 7 , GFLAGS),0 , "pclk_cru_pmu" , "pclk_pmu_pre" , CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0 ), 8 , GFLAGS),static const char *const px30_cru_critical_clocks[] __initconst = {"aclk_bus_pre" ,"pclk_bus_pre" ,"hclk_bus_pre" ,"aclk_peri_pre" ,"hclk_peri_pre" ,"aclk_gpu_niu" ,"pclk_top_pre" ,"pclk_pmu_pre" ,"hclk_usb_niu" ,"pclk_vo_niu" ,"aclk_vo_niu" ,"hclk_vo_niu" ,"aclk_vi_niu" ,"hclk_vi_niu" ,"pll_npll" ,"usb480m" ,"clk_uart2" ,"pclk_uart2" ,"pclk_usb_grf" ,static void __init px30_clk_init(struct device_node *np)struct rockchip_clk_provider *ctx;unsigned long clk_nr_clks;void __iomem *reg_base;0 );if (!reg_base) {"%s: could not map cru region\n" , __func__);return ;1 ;if (IS_ERR(ctx)) {"%s: rockchip clk init failed\n" , __func__);return ;"armclk" ,12 , reg_base + PX30_SOFTRST_CON(0 ),"rockchip,px30-cru" , px30_clk_init);static void __init px30_pmu_clk_init(struct device_node *np)struct rockchip_clk_provider *ctx;unsigned long clkpmu_nr_clks;void __iomem *reg_base;0 );if (!reg_base) {"%s: could not map cru pmu region\n" , __func__);return ;1 ;if (IS_ERR(ctx)) {"%s: rockchip pmu clk init failed\n" , __func__);return ;"rockchip,px30-pmucru" , px30_pmu_clk_init);
Messung V0.5 in Prozent C=95 H=92 G=93
