// SPDX-License-Identifier: GPL-2.0 /* * Renesas RZ/G3E CPG driver * * Copyright (C) 2024 Renesas Electronics Corp. #include <linux/clk-provider.h>#include <linux/device.h>#include <linux/init.h>#include <linux/kernel.h>#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>#include "rzv2h-cpg.h" enum clk_ids {/* Core Clock Outputs exported to DT */ /* External Input Clocks */ /* PLL Clocks */ /* Internal Core Clocks */ /* Module Clocks */ static const struct clk_div_table dtable_1_8[] = {0 , 1 },1 , 2 },2 , 4 },3 , 8 },0 , 0 },static const struct clk_div_table dtable_2_4[] = {0 , 2 },1 , 4 },0 , 0 },static const struct clk_div_table dtable_2_16[] = {0 , 2 },1 , 4 },2 , 8 },3 , 16 },0 , 0 },static const struct clk_div_table dtable_2_64[] = {0 , 2 },1 , 4 },2 , 8 },3 , 16 },4 , 64 },0 , 0 },static const struct clk_div_table dtable_2_100[] = {0 , 2 },1 , 10 },2 , 100 },0 , 0 },/* Mux clock tables */ static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0" , "et0_rxclk" };static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0" , "et0_txclk" };static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1" , "et1_rxclk" };static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1" , "et1_txclk" };static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3" , ".pllcm33_div4" };static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0" , ".pllcm33_div5" };static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {/* External Clock Inputs */ "audio_extal" , CLK_AUDIO_EXTAL),"rtxin" , CLK_RTXIN),"qextal" , CLK_QEXTAL),/* PLL Clocks */ ".pllcm33" , CLK_PLLCM33, CLK_QEXTAL, 200 , 3 ),".pllcln" , CLK_PLLCLN, CLK_QEXTAL, 200 , 3 ),".plldty" , CLK_PLLDTY, CLK_QEXTAL, 200 , 3 ),".pllca55" , CLK_PLLCA55, CLK_QEXTAL, PLLCA55),".plleth" , CLK_PLLETH, CLK_QEXTAL, 125 , 3 ),".pllvdo" , CLK_PLLVDO, CLK_QEXTAL, 105 , 2 ),/* Internal Core Clocks */ ".pllcm33_div3" , CLK_PLLCM33_DIV3, CLK_PLLCM33, 1 , 3 ),".pllcm33_div4" , CLK_PLLCM33_DIV4, CLK_PLLCM33, 1 , 4 ),".pllcm33_div5" , CLK_PLLCM33_DIV5, CLK_PLLCM33, 1 , 5 ),".pllcm33_div16" , CLK_PLLCM33_DIV16, CLK_PLLCM33, 1 , 16 ),".pllcm33_gear" , CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),".smux2_xspi_clk0" , CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),".smux2_xspi_clk1" , CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),".pllcm33_xspi" , CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,".pllcln_div2" , CLK_PLLCLN_DIV2, CLK_PLLCLN, 1 , 2 ),".pllcln_div8" , CLK_PLLCLN_DIV8, CLK_PLLCLN, 1 , 8 ),".pllcln_div16" , CLK_PLLCLN_DIV16, CLK_PLLCLN, 1 , 16 ),".pllcln_div20" , CLK_PLLCLN_DIV20, CLK_PLLCLN, 1 , 20 ),".plldty_acpu" , CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),".plldty_acpu_div2" , CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1 , 2 ),".plldty_acpu_div4" , CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1 , 4 ),".plldty_div8" , CLK_PLLDTY_DIV8, CLK_PLLDTY, 1 , 8 ),".plleth_250_fix" , CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1 , 4 ),".plleth_125_fix" , CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1 , 2 ),".plleth_gbe0" , CLK_CSDIV_PLLETH_GBE0, CLK_PLLETH_DIV_250_FIX,".plleth_gbe1" , CLK_CSDIV_PLLETH_GBE1, CLK_PLLETH_DIV_250_FIX,".smux2_gbe0_txclk" , CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),".smux2_gbe0_rxclk" , CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),".smux2_gbe1_txclk" , CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),".smux2_gbe1_rxclk" , CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),".plldty_div16" , CLK_PLLDTY_DIV16, CLK_PLLDTY, 1 , 16 ),".pllvdo_cru0" , CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),".pllvdo_gpu" , CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),/* Core Clocks */ "sys_0_pclk" , R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1 , 1 ),"ca55_0_coreclk0" , R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55,"ca55_0_coreclk1" , R9A09G047_CA55_0_CORECLK1, CLK_PLLCA55,"ca55_0_coreclk2" , R9A09G047_CA55_0_CORECLK2, CLK_PLLCA55,"ca55_0_coreclk3" , R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55,"iotop_0_shclk" , R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1 , 1 ),"spi_clk_spi" , R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1 , 2 ),"gbeth_0_clk_ptp_ref_i" , R9A09G047_GBETH_0_CLK_PTP_REF_I,1 , 1 ),"gbeth_1_clk_ptp_ref_i" , R9A09G047_GBETH_1_CLK_PTP_REF_I,1 , 1 ),static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {"icu_0_pclk_i" , CLK_PLLCM33_DIV16, 0 , 5 , 0 , 5 ,"gic_0_gicclk" , CLK_PLLDTY_ACPU_DIV4, 1 , 3 , 0 , 19 ,3 , BIT(5 ))),"wdt_1_clkp" , CLK_PLLCLN_DIV16, 4 , 13 , 2 , 13 ,1 , BIT(0 ))),"wdt_1_clk_loco" , CLK_QEXTAL, 4 , 14 , 2 , 14 ,1 , BIT(0 ))),"wdt_2_clkp" , CLK_PLLCLN_DIV16, 4 , 15 , 2 , 15 ,5 , BIT(12 ))),"wdt_2_clk_loco" , CLK_QEXTAL, 5 , 0 , 2 , 16 ,5 , BIT(12 ))),"wdt_3_clkp" , CLK_PLLCLN_DIV16, 5 , 1 , 2 , 17 ,5 , BIT(13 ))),"wdt_3_clk_loco" , CLK_QEXTAL, 5 , 2 , 2 , 18 ,5 , BIT(13 ))),"scif_0_clk_pck" , CLK_PLLCM33_DIV16, 8 , 15 , 4 , 15 ,3 , BIT(14 ))),"i3c_0_pclkrw" , CLK_PLLCLN_DIV16, 9 , 0 , 4 , 16 ,10 , BIT(15 ))),"i3c_0_pclk" , CLK_PLLCLN_DIV16, 9 , 1 , 4 , 17 ,10 , BIT(15 ))),"i3c_0_tclk" , CLK_PLLCLN_DIV8, 9 , 2 , 4 , 18 ,10 , BIT(15 ))),"riic_8_ckm" , CLK_PLLCM33_DIV16, 9 , 3 , 4 , 19 ,3 , BIT(13 ))),"riic_0_ckm" , CLK_PLLCLN_DIV16, 9 , 4 , 4 , 20 ,1 , BIT(1 ))),"riic_1_ckm" , CLK_PLLCLN_DIV16, 9 , 5 , 4 , 21 ,1 , BIT(2 ))),"riic_2_ckm" , CLK_PLLCLN_DIV16, 9 , 6 , 4 , 22 ,1 , BIT(3 ))),"riic_3_ckm" , CLK_PLLCLN_DIV16, 9 , 7 , 4 , 23 ,1 , BIT(4 ))),"riic_4_ckm" , CLK_PLLCLN_DIV16, 9 , 8 , 4 , 24 ,1 , BIT(5 ))),"riic_5_ckm" , CLK_PLLCLN_DIV16, 9 , 9 , 4 , 25 ,1 , BIT(6 ))),"riic_6_ckm" , CLK_PLLCLN_DIV16, 9 , 10 , 4 , 26 ,1 , BIT(7 ))),"riic_7_ckm" , CLK_PLLCLN_DIV16, 9 , 11 , 4 , 27 ,1 , BIT(8 ))),"canfd_0_pclk" , CLK_PLLCLN_DIV16, 9 , 12 , 4 , 28 ,10 , BIT(14 ))),"canfd_0_clk_ram" , CLK_PLLCLN_DIV8, 9 , 13 , 4 , 29 ,10 , BIT(14 ))),"canfd_0_clkc" , CLK_PLLCLN_DIV20, 9 , 14 , 4 , 30 ,10 , BIT(14 ))),"spi_hclk" , CLK_PLLCM33_GEAR, 9 , 15 , 4 , 31 ,4 , BIT(5 ))),"spi_aclk" , CLK_PLLCM33_GEAR, 10 , 0 , 5 , 0 ,4 , BIT(5 ))),"spi_clk_spix2" , CLK_PLLCM33_XSPI, 10 , 1 , 5 , 2 ,4 , BIT(5 ))),"sdhi_0_imclk" , CLK_PLLCLN_DIV8, 10 , 3 , 5 , 3 ,8 , BIT(2 ))),"sdhi_0_imclk2" , CLK_PLLCLN_DIV8, 10 , 4 , 5 , 4 ,8 , BIT(2 ))),"sdhi_0_clk_hs" , CLK_PLLCLN_DIV2, 10 , 5 , 5 , 5 ,8 , BIT(2 ))),"sdhi_0_aclk" , CLK_PLLDTY_ACPU_DIV4, 10 , 6 , 5 , 6 ,8 , BIT(2 ))),"sdhi_1_imclk" , CLK_PLLCLN_DIV8, 10 , 7 , 5 , 7 ,8 , BIT(3 ))),"sdhi_1_imclk2" , CLK_PLLCLN_DIV8, 10 , 8 , 5 , 8 ,8 , BIT(3 ))),"sdhi_1_clk_hs" , CLK_PLLCLN_DIV2, 10 , 9 , 5 , 9 ,8 , BIT(3 ))),"sdhi_1_aclk" , CLK_PLLDTY_ACPU_DIV4, 10 , 10 , 5 , 10 ,8 , BIT(3 ))),"sdhi_2_imclk" , CLK_PLLCLN_DIV8, 10 , 11 , 5 , 11 ,8 , BIT(4 ))),"sdhi_2_imclk2" , CLK_PLLCLN_DIV8, 10 , 12 , 5 , 12 ,8 , BIT(4 ))),"sdhi_2_clk_hs" , CLK_PLLCLN_DIV2, 10 , 13 , 5 , 13 ,8 , BIT(4 ))),"sdhi_2_aclk" , CLK_PLLDTY_ACPU_DIV4, 10 , 14 , 5 , 14 ,8 , BIT(4 ))),"gbeth_0_clk_tx_i" , CLK_SMUX2_GBE0_TXCLK, 11 , 8 , 5 , 24 ,8 , BIT(5 )), 1 ),"gbeth_0_clk_rx_i" , CLK_SMUX2_GBE0_RXCLK, 11 , 9 , 5 , 25 ,8 , BIT(5 )), 1 ),"gbeth_0_clk_tx_180_i" , CLK_SMUX2_GBE0_TXCLK, 11 , 10 , 5 , 26 ,8 , BIT(5 )), 1 ),"gbeth_0_clk_rx_180_i" , CLK_SMUX2_GBE0_RXCLK, 11 , 11 , 5 , 27 ,8 , BIT(5 )), 1 ),"gbeth_0_aclk_csr_i" , CLK_PLLDTY_DIV8, 11 , 12 , 5 , 28 ,8 , BIT(5 ))),"gbeth_0_aclk_i" , CLK_PLLDTY_DIV8, 11 , 13 , 5 , 29 ,8 , BIT(5 ))),"gbeth_1_clk_tx_i" , CLK_SMUX2_GBE1_TXCLK, 11 , 14 , 5 , 30 ,8 , BIT(6 )), 1 ),"gbeth_1_clk_rx_i" , CLK_SMUX2_GBE1_RXCLK, 11 , 15 , 5 , 31 ,8 , BIT(6 )), 1 ),"gbeth_1_clk_tx_180_i" , CLK_SMUX2_GBE1_TXCLK, 12 , 0 , 6 , 0 ,8 , BIT(6 )), 1 ),"gbeth_1_clk_rx_180_i" , CLK_SMUX2_GBE1_RXCLK, 12 , 1 , 6 , 1 ,8 , BIT(6 )), 1 ),"gbeth_1_aclk_csr_i" , CLK_PLLDTY_DIV8, 12 , 2 , 6 , 2 ,8 , BIT(6 ))),"gbeth_1_aclk_i" , CLK_PLLDTY_DIV8, 12 , 3 , 6 , 3 ,8 , BIT(6 ))),"cru_0_aclk" , CLK_PLLDTY_ACPU_DIV2, 13 , 2 , 6 , 18 ,9 , BIT(4 ))),"cru_0_vclk" , CLK_PLLVDO_CRU0, 13 , 3 , 6 , 19 ,9 , BIT(4 ))),"cru_0_pclk" , CLK_PLLDTY_DIV16, 13 , 4 , 6 , 20 ,9 , BIT(4 ))),"ge3d_clk" , CLK_PLLVDO_GPU, 15 , 0 , 7 , 16 ,3 , BIT(4 ))),"ge3d_axi_clk" , CLK_PLLDTY_ACPU_DIV2, 15 , 1 , 7 , 17 ,3 , BIT(4 ))),"ge3d_ace_clk" , CLK_PLLDTY_ACPU_DIV2, 15 , 2 , 7 , 18 ,3 , BIT(4 ))),"tsu_1_pclk" , CLK_QEXTAL, 16 , 10 , 8 , 10 ,2 , BIT(15 ))),static const struct rzv2h_reset r9a09g047_resets[] __initconst = {3 , 0 , 1 , 1 ), /* SYS_0_PRESETN */ 3 , 6 , 1 , 7 ), /* ICU_0_PRESETN_I */ 3 , 8 , 1 , 9 ), /* GIC_0_GICRESET_N */ 3 , 9 , 1 , 10 ), /* GIC_0_DBG_GICRESET_N */ 7 , 6 , 3 , 7 ), /* WDT_1_RESET */ 7 , 7 , 3 , 8 ), /* WDT_2_RESET */ 7 , 8 , 3 , 9 ), /* WDT_3_RESET */ 9 , 5 , 4 , 6 ), /* SCIF_0_RST_SYSTEM_N */ 9 , 6 , 4 , 7 ), /* I3C_0_PRESETN */ 9 , 7 , 4 , 8 ), /* I3C_0_TRESETN */ 9 , 8 , 4 , 9 ), /* RIIC_0_MRST */ 9 , 9 , 4 , 10 ), /* RIIC_1_MRST */ 9 , 10 , 4 , 11 ), /* RIIC_2_MRST */ 9 , 11 , 4 , 12 ), /* RIIC_3_MRST */ 9 , 12 , 4 , 13 ), /* RIIC_4_MRST */ 9 , 13 , 4 , 14 ), /* RIIC_5_MRST */ 9 , 14 , 4 , 15 ), /* RIIC_6_MRST */ 9 , 15 , 4 , 16 ), /* RIIC_7_MRST */ 10 , 0 , 4 , 17 ), /* RIIC_8_MRST */ 10 , 1 , 4 , 18 ), /* CANFD_0_RSTP_N */ 10 , 2 , 4 , 19 ), /* CANFD_0_RSTC_N */ 10 , 3 , 4 , 20 ), /* SPI_HRESETN */ 10 , 4 , 4 , 21 ), /* SPI_ARESETN */ 10 , 7 , 4 , 24 ), /* SDHI_0_IXRST */ 10 , 8 , 4 , 25 ), /* SDHI_1_IXRST */ 10 , 9 , 4 , 26 ), /* SDHI_2_IXRST */ 11 , 0 , 5 , 1 ), /* GBETH_0_ARESETN_I */ 11 , 1 , 5 , 2 ), /* GBETH_1_ARESETN_I */ 12 , 5 , 5 , 22 ), /* CRU_0_PRESETN */ 12 , 6 , 5 , 23 ), /* CRU_0_ARESETN */ 12 , 7 , 5 , 24 ), /* CRU_0_S_RESETN */ 13 , 13 , 6 , 14 ), /* GE3D_RESETN */ 13 , 14 , 6 , 15 ), /* GE3D_AXI_RESETN */ 13 , 15 , 6 , 16 ), /* GE3D_ACE_RESETN */ 15 , 8 , 7 , 9 ), /* TSU_1_PRESETN */ const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {/* Core Clocks */ /* Module Clocks */ 28 * 16 ,/* Resets */ 208 ,
Messung V0.5 in Prozent C=92 H=97 G=94
