// SPDX-License-Identifier: GPL-2.0 /* * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2020 Renesas Electronics Corp. * * Based on r8a7795-cpg-mssr.c * * Copyright (C) 2015 Glider bvba * Copyright (C) 2015 Renesas Electronics Corp. #include <linux/bitfield.h>#include <linux/clk.h>#include <linux/clk-provider.h>#include <linux/device.h>#include <linux/err.h>#include <linux/init.h>#include <linux/kernel.h>#include <linux/soc/renesas/rcar-rst.h>#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>#include "renesas-cpg-mssr.h" #include "rcar-gen4-cpg.h" enum clk_ids {/* Core Clock Outputs exported to DT */ /* External Input Clocks */ /* Internal Core Clocks */ /* Module Clocks */ #define DEF_PLL(_name, _id, _offset) \#define CPG_PLL20CR 0 x0834 /* PLL20 Control Register */ #define CPG_PLL21CR 0 x0838 /* PLL21 Control Register */ #define CPG_PLL30CR 0 x083c /* PLL30 Control Register */ #define CPG_PLL31CR 0 x0840 /* PLL31 Control Register */ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {/* External Clock Inputs */ "extal" , CLK_EXTAL),"extalr" , CLK_EXTALR),/* Internal Core Clocks */ ".main" , CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),".pll1" , CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),".pll5" , CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),".pll20" , CLK_PLL20, CPG_PLL20CR),".pll21" , CLK_PLL21, CPG_PLL21CR),".pll30" , CLK_PLL30, CPG_PLL30CR),".pll31" , CLK_PLL31, CPG_PLL31CR),".pll1_div2" , CLK_PLL1_DIV2, CLK_PLL1, 2 , 1 ),".pll20_div2" , CLK_PLL20_DIV2, CLK_PLL20, 2 , 1 ),".pll21_div2" , CLK_PLL21_DIV2, CLK_PLL21, 2 , 1 ),".pll30_div2" , CLK_PLL30_DIV2, CLK_PLL30, 2 , 1 ),".pll31_div2" , CLK_PLL31_DIV2, CLK_PLL31, 2 , 1 ),".pll5_div2" , CLK_PLL5_DIV2, CLK_PLL5, 2 , 1 ),".pll5_div4" , CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2 , 1 ),".s1" , CLK_S1, CLK_PLL1_DIV2, 2 , 1 ),".s3" , CLK_S3, CLK_PLL1_DIV2, 4 , 1 ),".sdsrc" , CLK_SDSRC, CLK_PLL5_DIV4, 1 , 1 ),".oco" , CLK_OCO, 32768 ),".rpcsrc" , CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),/* Core Clock Outputs */ "z0" , R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2 , 0 ),"z1" , R8A779A0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL21, 2 , 8 ),"zx" , R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2 , 1 ),"s1d1" , R8A779A0_CLK_S1D1, CLK_S1, 1 , 1 ),"s1d2" , R8A779A0_CLK_S1D2, CLK_S1, 2 , 1 ),"s1d4" , R8A779A0_CLK_S1D4, CLK_S1, 4 , 1 ),"s1d8" , R8A779A0_CLK_S1D8, CLK_S1, 8 , 1 ),"s1d12" , R8A779A0_CLK_S1D12, CLK_S1, 12 , 1 ),"s3d1" , R8A779A0_CLK_S3D1, CLK_S3, 1 , 1 ),"s3d2" , R8A779A0_CLK_S3D2, CLK_S3, 2 , 1 ),"s3d4" , R8A779A0_CLK_S3D4, CLK_S3, 4 , 1 ),"zs" , R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4 , 1 ),"zt" , R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2 , 1 ),"ztr" , R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2 , 1 ),"zr" , R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1 , 1 ),"cnndsp" , R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1 , 1 ),"vip" , R8A779A0_CLK_VIP, CLK_PLL5, 5 , 1 ),"adgh" , R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1 , 1 ),"icu" , R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2 , 1 ),"icud2" , R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4 , 1 ),"vcbus" , R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1 , 1 ),"cbfusa" , R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2 , 1 ),"cp" , R8A779A0_CLK_CP, CLK_EXTAL, 2 , 1 ),"cl16mck" , R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64 , 1 ),"sd0h" , R8A779A0_CLK_SD0H, CLK_SDSRC, CPG_SD0CKCR),"sd0" , R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, CPG_SD0CKCR),"rpc" , R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),"rpcd2" , R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,"mso" , R8A779A0_CLK_MSO, CLK_PLL5_DIV4, CPG_MSOCKCR),"canfd" , R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, CPG_CANFDCKCR),"csi0" , R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, CPG_CSICKCR),"dsi" , R8A779A0_CLK_DSI, CLK_PLL5_DIV4, CPG_DSIEXTCKCR),"osc" , R8A779A0_CLK_OSC, CLK_EXTAL, 8 ),"r" , R8A779A0_CLK_R, 29 , CLK_EXTALR, 1 , CLK_OCO, 1 ),static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {"isp0" , 16 , R8A779A0_CLK_S1D1),"isp1" , 17 , R8A779A0_CLK_S1D1),"isp2" , 18 , R8A779A0_CLK_S1D1),"isp3" , 19 , R8A779A0_CLK_S1D1),"avb0" , 211 , R8A779A0_CLK_S3D2),"avb1" , 212 , R8A779A0_CLK_S3D2),"avb2" , 213 , R8A779A0_CLK_S3D2),"avb3" , 214 , R8A779A0_CLK_S3D2),"avb4" , 215 , R8A779A0_CLK_S3D2),"avb5" , 216 , R8A779A0_CLK_S3D2),"canfd0" , 328 , R8A779A0_CLK_S3D2),"csi40" , 331 , R8A779A0_CLK_CSI0),"csi41" , 400 , R8A779A0_CLK_CSI0),"csi42" , 401 , R8A779A0_CLK_CSI0),"csi43" , 402 , R8A779A0_CLK_CSI0),"du" , 411 , R8A779A0_CLK_S3D1),"dsi0" , 415 , R8A779A0_CLK_DSI),"dsi1" , 416 , R8A779A0_CLK_DSI),"fcpvd0" , 508 , R8A779A0_CLK_S3D1),"fcpvd1" , 509 , R8A779A0_CLK_S3D1),"hscif0" , 514 , R8A779A0_CLK_S1D2),"hscif1" , 515 , R8A779A0_CLK_S1D2),"hscif2" , 516 , R8A779A0_CLK_S1D2),"hscif3" , 517 , R8A779A0_CLK_S1D2),"i2c0" , 518 , R8A779A0_CLK_S1D4),"i2c1" , 519 , R8A779A0_CLK_S1D4),"i2c2" , 520 , R8A779A0_CLK_S1D4),"i2c3" , 521 , R8A779A0_CLK_S1D4),"i2c4" , 522 , R8A779A0_CLK_S1D4),"i2c5" , 523 , R8A779A0_CLK_S1D4),"i2c6" , 524 , R8A779A0_CLK_S1D4),"ispcs0" , 612 , R8A779A0_CLK_S1D1),"ispcs1" , 613 , R8A779A0_CLK_S1D1),"ispcs2" , 614 , R8A779A0_CLK_S1D1),"ispcs3" , 615 , R8A779A0_CLK_S1D1),"msi0" , 618 , R8A779A0_CLK_MSO),"msi1" , 619 , R8A779A0_CLK_MSO),"msi2" , 620 , R8A779A0_CLK_MSO),"msi3" , 621 , R8A779A0_CLK_MSO),"msi4" , 622 , R8A779A0_CLK_MSO),"msi5" , 623 , R8A779A0_CLK_MSO),"pwm0" , 628 , R8A779A0_CLK_S1D8),"rpc-if" , 629 , R8A779A0_CLK_RPCD2),"scif0" , 702 , R8A779A0_CLK_S1D8),"scif1" , 703 , R8A779A0_CLK_S1D8),"scif3" , 704 , R8A779A0_CLK_S1D8),"scif4" , 705 , R8A779A0_CLK_S1D8),"sdhi0" , 706 , R8A779A0_CLK_SD0),"sys-dmac1" , 709 , R8A779A0_CLK_S1D2),"sys-dmac2" , 710 , R8A779A0_CLK_S1D2),"tmu0" , 713 , R8A779A0_CLK_CL16MCK),"tmu1" , 714 , R8A779A0_CLK_S1D4),"tmu2" , 715 , R8A779A0_CLK_S1D4),"tmu3" , 716 , R8A779A0_CLK_S1D4),"tmu4" , 717 , R8A779A0_CLK_S1D4),"tpu0" , 718 , R8A779A0_CLK_S1D8),"vin00" , 730 , R8A779A0_CLK_S1D1),"vin01" , 731 , R8A779A0_CLK_S1D1),"vin02" , 800 , R8A779A0_CLK_S1D1),"vin03" , 801 , R8A779A0_CLK_S1D1),"vin04" , 802 , R8A779A0_CLK_S1D1),"vin05" , 803 , R8A779A0_CLK_S1D1),"vin06" , 804 , R8A779A0_CLK_S1D1),"vin07" , 805 , R8A779A0_CLK_S1D1),"vin10" , 806 , R8A779A0_CLK_S1D1),"vin11" , 807 , R8A779A0_CLK_S1D1),"vin12" , 808 , R8A779A0_CLK_S1D1),"vin13" , 809 , R8A779A0_CLK_S1D1),"vin14" , 810 , R8A779A0_CLK_S1D1),"vin15" , 811 , R8A779A0_CLK_S1D1),"vin16" , 812 , R8A779A0_CLK_S1D1),"vin17" , 813 , R8A779A0_CLK_S1D1),"vin20" , 814 , R8A779A0_CLK_S1D1),"vin21" , 815 , R8A779A0_CLK_S1D1),"vin22" , 816 , R8A779A0_CLK_S1D1),"vin23" , 817 , R8A779A0_CLK_S1D1),"vin24" , 818 , R8A779A0_CLK_S1D1),"vin25" , 819 , R8A779A0_CLK_S1D1),"vin26" , 820 , R8A779A0_CLK_S1D1),"vin27" , 821 , R8A779A0_CLK_S1D1),"vin30" , 822 , R8A779A0_CLK_S1D1),"vin31" , 823 , R8A779A0_CLK_S1D1),"vin32" , 824 , R8A779A0_CLK_S1D1),"vin33" , 825 , R8A779A0_CLK_S1D1),"vin34" , 826 , R8A779A0_CLK_S1D1),"vin35" , 827 , R8A779A0_CLK_S1D1),"vin36" , 828 , R8A779A0_CLK_S1D1),"vin37" , 829 , R8A779A0_CLK_S1D1),"vspd0" , 830 , R8A779A0_CLK_S3D1),"vspd1" , 831 , R8A779A0_CLK_S3D1),"rwdt" , 907 , R8A779A0_CLK_R),"cmt0" , 910 , R8A779A0_CLK_R),"cmt1" , 911 , R8A779A0_CLK_R),"cmt2" , 912 , R8A779A0_CLK_R),"cmt3" , 913 , R8A779A0_CLK_R),"pfc0" , 915 , R8A779A0_CLK_CP),"pfc1" , 916 , R8A779A0_CLK_CP),"pfc2" , 917 , R8A779A0_CLK_CP),"pfc3" , 918 , R8A779A0_CLK_CP),"tsc" , 919 , R8A779A0_CLK_CL16MCK),"vspx0" , 1028 , R8A779A0_CLK_S1D1),"vspx1" , 1029 , R8A779A0_CLK_S1D1),"vspx2" , 1030 , R8A779A0_CLK_S1D1),"vspx3" , 1031 , R8A779A0_CLK_S1D1),"fcpvx0" , 1100 , R8A779A0_CLK_S1D1),"fcpvx1" , 1101 , R8A779A0_CLK_S1D1),"fcpvx2" , 1102 , R8A779A0_CLK_S1D1),"fcpvx3" , 1103 , R8A779A0_CLK_S1D1),static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {907 ), /* RWDT */ /* * CPG Clock Data /* * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC * 14 13 (MHz) 21 31 * ---------------------------------------------------------------- * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16 * 0 1 20 x 1 x106 x180 x106 x120 x160 /19 * 1 0 Prohibited setting * 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14 )) >> 13 ) | \13 )) >> 13 ))static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4 ] __initconst = {/* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */ 1 , 128 , 1 , 192 , 1 , 16 , },1 , 106 , 1 , 160 , 1 , 19 , },0 , 0 , 0 , 0 , 0 , 0 , },2 , 128 , 1 , 192 , 1 , 32 , },static int __init r8a779a0_cpg_mssr_init(struct device *dev)const struct rcar_gen4_cpg_pll_config *cpg_pll_config;int error;if (error)return error;return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {/* Core Clocks */ /* Module Clocks */ 15 * 32 ,/* Critical Module Clocks */ /* Callbacks */
Messung V0.5 in Prozent C=93 H=96 G=94
¤ Dauer der Verarbeitung: 0.12 Sekunden
(vorverarbeitet am 2026-06-06)
¤ *© Formatika GbR, Deutschland
